This demo shows a toolbox for the optimization and automated high-level design of Analog-to-Digital Converters (ADCs). The tool integrates Artificial Neural Networks (ANNs) with behavioral simulation to optimize the high-level sizing process, mapping system-level specifications to building-block requirements. ANNs are trained to determine the optimal ADC architecture based on given specifications, as well as the ideal set of design parameters that meet these requirements. The ANN-generated designs are refined through iterative simulations to achieve the best figure of merit. The toolbox, applied to Sigma-Delta Modulators (Σ∆Ms), features a Graphical User Interface (GUI) implemented in MATLAB, which guides users through the entire process—from specifications to verification1

This demo shows how to use the You Only Look Once (YOLO) version 8 framework to identify radio-frequency (RF) signals for spectrum sensing in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, a trained YOLOv8 nano framework was embedded in an IoT device based on a Raspberry Pi 5 and connected to an ADALM-PLUTO SDR board to detect and classify the activity of RF frames around the industrial, scientific, and medical (ISM) frequency band. This framework detects wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real-time and can detect RF frames showing its potential application in SDR/CR terminals1.

This paper presents a Radio-Frequency (RF) spectrum prediction system based on a Convolutional Neural Network (CNN) architecture for image-based forecasting intended for Cognitive Radio (CR) terminals. Compared to previous approaches based on the use of time series, we propose a more efficient way for occupancy spectrum prediction based on channel availability tables (derived from spectrograms) to train a deep learning model. As a result, the neural engine is able to predict the best band available for Secondary User (SU) transmission in edge devices. As a proof of concept, a simple CR demonstrator combining a computational model for the neural engine – previously modeled and trained in Python using the Keras API – in MATLAB/SIMULINK with two Software-Defined Radio (SDR) boards has been developed. Three different table sizes were used as input for the predictor and a comparison is presented. The system performance is assessed using real over-the-air signals captured in the 2.412 GHz central frequency with 60 MHz bandwidth to validate the presented approach1.

This demo shows how to use Artificial Neural Networks (ANNs) for the optimization and automated design of analog and mixed-signal circuits. A step-by-step procedure is demonstrated to explain the key and practical aspects to consider in this approach, such as dataset preparation, ANNs modeling, training, and optimization of network hyperparameters. Two case studies at different abstraction levels are presented. The first one is the system-level sizing of Sigma-Delta Modulators (Σ∆Ms), where ANNs are combined with behavioral simulations to generate valid circuit-level design variables for a given set of specifications. The second example combines ANNs with electrical simulators to optimize the circuit-level design of operational transconductance amplifiers. The methods and tools shown in the demo can be used for the optimization of any arbitrary analog and mixed-signal integrated circuits and systems1.ISCAS Track: Analog Signal Processing.

This demo shows how to use Artificial Neural Networks (ANNs) to identify and predict the evolution of vacant portions or frequency holes of the radio spectrum with application in Software-Defined-Radio (SDR) and Cognitive-Radio (CR) systems. To this purpose, different kinds of ANNs – including Convolutional Neural Networks (CNNs), Long Short-Term Memory (LSTM) networks and hybrid combinations of them – are trained and tested with experimental datasets taken from measurements of the frequency spectrum. Trained ANNs are embedded in an IoT device based on a Rasperry Pi and connected with a SDR board to detect the activity of Radio-Frequency (RF) signals around the frequency band of 2.4GHz, shared by several wireless standards such as Bluetooth and WiFi. This hardware demonstrator operates in real time and is able to detect in advance which portions of this frequency band will be less occupied, thus showing their potential application in SDR/CR terminals1.ISCAS Track: Analog Signal Processing.

This paper presents a high-level synthesis methodology for Sigma-Delta Modulators ($\SD$Ms) that combines behavioral modeling and simulation for performance evaluation, and Artificial Neural Networks (ANNs) to generate high-level designs variables for the required specifications. To this end, comprehensive datasets made up of design variables and performance metrics, generated from accurate behavioral simulations of different kinds of$\SD$Ms, are used to allow the ANN to learn the complex relationships between design-variables and specifications. Several representative case studies are considered, including single-loop and cascade architectures with single-bit and multi-bit quantization, as well as both Switched-Capacitor (SC) and Continuous-Time (CT) circuit techniques. The proposed solution works in two steps. First, for a given set of specifications, a trained classifier proposes one of the available$\SD$M architectures in the dataset. Second, for the proposed architecture, a Regression-type Neural Network (RNN) infers the design variables required to produce the requested specifications. A comparison with other optimization methods – such as genetic algorithms and gradient descent – is discussed, demonstrating that the presented approach yields to more efficient design solutions in terms of performance metrics and CPU time.

This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation to different illumination conditions while preserving contrast is achieved by using a sensor chip, which implements an adaptive content-aware tone mapping compression algorithm by using in-pixel circuitry. Its response gets adapted to changing illumination conditions by using at each frame a statistical estimation of the light distribution, which is derived from the HDR histogram calculated at the previous frame. This method allows adaptive HDR video, while capable to capture very large DR scenes including moving objects.

This paper presents a QCIF HDR imager where visual information is simultaneously captured and adaptively compressed by an in-pixel tone-mapping scheme [1]. The tone mapping curve (TMC) is calculated from the histogram of an auxiliary previous image, which serves as a probability indicator of the distribution of illuminations within the current frame. The chip maps 148dB scenes onto 7-bit/pixel coding, containing illuminations from 2.2mlux (SNR10) to 55.33klux -with extreme values captured at 8s and 2.34µs, respectively. Pixels use an Nwell-Psubstrate photodiode and autozeroing for establishing the reset voltage. Measured sensitivity is 5.79 V over lux·s. Dark current effects in the final image are attenuated by an automatic programming of the DAC levels. The chip has been fabricated in the 0.35µm OPTO technology from AMS.

This paper describes a programmable digital computing architecture dedicated to process information in accordance to the organization and operating principles of the four-layer neuron structure encountered at the visual system of locusts. This architecture takes advantage of the natural collision detection skills of locusts and is capable of processing images and ascertaining collision threats in real-time automotive scenarios. In addition to the locust features, the architecture embeds a topological feature estimator module to identify and classify objects in collision course

This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. Due to its very advanced features and algorithmic capabilities, this chip has been demonstrated to be able to perform not only linear templates executions, but also to be very adequate for the implementation of non-linear templates by using a decomposition method. This paper focus on the application examples of the execution of non-linear templates with the CNNUC3 prototype. A brief description of the theoretical background is also presented in the paper.