Masahiro Sayano

dblp:98/4010 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Coding theory · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 67% Memory systems · 33%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Coding theory › error-correcting codes › block codes
array codes
0.011993
Phased burst error-correcting array codes · IEEE Trans. Inf. Theory 1993
Coding theory › error-correcting codes
burst error correction
0.011993
Phased burst error-correcting array codes · IEEE Trans. Inf. Theory 1993
Coding theory
error-correcting codes
0.011993
Phased burst error-correcting array codes · IEEE Trans. Inf. Theory 1993
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.011991
The reliability of semiconductor RAM memories with on-chip error-correction coding · IEEE Trans. Inf. Theory 1991
Memory systems
semiconductor memory
0.011991
The reliability of semiconductor RAM memories with on-chip error-correction coding · IEEE Trans. Inf. Theory 1991
Hardware reliability and fault tolerance
soft errors
0.011991
The reliability of semiconductor RAM memories with on-chip error-correction coding · IEEE Trans. Inf. Theory 1991

Methods — techniques the papers use, named apart from their topics

singleton bound · 0.0parity check construction · 0.0poisson approximation · 0.0markov modeling · 0.0
YearPublicationVenuePosition
1993 Phased burst error-correcting array codes
abstract
Various aspects of single-phased burst-error-correcting array codes are explored. These codes are composed of two-dimensional arrays with row and column parities with a diagonally cyclic readout order; they are capable of correcting a single burst error along one diagonal. Optimal codeword sizes are found to have dimensions n/sub 1/*n/sub 2/ such that n/sub 2/ is the smallest prime number larger than n/sub 1/. These codes are capable of reaching the Singleton bound. A new type of error, approximate errors, is defined; in q-ary applications, these errors cause data to be slightly corrupted and therefore still close to the true data level. Phased burst array codes can be tailored to correct these codes with even higher rates than before.>
Rodney M. Goodman, Robert J. McEliece, Masahiro Sayano
IEEE Trans. Inf. Theory3
1991 The reliability of semiconductor RAM memories with on-chip error-correction coding
abstract
The mean lifetimes are studied of semiconductor memories that have been encoded with an on-chip single error-correcting code along each row of memory cells. Specifically, the effects of single-cell soft errors and various hardware failures (single-cell, row, column, row-column, and entire chip) in the presence of soft-error scrubbing are examined. An expression is presented for computing the mean time to failure of such memories in the presence of these types of errors using the Poisson approximation; the expression has been confirmed experimentally to accurately model the mean time to failure of memories protected by single error-correcting codes. These analyses will enable the system designer to accurately assess the improvement in mean time to failure (MTTF) achieved by the use of error-control coding.>
Rodney M. Goodman, Masahiro Sayano
IEEE Trans. Inf. Theory2