This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.

We present a general multilayer area router for performing detailed routing in integrated circuits. This router is based on a novel grid construction scheme which considers the differing design rules of the routing layers and produces more wiring tracks than a uniform grid scheme. Our router is very general and flexible and is designed to handle all the physical constraints of a CMOS custom cell layout problem for an arbitrary number of routing layers. The router has been incorporated into the Custom Cell Synthesizer project at MCC. It has produced better results than uniform gridded routers and improved the capability of the system by providing routing flexibility and supporting features needed to handle a wide range of design styles in generating CMOS custom cells.

This paper presents a general multi-layer area router based on a novel grid construction scheme. The grid construction scheme produces more wiring tracks than the normal uniform grid scheme and accounts for differing design rules of the layers involved. Initial routing performed on the varying capacity grid is followed by a layer assignment stage. Routing completion is ensured by iterating local and global modifications in the layer assignment stage. Our router has been incorporated into the Custom Cell Synthesis project at MCC and has shown improved results for cell synthesis problems when compared with the router Mighty which was used in earlier versions of the project. spacing rules. (The general area routers such as Mighty(SI and Codar(6) can be used only in this way). This results in low utilization of wiring resources in the lower layers which usually have smaller spacing rules than the layers above. This router overcomes the shortcomings of gridded routers by using a novel approach to forming a virtual grid based on the design rules of each layer used in routing. Placement and routing of transistors are normally followed by a compaction stage which spaces the wires, vias and devices according to design rules. The grid is modelled with the knowledge that the layout will go through a compaction stage before the mask is generated. We use a model in which the tracks in the lower layers are denser than the tracks in the upper

The authors present a channel-ordering algorithm for VLSI layout with rectilinear modules. Existing approaches for layout with rectangular modules using only straight and L-shaped channels are no longer applicable. In general, rectilinear channels are needed. An important class of channels, called staircase channels, is introduced. This algorithm produces a feasible channel ordering which minimizes the usage of nonstaircase channels and minimizes the number of corners in a channel.>

A feasible channel-ordering algorithm for building-block layout using rectilinear blocks is presented. Existing approaches for layout with rectangular modules using only straight and L-shaped channels are no longer applicable. A class of channels called monotone channels is introduced. A monotone channel is a generalization of an L-shaped channel that has the form of a staircase. Routing is achieved by expanding the channel in both the horizontal and vertical directions. The algorithm produces a feasible channel order which minimizes the number of nonmonotone channels and the maximum number of corners in a channel used.>