Estimating the power consumption of System on Chip as early as possible in the design life cycle is important to meet the time to market requirements. For this purpose, most research is turning toward high-level models, like TLM, to estimate power earlier. This paper presents a high-level IP oriented power estimation methodology. The methodology separates the activity of the IP from the implementation. This allows the ability to easily create a model that can be used with different frequencies, layout and implementation technology. By using data gathered from the RTL a model can be created for high-level simulation that can take into account the technology and characteristics of the FPGA device. The methodology is presented in this paper with a processor and its local memory IP from Xilinx. Compared to estimations made at the RTL level, the resulting model gives accurate results of 15% with three to four order speedups and through different implementations.

A metric for the automatic determination of word lengths required for implementing DSP algorithms is proposed. The metric is capable of handling several error models computed between the fixed-point and the floating-point simulation results to model the impact of finite word lengths on the overall accuracy. It grades all the word-length combinations and guides a procedure towards the optimal solution. This metric was implemented in an automatic word-length determination tool to guide its search for better hardware implementations. It enables the creation of a framework for architecture and platform exploration.

A reformulated Adaptive Resonance Theory (ART) neural network algorithm has recently been implemented in digital hardware. Naturally, the fixed point, fixed word length data format used causes some output differences with respect to floating point computer simulation. These differences are observed when using realistic input data. The effects of input quantization and the accumulation of round off errors in the arithmetic operations making up the algorithm are analyzed. Even a small quantization or round off error can trigger a change in the clustering produced. This does not mean that the clustering is not valid. Indeed, the validity of the clustering can be comparable to that obtained by floating point computer simulation, provided the word length is sufficient. This is verified on realistic input data consisting of radar pulses received from a number of emitters.

The paper analyzes the performance differences found between software and hardware/sofware implementations of a reformulated fuzzy ART neural network algorithm. This reformulated algorithm is a solution for a real time radar signal clustering problem. The software implementations run on a 50 MHz TMS320C40 DSP, and the hardware/sofware implementation runs on the same DSP for its software part, whereas the FPGA based application specific hardware accelerator is realized on MiroTech's X-CIM TIM40 module. This investigation of FPGA based acceleration gave excellent results for our application: acceleration factors up to 68.9 have been reached.