This paper describes a test generation methodology that supports test generation for bridging faults in CMOS circuits using I/sub DDQ/ testing or quiescent supply current observation. A modular, hierarchical approach is used to handle large circuit sizes while maintaining an accurate representation of the structure of CMOS designs and fault mechanisms. The emphasis of this work is on the efficient generation of I/sub DDQ/ test sets that achieve very high fault coverage of unrestricted bridging faults, including both gate- and switch-level bridging faults, with reasonable computational requirements. An implementation of the approach supports all operations required for automatic test pattern generation, including fault sensitization, fault simulation, and test set compaction. Results are presented for tests of realistic bridging faults derived directly from the CMOS layouts of a set of benchmark circuits.>

Investigates linkages between physically realistic faults in CMOS integrated circuits and test generation and test quality. The procedure and results for an inductive fault analysis experiment that determined likely bridging faults in a set of CMOS circuits are presented. The implications of the results on test generation for physically realistic faults and on fault coverage are discussed.>

Explores the feasibility of using circuit partitioning approach to reduce the run-time complexity of test generation via parallel processing. Characterization of the major phases of test generation is used to show how the inherent parallelism existing in test generation can be exploited during forward implication and backward justification. Upper bounds on the concurrency available in specific are empirically determined by simulating the behavior of a 'perfect' conflict-free test generation algorithm that operates without backtracking. Results presented for a number of benchmark circuits indicate that the average available parallelism is fairly low, limiting the potential speedup of a circuit partitioning approach to test generation.>

The authors examine tests for short and open faults in CMOS circuits considering both IDDQ and logic observation test methods. Short and open faults are classified according to a topological classification that considers the type of fault, fault location, and affected transistor structure. The testability of each fault classification is considered for both optimistic and pessimistic assumptions. Circuit-level simulation is used to illustrate the classification.>

A graph-based solution to the mapping problem using the simulated annealing optimization heuristic is developed. An automated two-phase mapping strategy is formulated: process annealing assigns parallel processes to processing nodes, and connection annealing schedules traffic connections on network data links so that interprocess communication conflicts are minimized. To evaluate the quality of generated mappings. cost functions suitable for simulated annealing that accurately quantify communications overhead are derived. Communication efficiency is formulated to measure the quality of assignments when the optimal mapping is unknown. The mapping scheme is implemented using the hypercube as a host architecture, and results for several image graphs are presented.>