A novel and efficient method is presented for computing the delay and supply current pulse in a CMOS inverter with an RC load. The method builds on existing techniques for computing these quantities in the presence of a capacitance load. As in the work of other authors, the concept of an effective capacitance C/sub eff/ is used. However, here it captures the inverter's behavior only while the charging/discharging transistor is in saturation and, therefore, behaves like a current source to a good approximation. This capacitance is determined by means of a simple iterative procedure that uses an empirical piecewise-linear approximation to the RC circuit's output voltage, which has a normal CMOS symmetrical form. Since a C/sub eff/ defined in the above way is independent of the inverter's parameters, such as transistor size, the coefficients of the approximation have to be determined for only one reference inverter. A simple analytical method yields the inverter's output voltage outside the saturation region. The complete model has been shown to be accurate for both 0.8-/spl mu/m 5-V and 0.24-/spl mu/m 2.5-V CMOS technologies. Its speed is comparable to that of the "capacitance load" techniques that it relies on.

Quantitative workload characterization is essential to high performance computer architecture design. Unfortunately, quantitative results are typically hard to interpret, reproduce and compare, due to the staggering amount of detail inherent in modern architecture. Source language, compiler technology target ISA, and micro-architecture, intertwined with system aspects such as memory hierarchy and multitasking regime, all add to the complexity of workload characterization. We propose two simple metrics to characterize program execution: a footprint measures the "size" of a program, and a Unified Prediction profile shows its "complexity". These metrics are architecture-independent, and allow meaningful comparisons of program behavior at a numerical but abstract level. We believe they can provide direction to subsequent, more detailed and costly simulation efforts.