VLDB 2026 Research / reviewers in the wild / expert
S. A. Ali
dblp:98/6987
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › fault detection
fault detection probability |
0.0 | 1 | 1994 | Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits · IEEE Trans. Computers 1994 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1994 | Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits · IEEE Trans. Computers 1994 |
Electronic design automation › hardware verification and test
random testing |
0.0 | 1 | 1994 | Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits · IEEE Trans. Computers 1994 |
Electronic design automation › hardware verification and test
fault modeling |
0.0 | 1 | 1994 | Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits · IEEE Trans. Computers 1994 |
Methods — techniques the papers use, named apart from their topics
linear-time bound computation · 0.0dominance relations · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational CircuitsabstractA new technique for estimating a tight lower bound of the detection probabilities for single faults at any internal signal line in a combinational circuit for random testing is presented. This lower bound is calculated from the detection probabilities of all single faults at the primary input lines in a linear time. The technique relies on the relationship between the detection probabilities of dominating and dominated faults in the considered combinational circuit.> S. A. Ali, G. Robert Redinbo |
IEEE Trans. Computers | 1 |