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William W. Patterson

dblp:98/7753 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1974
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 46% Integrated circuit design · 46% Electronic design automation · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › asynchronous circuit design
asynchronous sequential machine
0.011974
A Fail-Safe Asynchronous Sequential Machine · IEEE Trans. Computers 1974
Integrated circuit design
digital circuit design
0.011974
A Fail-Safe Asynchronous Sequential Machine · IEEE Trans. Computers 1974
Hardware reliability and fault tolerance › design for reliability
fail-safe design
0.011974
A Fail-Safe Asynchronous Sequential Machine · IEEE Trans. Computers 1974
Hardware reliability and fault tolerance
fault-tolerant design
0.011974
A Fail-Safe Asynchronous Sequential Machine · IEEE Trans. Computers 1974
Electronic design automation › hardware verification and test
fault detection
0.011974
A Fail-Safe Asynchronous Sequential Machine · IEEE Trans. Computers 1974

Methods — techniques the papers use, named apart from their topics

state assignment · 0.0self-testing check circuit · 0.0
YearPublicationVenuePosition
1974 A Fail-Safe Asynchronous Sequential Machine
abstract
This paper examines the dynamic fault behavior of asynchronous sequential machines, specifically identifying the faults which cause critical races and hazards, and presents a state assignment technique leading to a machine that enters one of a small set of error states whenever a fault occurs. Entry into an error state can be checked by very simple check circuits; a self-testing check circuit and one requiring only two tests for fault detection are discussed. An extension of the state assignment technique to produce a machine that is fail-safe is also presented. The fail-safe design has the property that once a fault has caused the machine to malfunction and enter an error state, the machine never leaves the error state and therefore does not produce erroneous outputs. This machine detects all but a small class of multiple faults.
William W. Patterson, Gernot Metze
IEEE Trans. Computers1