Demo Data from VLDB 2026 / reviewers in the wild / expert
Duhee Lee
dblp:98/7790
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Storage systems · 55% Embedded and real-time systems · 34% Memory systems · 12% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
flash and SSD |
0.2 | 3 | 2011 | A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded Systems · RTSS 2009 Real-Time Program Execution on NAND Flash Memory for Portable Media Players · RTSS 2008 RT-PLRU: A New Paging Scheme for Real-Time Execution of Program Codes on NAND Flash Memory for Portable Media Players · IEEE Trans. Computers 2011 |
Storage systems › flash and SSD › flash memory
NAND flash |
0.2 | 3 | 2011 | A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded Systems · RTSS 2009 Real-Time Program Execution on NAND Flash Memory for Portable Media Players · RTSS 2008 RT-PLRU: A New Paging Scheme for Real-Time Execution of Program Codes on NAND Flash Memory for Portable Media Players · IEEE Trans. Computers 2011 |
Storage systems › flash and SSD
flash memory |
0.2 | 1 | 2013 | mRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash Memory · IEEE Trans. Computers 2013 |
Memory systems › memory management › virtual memory
paging |
0.1 | 1 | 2011 | RT-PLRU: A New Paging Scheme for Real-Time Execution of Program Codes on NAND Flash Memory for Portable Media Players · IEEE Trans. Computers 2011 |
Embedded and real-time systems
real-time scheduling |
0.1 | 1 | 2009 | A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded Systems · RTSS 2009 |
Embedded and real-time systems › real-time scheduling
schedulability analysis |
0.0 | 1 | 2013 | mRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash Memory · IEEE Trans. Computers 2013 |
Embedded and real-time systems
multitasking embedded system |
0.0 | 1 | 2009 | A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded Systems · RTSS 2009 |
Methods — techniques the papers use, named apart from their topics
stochastic analysis · 0.3convex optimization · 0.3real-time constrained optimization · 0.1pinning · 0.1LRU · 0.1pinning and LRU · 0.1paging mechanism · 0.1RT-PLRU · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | mRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash MemoryabstractThis paper proposes a novel technique called mRT-PLRU (Multitasking Real-Time constrained combination of Pinning and LRU), which forms a generic framework to use inexpensive nonvolatile NAND flash memory for storing and executing real-time programs in multitasking environments. In order to execute multiple real-time tasks stored in NAND flash memory with the minimal usage of expensive RAM, the mRT-PLRU is optimally configured in two steps. In the first step, the per-task analysis finds the function of RAM size versus execution time (and the corresponding optimal pinning/LRU combination) for each individual task. Using these functions for all the tasks as inputs, the second-step called a stochastic-analysis-in-loop optimization conducts an iterative convex optimization with the stochastic analysis for the probabilistic schedulability check. As a result, the optimization loop can optimally determine the RAM sizes for multiple tasks such that their deadlines are probabilistically guaranteed with the minimal size of total RAM. The usefulness of the developed technique is intensively verified through both simulation and actual implementation. Our experimental study shows that mRT-PLRU can save up to 80 percent of RAM required by the industry-common shadowing approach. Duhee Lee, Jongchan Kim 0001, Chang-Gun Lee, Kanghee Kim |
IEEE Trans. Computers | 1 |
| 2011 | RT-PLRU: A New Paging Scheme for Real-Time Execution of Program Codes on NAND Flash Memory for Portable Media PlayersabstractNAND flash memory has been widely used as a nonvolatile storage for storing data. However, it is challenging to execute program codes on NAND flash memory, since NAND flash memory only supports page-based reads, not byte-level random reads. This paper proposes an automated process to find the optimal paging strategy called RT-PLRU (Real-Time constrained combination of Pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of RAM. Moreover, the proposed process optimally configure the RT-PLRU in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a portable media player (PMP). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of RAM. Jongchan Kim 0001, Duhee Lee, Chang-Gun Lee, Kanghee Kim |
IEEE Trans. Computers | 2 |
| 2009 | A Generic Framework for Soft Real-Time Program Executions on NAND Flash Memory in Multi-Tasking Embedded SystemsabstractThis paper proposes a novel technique called mRT-PLRU (multi-tasking real-time constrained combination of pinning and LRU), which forms a generic framework to use inexpensive nonvolatile NAND flash memory for storing and executing real-time programs in multi-tasking environments. In order to execute multiple real-time tasks stored in NAND flash memory with the minimal usage of expensive RAM, the mRT-PLRU is optimally configured in two steps. In the first step, the per-task analysis finds the function of RAM size vs. execution time for each individual task. Using these functions for all the tasks as inputs, the second-step called a stochastic-analysis-in-loop optimization conducts an iterative convex optimization with the stochastic-analysis for the probabilistic schedulability check. As a result, the optimization loop can optimally allocate RAM to multiple tasks such that their deadlines are probabilistically guaranteed with the minimal usage of RAM. Moreover, the mRT-PLRU is optimally configured in a developer-transparent way without giving any burden to the program developer, which is essential for the embedded system industry under a high pressure of time-to-market. The usefulness of the developed technique is intensively verified through both simulation and actual implementation. Our experimental study shows that mRT-PLRU can save up to 80% of RAM required by the industry-common shadowing approach. Duhee Lee, Chang-Gun Lee, Kanghee Kim |
RTSS | 1 |
| 2008 | Real-Time Program Execution on NAND Flash Memory for Portable Media PlayersabstractNAND flash memory has been widely used as a non-volatile storage for storing data. However, it requires a large amount of SRAM for executing program codes stored in it since it only supports page-based reads, not byte-level random reads. This paper proposes a new paging mechanism called RT-PLRU (real-time constrained combination of pinning and LRU) that allows program codes stored in NAND flash memory to be executed satisfying real-time requirements with minimal usage of SRAM. Moreover, the RT-PLRU is optimally configured in a developer-transparent way without giving any burden to the program developer. The developed technique is specifically applied to a media player program targeting a PMP (portable medial player). To the best of our knowledge, this is the first effort to use NAND flash memory as a code storage for storing and executing real-time programs with minimal usage of SRAM. Jongchan Kim 0001, Duhee Lee, Chang-Gun Lee, Kanghee Kim, Eun Yong Ha |
RTSS | 2 |