A majority logic decoder made of unreliable logic gates, whose failures are transient and data-dependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for a one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit-flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.

In this paper we analyze the effect of hardware unreliability to performance of bit-flipping decoders of low-density parity-check (LDPC) codes. We apply expander arguments to show that the simple parallel bit flipping decoder, built partially from faulty gates, can correct a linear fraction of worst case channel errors, when gate failures are correlated and dependent on the switching activity of logic gates. In addition, we provide a lower bound on the guaranteed error correction of LDPC codes with left degree of at least eight.

We propose an iterative decoder made of a combination of faulty and perfect logic gates that is capable of correcting more channel errors than its counterpart made completely of perfect logic gates. We present an error probability analysis based on absorbing Markov chains, and explain how the randomness in the check node update function helps a decoder to escape to local minima associated with trapping sets. For the (155, 64) Tanner low-density parity check code, we provide a range of gate failure probabilities for which imperfect decoders perform better.

We give an architecture of a storage system consisting of a storage medium made of unreliable memory elements and an error correction circuit made of a combination of noisy and noiseless logic gates that is capable of retaining the stored information with the lower probability of error than a storage system with a correction circuit made completely of noiseless logic gates. Our correction circuit is based on the iterative decoding of low-density parity check codes, and uses the positive effect of errors in logic gates to correct errors in memory elements. In the spirit of Marcus Tullius Cicero's Clavus clavo eicitur (one nail drives out another), the proposed storage system operates on the principle: error errore eicitur-one error drives out another. The randomness that is present in the logic gates makes these classes of decoders superior to their noiseless counterparts. Moreover, random perturbations do not require any additional computational resources as they are inherent to unreliable hardware itself. To utilize the benefits of logic gate failures, our correction circuit relies on two key novelties: a mixture of reliable and unreliable gates and decoder rewinding. We present a method based on absorbing Markov chains for the probability of error analysis, and explain how the randomness in the variable and check node update function helps a decoder to escape to local minima associated with trapping sets.

We propose an improved version of probabilistic gradient descent bit flipping algorithm for decoding low density parity check codes, based on MUltiple Decoding attempts and Random re-Initializations (MUDRI). The proposed algorithm significantly increases the probability of correcting error patterns uncorrectable by the existing variants of bit-flipping algorithm. The performance of the algorithm implemented in noisy hardware is analyzed for various code types and codeword lengths, and shown to be superior compared to other hard decision algorithms. The MUDRI decoder is mostly insensitive to the failures in registers and logic gates and therefore represents a desirable solution for implementation in unreliable hardware.

In this paper, we analyze diversity reception of optical signals transmitted over terrestrial free-space optical (FSO) links. The irradiance fluctuations of the received signal are modeled by a Gamma-Gamma probability density function whose parameters are directly linked to propagation conditions. The switch-and-stay combining technique at the receiver is utilized for signal reception. Due to insufficient separation of photodiodes, there is a correlation between received signals at different branches. We analyze the effects of spatial signal correlation and switching threshold value on the outage probability. The analytical expression for outage probability is derived in the form of rapidly convergent series. The numerical results illustrate that spatial correlation causes penalty in electrical signal-to-noise ratio of about 5 dB for outage probability of 10-7. The results obtained here also show that proper selection of switching threshold can decrease the outage probability for an order of magnitude.

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

In this paper we present analysis of one-step majority logic decoders made of unreliable components in the presence of data-dependent gate failures. Gate failures are modeled by a Markov chain, and based on the combinatorial representation of the fault configurations, a closed-form expression for the average bit error rate is derived for a regular LDPC code ensemble. Presented analysis framework is then used for obtaining upper bounds on decoding performance under timing errors.

Spectrum sharing cognitive radio with multiple antennas at the primary user receiver and maximal ratio combining applied at the secondary user receiver is analyzed. The closed-form expression is derived for the ergodic capacity of the secondary link with an arbitrary number of receive antennas and Nakagami fading distribution. Analytical expressions are derived for both cases of peak and average interference constraint at the primary user receiver. The correctness of analytical results is verified by using an independent simulation model.

In this study, exact closed-form expressions for the second-order statistics of the signal-to-noise ratio at a maximum ratio combiner (MRC) output for a Nakagami fading channel are derived. Using the joint characteristic function for the MRC output and its time derivative, the level crossing rate, average fading duration and autocorrelation function expressions are derived for the case of independent but unbalanced diversity branches, with unequal fading parameters and an arbitrary number of diversity branches. The analytical results are validated by simulations.

The second-order statistics of the time varying signal to noise ratio at the output of a multiple-input-multiple-output(MIMO) system with maximal ratio combining (MRC) are analyzed. Exact closed-form expressions for the level crossing rate and the average fade duration are derived for the Ricean propagation and arbitrary channel matrix dimensions. Novel expressions are compared with the special case of MRC receive diversity. The analytical results are validated by simulation.

An analytical method for the performance evaluation of adaptive multiple-input-multiple-output (MIMO) system employing maximal ratio combining (MRC) by a Markov model is developed. The finite state Markov channel model parameters were determined by a new exact expression for level crossing rate of the signal to noise ratio at the output of MIMO-MRC with imperfect channel state information, derived for the Rayleigh propagation and arbitrary channel matrix dimensions. The analytical results are validated by computer simulation.

Several classes of low-density parity-check (LDPC) codes are proposed as an error control coding (ECC) scheme for a non-linear satellite system with the phase-shift keying (PSK) signaling. The bit-error rate (BER) performance of LDPC codes is determined by means of an advanced simulator that takes into account all major impairments in the transmission link between fixed ground stations over a non-regenerative geostationary (GEO) satellite. Our analysis includes the following impairments: the degradations caused by simultaneous influences of cross- polarization effects, undesired signals from neighboring satellite systems or terrestrial radio-relay links and phase noise produced by local oscillator at the satellite station and reference signal extractor at the receiving ground station. The proposed LDPC codes are compared against standard ECC schemes employed in modern satellite communication systems.