This paper presents two improved modular multiplication algorithms: variable length Interleaved modular multiplication (VLIM) algorithm and parallel modular multiplication (P_MM) method using variable length algorithms to achieve high throughput rates. The new Interleaved modular multiplication algorithm applies the zero counting and partitioning algorithm to a multiplier’s non-adjacent form (NAF). It divides this input into sections with variable-radix. The sections include a digit of zero sequences and a non-zero digit (-1 or 1) in the most valuable place. Therefore, in addition to reducing the number of required clock pulses, high-radix partial multiplication$\mathbf{X}^{\left(\mathbf{i}\right)}\cdot \mathbf{Y}$is simplified and performed as a binary addition or subtraction operation, and multiplication operations for consecutive zero bits are executed in one clock cycle instead of several clock cycles. The proposed parallel modular multiplication algorithm divides the multiplier into two parts. It utilizes (VLIM) and variable length Montgomery modular multiplication (VLM3) methods to compute the modular multiplication for the upper and lower portions in parallel, according to the proximity of their multiplication time. The implementation results on a Xilinx Virtex-7 FPGA show that the parallel modular multiplication computes a 2048-bit modular multiplication in 0.903 µs, with a maximum clock frequency of 387 MHz and area × time per bit value equal to 9.14.

The Social Spider Algorithm (SSA) was introduced based on the information-sharing foraging strategy of spiders to solve the continuous optimization problems. SSA was shown to have better performance than the other state-of-the-art meta-heuristic algorithms in terms of best-achieved fitness values, scalability, reliability, and convergence speed. By preserving all strengths and outstanding performance of SSA, we propose a novel algorithm named Discrete Social Spider Algorithm (DSSA), for solving discrete optimization problems by making some modifications to the calculation of distance function, construction of follow position, the movement method, and the fitness function of the original SSA. DSSA is employed to solve the symmetric and asymmetric traveling salesman problems. To prove the effectiveness of DSSA, TSPLIB benchmarks are used, and the results have been compared to the results obtained by six different optimization methods: discrete bat algorithm (IBA), genetic algorithm (GA), an island-based distributed genetic algorithm (IDGA), evolutionary simulated annealing (ESA), discrete imperialist competitive algorithm (DICA) and a discrete firefly algorithm (DFA). The simulation results demonstrate that DSSA outperforms the other techniques. The experimental results show that our method is better than other evolutionary algorithms for solving the TSP problems. DSSA can also be used for any other discrete optimization problem, such as routing problems.

Abstract This paper presents and evaluates an advance hybrid key management architecture for supervisory control and data acquisition (SCADA) networks (HSKMA), which supports all three types of communications: unicast, multicast, and broadcast. The HSKMA is based on the elliptic curve cryptography and symmetric cryptography. While the elliptic curve cryptography is used for communication between master station unit (MSU) and sub‐MSUs, the symmetric cryptographic algorithm is used for communication between sub‐MSUs and slave stations that have limited computational resources. Our analysis shows that the HSKMA has the following distinctive advantages: 1) it supports the security requirement such as availability, forward security, and backward security, 2) it supports the required speed in the MODBUS implementation, and 3) it is suitable for the environments that have limited computational resources. Copyright © 2016 John Wiley & Sons, Ltd.

Modular exponentiation with a large modulus and exponent is a fundamental operation in many public-key cryptosystems. This operation is usually accomplished by repeating modular multiplications. Montgomery modular multiplication has been widely used to relax the quotient determination. The carry-save adder has been employed to reduce the critical path. This paper presents and evaluates a new and efficient Montgomery modular multiplication architecture based on a new digit serial computation. The proposed architecture relaxes the high-radix partial multiplication to a binary multiplication. It also performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles. Moreover, the right-to-left and left-to-right modular exponentiation architectures have been modified to use the proposed modular multiplication architecture as its structural unit. We provide the implementation results on a Xilinx Virtex 5 FPGA demonstrating that the total computation time and throughput rate of the proposed architectures outperform most results so far in the literatures.