Demo Data from VLDB 2026 / reviewers in the wild / expert
Kenneth Skovhede
dblp:98/8353
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2019
0000-0003-0265-1248ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis › hardware generation
hardware description language generation |
0.4 | 1 | 2019 | Building FPGA State Machines from Sequential Code · FPGA 2019 |
Electronic design automation
high-level synthesis |
0.4 | 1 | 2019 | Building FPGA State Machines from Sequential Code · FPGA 2019 |
Electronic design automation › high-level synthesis
VHDL generation |
0.4 | 1 | 2019 | Building FPGA State Machines from Sequential Code · FPGA 2019 |
Methods — techniques the papers use, named apart from their topics
transpilation · 0.4sequential code transformation · 0.4await construct · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Building FPGA State Machines from Sequential CodeabstractState machines are commonly used and well understood for hardware. However, in some cases they can introduce complexity as the program can no longer be read sequentially. We propose an extension to the SME model, which retains the sequential program structure, by using a barrier-like 'await' construct to divide a program into states. This is done by awaiting a predicate, ensuring that the sequential program does not progress until the predicate is satisfied. This initial implementation enables the clock signal as a predicate, allowing for easy partitioning of the sequential program, which is a common approach when either pipelining or sequencing a problem. Future implementations will also enable functions or signal values as predicates. The signal values will be a simple to use barrier when waiting for external input. As for the functions, it handles all the communication regarding input/output for and synchronization with the function. As always with the SME model, the problems implemented in the model can be transpiled into VHDL along with a VHDL test bench, which verifies that the generated VHDL matches the SME simulation. Our preliminary results shows that Xilinx Vivado recognises the state machines and that the SME simulation is clock cycle accurate to the simulation of the generated VHDL. Furthermore, we see reduced resource consumption and higher clock rates, as we should by leveraging state machines, without increasing the complexity and readability of the original program. Carl-Johannes Johnsen, Kenneth Skovhede |
FPGA | 2 |
| 2009 | Distributed Shared Memory for the Cell Broadband Engine (DSMCBE)abstractThe CELL-BE processor provides high performance and has been shown to reach a performance close to the theoretical peak, however, the high performance comes at the price of a quite complex programming model. Central to the complexity of the CELL-BE programming model is the need to move data in and out of non-coherent local storage blocks for each special processor element. In this paper we present a software library, namely the distributed shared memory for the cell broadband engine (DSMCBE). By using techniques known from distributed shared memory DSMCBE allows programmers to program the CELL-BE with relative ease and in addition scale their applications to use multiple CELL-BE processors in a network. Performance experiments show that a quite high performance can be obtained with DSMCBE even in a cluster environment. Morten N. Larsen, Kenneth Skovhede, Brian Vinter |
ISPDC | 2 |