The computing landscape has been increasingly characterized by processor architectures with increasing core counts, while a majority of the software applications remain inherently sequential. Although state-of-the-art compilers feature sophisticated optimizations, a significant chunk of wasteful computation persists due to the presence of data-dependent operations and irregular control-flow patterns that are unpredictable at compile-time. This work presents speculative code compaction (SCC), a novel microarchitectural technique that significantly enhances the capabilities of the microcode engine to aggressively and speculatively eliminate dead code from hot code regions resident in the micro-op cache, and further generate a compact stream of micro-ops, based on dynamically predicted machine code invariants. SCC also extends existing micro-op cache designs to co-host multiple versions of unoptimized and speculatively optimized micro-op sequences, providing the fetch engine with significant flexibility to dynamically choose from and stream the appropriate set of micro-ops, as and when deemed profitable.SCC is a minimally-invasive technique that can be implemented at the processor front-end using a simple ALU and a register context table, and is yet able to substantially accelerate the performance of already compile-time optimized and machine-tuned code by an average of 6% (and as much as 30%), with an average of 12% (and as much as 24%) savings in energy consumption, while eliminating the need for profiling and offering increased adaptability to changing datasets and workload patterns.

In-memory database management systems (DBMSs) outperform disk-oriented systems for on-line transaction processing (OLTP) workloads. But this improved performance is only achievable when the database is smaller than the amount of physical memory available in the system. To overcome this limitation, some in-memory DBMSs can move cold data out of volatile DRAM to secondary storage. Such data appears as if it resides in memory with the rest of the database even though it does not.

This paper presents BigDAWG, a reference implementation of a new architecture for "Big Data" applications. Such applications not only call for large-scale analytics, but also for real-time streaming support, smaller analytics at interactive speeds, data visualization, and cross-storage-system queries. Guided by the principle that "one size does not fit all", we build on top of a variety of storage engines, each designed for a specialized use case. To illustrate the promise of this approach, we demonstrate its effectiveness on a hospital application using data from an intensive care unit (ICU). This complex application serves the needs of doctors and researchers and provides real-time support for streams of patient data. It showcases novel approaches for querying across multiple storage engines, data visualization, and scalable real-time analytics.

Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we try to mitigate the conflicting design and test requirements using an integrated approach to design and test that utilizes the existing low power and error resilient design techniques and augments them to improve test coverage and cost. Simulation results on an example 8×8 Wallace tree multiplier in 90nm technology node show 20% reduction in operating power, 60% reduction in test power and 99% reduction in critical paths while at the same time improving the yield from 96% to 100%, compared to existing design and test methodologies. All this comes at the cost of a marginal increase in area (7.8%).

Process technology advancements continue to provide designers with more transistors to utilize. In the past, this took the form of designers seeking novel techniques to support the exponential growth of clock frequency scaling. Today, clock frequency scaling has tapered and yet design is still expected to extract value from these additional transistors in the form of better performance and more functionality while staying within a required power envelope. This talk will discuss these trends including the move towards multi-core designs. This talk will also discuss deficiencies in our current design and test methodologies needed to support this and will conclude with challenges that face industry which could be addressed by university research.

In the past, processor design trends were dominated by increasingly complex feature sets, higher clock speeds, growing thermal envelopes and increasing power dissipation. Recently, clock speeds have tapered and thermal and power dissipation envelopes have remained flat. However, the demand for increasing performance continues which has fueled the move to integrated multiple processor (multi-core) designs. This paper discusses this trend towards multi-core processor designs, the design challenges that accompany it and a view of the research required to support it.

Transistor density on an integrated circuit continues to grow at an exponential rate. The associated complexities when applied to synthesis, layout, and timing analysis will become untenable within the framework of our current technological capabilities. This paper briefly outlines the problems facing the semiconductor industry early into the next decade. A SRC research thrust team consisting of members from various companies prioritized these problems and established a top ten list. This paper includes both problem descriptions as well as metrics to benchmark proposed solutions.