The most advanced solutions that are currently adopted in ports and terminals use technologies based on radio frequency identification (RFID) and the Global Positioning System (GPS) to identify and localize shipping containers in the yard. Nevertheless, because of the limitations of these solutions, the position of containers is still affected by errors, and it cannot be determined in real time. In this paper, a nonconventional approach is presented: Each container is equipped with nodes that use wireless communication to detect neighbor containers and to send proximity information to a base station. At the base station, geometrical constraints and proximity data are combined to determine the positions of containers. Missing information due to faulty nodes is tolerated by modeling geometrical constraints as an integer linear programming problem. Numerical simulations show that most of the containers can be localized, even when the number of nodes that are affected by faults is on the order of 30%.

Falls are a major cause of hospitalization and injury-related deaths among the elderly population. The detrimental effects of falls, as well as the negative impact on health services costs, have led to a great interest on fall detection systems by the health-care industry. The most promising approaches are those based on a wearable device that monitors the movements of the patient, recognizes a fall and triggers an alarm. Unfortunately such techniques suffer from the problem of false alarms: some activities of daily living are erroneously reported as falls, thus reducing the confidence of the user. This paper presents a novel approach for improving the detection accuracy which is based on the idea of identifying specific movement patterns into the acceleration data. Using a single accelerometer, our system can recognize these patterns and use them to distinguish activities of daily living from real falls; thus the number of false alarms is reduced.

Wireless sensor networks are moving from academia to real world scenarios. This will involve, in the near future, the design and production of hardware platforms characterized by low-cost and small form factor. As a consequence, the amount of resources available on a single node, i.e. computing power, storage, and energy, will be even more constrained than today. This paper faces the problem of storing and executing an application that exceeds the memory resources available on a single node. The proposed solution is based on the idea of partitioning the application code into a number of opportunistically cooperating modules. Each node contributes to the execution of the original application by running a subset of the application tasks and providing service to the neighboring nodes.

One of the critical aspects of clustering algorithms is the correct identification of the dissimilarity measure used to drive the partitioning of the data set. The dissimilarity measure induces the cluster shape and therefore determines the success of clustering algorithms. As cluster shapes change from a data set to another, dissimilarity measures should be extracted from data. To this aim, we exploit some pairs of points with known dissimilarity value to teach a dissimilarity relation to a feed-forward neural network. Then, we use the neural dissimilarity measure to guide an unsupervised relational clustering algorithm. Experiments on synthetic data sets and on the Iris data set show that the relational clustering algorithm based on the neural dissimilarity outperforms some popular clustering algorithms (with possible partial supervision) based on spatial dissimilarity.

Abstract The exploitation of the salient features of capability‐based addressing environments leads to a high number of small objects existing in memory at the same time. It is thus necessary to enhance the efficiency of the mechanisms for object relocation, and to avoid congestion of input/output devices due to swapping. In this paper, we present an approach to the management of a large virtual memory space aimed at solving these problems. We insert partial information concerning the physical allocation of each object into the virtual identifier of this object. Objects are grouped into large swapping units, called pages. The page size is independent of the average object size. This results in enhanced efficiency in managing the relocation information both with regard to memory requirements and access times. The allocation of objects into pages, and the movement of pages through the memory hierarchy, are controlled by user processes. This means that programs which have knowledge of their own use of virtual memory can increase their locality of reference, diminish the number of swap operations and reduce fragmentation.

Multiple processor architectures can be used to speed up the execution of logic programs, as they allow the exploitation of appropriate forms of OR–AND parallelism. In this paper we refer to distributed systems in which nodes are connected by means of point-to-point links, and information exchanges between processes are accomplished by message passing alone. The number of nodes is supposed to be not too large, and the memory of each node not sufficient to store all the database. A parallel interpreter for logic programs is proposed in which the parallelism exploited is not the maximum one and consists of the classical OR parallelism paired with an appropriate form of AND parallelism (‘backtracking parallelism’). The solutions are evaluated in the same order as a classical sequential depth-first interpreter.

The problem of implementing abstract objects in a system having a capability based addressing is analysed in some detail. Hardware features needed to support a classical capability environment are first pointed out, and a simple implementation of abstract objects is presented. Then a generalization of the classical capability environment is given, which allows one to solve the stated problem in a more efficient way.

Abstract In this paper a capability addressing environment is presented, based on the concept of extended capability. First of all it is shown that such an environment is well suited for implementing objects of abstract type. Then the problem of distributing and revoking access authorizations on abstract objects is considered and an efficient solution is presented. The revocation mechanism results in being selective, transitive and deferred.

In this work the generalized discrete Fourier transform (GFT), which includes the DFT as a particular case, is considered. Two pairs of fast algorithms for evaluating a multidimensional GFT are given (T-algorithm, F-algorithm, and T′-algorithm, F′-algorithm). It is shown that in the case of the DFT of a vector, the T-algorithm represents a form of the classical FFT algorithm based on a decimation in time, and the F-algorithm represents a form of the classical FFT algorithm based on decimation in frequency. Moreover, it is shown that the T′-algorithm and the T-algorithm involve exactly the same arithmetic operations on the same data. The same property holds for the F′-algorithm and the F-algorithm. The relevance of such algorithms is discussed, and it is shown that the T′-algorithm and the F′-algorithm are particularly advantageous for evaluating the DFT of large sets of data.

The structure of the Processing Element (PE), which is the basic component of SMA1, is presented. The PE consists of a simple serial arithmetic unit, a local high speed data memory, serial input and output ports, serial communication channels with neighbouring PE's, and some local control logic. The PE array operates under the control of a microprogrammed Array Control Unit (ACU). The peculiarities of ACU microprogramming are discussed, and some typical microprograms are reported. After presentation of the SMA principal instructions, some application programs are described implementing common radar filtering algorithms.

In this correspondence the problem of performing the multiplication by recoding the multiplier is considered. A special recoding for fractional numbers in two's complement form is presented, that generates a class of uniform shift multiplication algorithms having the property that every partial product is always in the open interval (-1,1). Both the scan of the multiplier from the least to the most significant bit and the scan in the opposite direction are considered.