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Denis Deschacht

dblp:99/5249 · DBLP profile ↗
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5ranked-venue papers
4as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 64% Performance modeling and evaluation · 28% Integrated circuit design · 8%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › simulation
discrete-event simulation		 0.011993
Post-layout timing simulation of CMOS circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › circuit simulation › timing simulation
post-layout timing simulation		 0.011993
Post-layout timing simulation of CMOS circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation
timing analysis		 0.011993
Post-layout timing simulation of CMOS circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › circuit modeling
delay characterization		 0.011993
Post-layout timing simulation of CMOS circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Integrated circuit design › digital circuit design › CMOS circuit design
digital CMOS circuits		 0.011993
Post-layout timing simulation of CMOS circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993

Methods — techniques the papers use, named apart from their topics

two-pass algorithm · 0.0conduction path extraction · 0.0
YearPublicationVenuePosition
2006 DSM interconnects: importance of inductance effects and corresponding range of length
abstract
To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-mum technology
Denis Deschacht
 IEEE Trans. Very Large Scale Integr. Syst.1
2001 On-chip interconnections: impact of adjacent lines on timing
abstract
As the CMOS technology scales down, the coupling capacitance between adjacent wires plays dominant part in wire load and interference becomes a serious problem for VLSI design. In this paper, we focus on delay increase caused by adjacent lines. This increase in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. We propose an analytical expression to compute the delay in the presence of coupling that takes explicitly into account interconnect resistance and capacitance, driver resistance and relative driver strengths.
Denis Deschacht, Grégory Servel
 ASP-DAC1
1995 A new and accurate interconnection delay time evaluation in a general tree-type network
abstract
No abstract available.
Denis Deschacht, Christophe Dabrin
 ASP-DAC1
1993 Post-layout timing simulation of CMOS circuits
abstract
As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes only transitions with gates controlled by events. Extraction of conduction paths from a general decomposition of data paths in unidirectional blocks allows general conflictual situations to be solved. Configuration problems detected during the evaluation, such as pulse rejection and strength conflicts, are illustrated, and effective solutions of conflictual configurations are given. It is shown that the implementation of a two-pass algorithm results in a significant improvement of speed. Execution times have been found to be nearly linear with the node numbers. Comparison of simulation times obtained from other timing simulators is given. SPICE compatibilities of PATH-RUNNER allow automatic real characterization of data paths from post-layout extracted net lists, with SPICE-like accuracy for evaluation of delays on real structures.>
Denis Deschacht, Michel Robert, Nadine Azémard, Daniel Auvergne
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1991 TVA: A timing verifier with analytic temporal modelling
D. Navarro, Michel Robert, Denis Deschacht, Daniel Auvergne
 Microprocessing and Microprogramming4