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Shiuann-Shiuh Lin

dblp:99/5250 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 70% Reconfigurable computing and FPGAs · 23% Interconnection networks and networks-on-chip · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA-based emulation
0.011997
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › physical design › routing › detailed routing
net assignment
0.011997
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation
physical design
0.011997
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Electronic design automation › physical design
routing
0.011997
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997
Interconnection networks and networks-on-chip › switching network › multistage interconnection network
folded-clos network
0.011997
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997

Methods — techniques the papers use, named apart from their topics

two-phase approach · 0.0heuristic algorithm · 0.0exact algorithm · 0.0
YearPublicationVenuePosition
1999 A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning
abstract
The spectral method can lead to a high quality of multi-way partition due to its ability to capture global netlist information. For spectral partition, n netlist modules are mapped to n points in d-dimensional space, and then a linear ordering of these n modules is constructed to be used as a basis for partitioning. In this paper, we propose two clustering based linear ordering algorithms taking into consideration the objective function presented.
Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang
ASP-DAC1
1997 Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure
abstract
In this paper, we study the net assignment problem for a logic emulation system in the folded-Clos network interconnection, also referred to as the "partial crossbar interconnection structure". Net assignment of two-terminal nets in this interconnection structure is guaranteed to be completed in polynomial time. However, net assignment of multiterminal nets becomes NP-complete. A previous paper by Butts et al. (1992) has proposed a simple heuristic to perform net assignment for multiterminal nets. Its results showed that it failed to complete routing of all nets for many cases. It is inadequate to have a net assignment algorithm which does not guarantee an exact solution, as the failure of interconnecting field programmable gate arrays (FPGA's) will result in the failure of mapping to the computing engine as a whole and will result in redoing the previous steps, e.g., partitioning of circuits. Therefore, we propose an exact algorithm to solve the net assignment problem. The exact algorithm will find a solution if one exists. However, the exact algorithm may take exponential time. Accordingly, a two-phase approach is taken in this paper. A time-efficient heuristic method is used first. The exact solver will be called only if the heuristic fails to deliver a solution.
Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1