This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential machines. This allows the application of arbitrary two-vector test sets necessary for delay fault testing. This arrangement is feasible for practical circuits because today's complex ICs consist, in general, of many sequential machines that may need to be delay testable.

We present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using differential cascode voltage switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an application specific integrated circuit that can be used to implement a variety of fault-tolerant architectures including triple modular redundant and hybrid configurations. The unit is capable of detecting and correcting failures in the redundant modules by monitoring their respective buses, and it delivers fault-free data to the destination modules. The unit is also capable of detecting faults occurring in the unit itself by utilizing the fault secure properties of DCVS logic. In this paper, we present the operation of the bus-monitor unit and we describe its DCVS design and implementation, as well as the performance characteristics of the prototype chips. Finally, we illustrate how the bus-monitor unit(s) can be used to implement highly reliable fault-tolerant architectures, and we demonstrate that architectures designed using the developed unit(s) exhibit higher reliability compared to the ones implemented with CMOS logic, using the same number of computational resources.>

Presents a new approach to testing board interconnects, on a board containing three-state nets and with chips equipped with the boundary scan architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, the authors have concentrated on the walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of walking 1/0 in linear time.>

A technique for designing self-checking circuits using differential cascode voltage switch (DCVS) logic is presented. This technique is used in a design case study and the results obtained through actual implementation and testing of a self-checking circuit are discussed. It is demonstrated that the self-checking capability of the circuit can be used to implement fault tolerance at low hardware-overhead costs.>

To facilitate the design of high performance digital ASICs, the Research Triangle Institute (RTI) is developing a library of common digital signal processing macrocells for use in a silicon compilation environment. In many types of digital ASICs (especially signal processing applications), VLSI circuits are composed of a basic set of high-level functions which are used in different configurations. Examples of these functions are adders, registers, memories, multiplexers, and multipliers. By developing a robust library of parameterized functions, significant reductions in design time and costs can be achieved. A complete list of macrocells slated for development by RTI is shown. This list is meant to complement RAM, ROM, and PLA generators already available through Mentor-Graphics.>

A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.>