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Dhiren Xavier

dblp:99/6199 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
aliasing
0.011992
Using an asymmetric error model to study aliasing in signature analysis registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.011992
Using an asymmetric error model to study aliasing in signature analysis registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
hardware verification and test
0.011992
Using an asymmetric error model to study aliasing in signature analysis registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › random testing
pseudorandom testing
0.011992
Using an asymmetric error model to study aliasing in signature analysis registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › hardware verification and test › test response compaction
signature analysis
0.011992
Using an asymmetric error model to study aliasing in signature analysis registers · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

independent error model · 0.0asymmetric error model · 0.0
YearPublicationVenuePosition
1995 A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes
D. Lambidonis, Vinod K. Agarwal, André Ivanov, Dhiren Xavier
J. Electron. Test.4
1992 Using an asymmetric error model to study aliasing in signature analysis registers
abstract
Recent predictions about the aliasing behavior of linear feedback shift registers used in signature analysis with pseudorandom testing are validated experimentally. It is shown that the independent error model accurately predicts aliasing in these signature registers when test sets are selected at random. In practice, however, a circuit's test set is fixed, and it is shown that adopting a more general asymmetric error model, of which the independent is a special case, yields more accurate aliasing information, especially in the dynamic or non-steady-state region of the aliasing profile. The only additional information needed to apply the asymmetric model to signature analysis is the fault-free sequence. Since this sequence is needed in any case to compute the fault-free signature, the model can reflect test set ordering at no extra cost.>
Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1989 : Experiments on Aliasing in Signature Analysis Registers
abstract
An effort is made to validate experimentally predictions on aliasing in signature analysis registers under the independent error model. From the experimental results it appears that the independent error model accurately predicts the probability of aliasing in signature registers. The authors also provide justification for the adoption of a more general asymmetric error model of which the former is a special case; the latter can be used at no extra cost. Among the potential benefits in using the asymmetric error model is the subdivision of faults into classes based on pD and pDbar, the conditional probability, respectively, of the fault-free bit being 1 and the faulty bit being 0 and vice versa, whereby faults in a given class have the same probability of aliasing. Under the independent error model fault classification is based on a single parameter p. Use of an asymmetric model hence provides a better resolution in terms of the classification of faults based on aliasing probability. Experimental results also indicate that considering the asymmetric nature of circuit outputs yields more useful information, especially in the dynamic region of the aliasing curve.>
Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal
ITC1