This paper presents a novel and flexible modeling technique to generate accurate linear and nonlinear driver models with applications in timing and noise analysis. The new technique, based on Galerkin's finite elements method, is very efficient because it relies on existing logic block characterization for timing, does not require additional nonlinear circuit simulations during modeling, and generates reusable models. The performance of the proposed modeling technique is exemplified in two different implementations: nonlinear driver models for delay noise analysis and piece-wise linear driver models for static-timing analysis.

We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of the design process. A case study showing the application of this methodology to the PowerPC™ 750 microprocessor is presented.

The Elmore delay is an extremely popular timing-performance metric which is used at all levels of electronic circuit design automation, particularly for resistor-capacitor (RC) tree analysis. The widespread usage of this metric is mainly attributable to it being a delay measure that is a simple analytical function of the circuit parameters. The only drawback to this delay metric is the uncertainty of its accuracy and the restriction to it being an estimate only for the step response delay. In this paper, we prove that the Elmore delay measure is an absolute upper bound on the actual 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore metric as we use it as a performance metric for design automation.

Most timing simulators obtain their efficiency over circuit simulation in terms of explicit integration algorithms that have dif-ficulty handling the stiff RC circuit models which characterize interconnect-dominated paths. In this paper we describe a reduced-order N-port interconnect macromodel for timing simula-tion. This macromodel is shown to improve the timing simulation efficiency dramatically since it alleviates the stiff circuit problem. Moreover, through its compatibility with the simple timing simula-tion transistor models, it is shown that this macromodel does not suffer from the dramatic increase in complexity with an increase in the number of ports like circuit simulation. I.

Due to its simplicity, the ubiquitous Elmore delay, or first moment of the impulse response, has been an extremely popular delay metric for analyzing RC trees and meshes. Its inaccuracy has been noted however and it has been demonstrated that higher order moments can be mapped to dominant pole approximations (e.g. AWE) in the general case. The first three moments can be mapped to a two pole approximation, but stability is an issue and even a stable model results in a transcendental equation that must be iteratively evaluated to determine the delay. We describe an explicit delay approximation based on the first three moments of the impulse response. We begin with the development of a provably stable two pole transfer function/impedance model based on the first three moments (about s=0) of the impulse response. Then, since the model form is known, we evaluate the delay (any waveform percentage point) in terms of an analytical approximation that is consistently within a fraction of 1 percent of the exact solution for this model. The result is an accurate, explicit delay expression that will be an effective metric for high speed interconnect circuit models.

The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis.The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters.The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation.In this paper, we prove that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response.Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases.A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response.The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation.