In this paper, efficient built-in self-repair (BISR) techniques for multiple repairable memory cores with different sizes and divided redundancy mechanisms are proposed. Embedded memory cores are first partitioned into memory groups. For each memory group, a redundant memory module is added and divided into row blocks and column blocks. Moreover, the memory cores within a memory group are partitioned into divided arrays (consisting of row/column blocks) of the same size. The redundant memory can be shared among all memory cores within the same memory group. Therefore, unlike the traditional redundancy architectures, a row (column) block is used as the basic replacement element. Based on the proposed redundancy architecture, a heuristic heterogeneous extended spare pivoting redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that the repair rate and manufacturing yield can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example memory group consisting of four memory instances of size 9.25 Mbits is only 1.12%.

In this paper, BISR (built-in self-repair) techniques for heterogeneous multiple memory cores with divided redundancy mechanism are proposed. Redundant memories are partitioned into row blocks and column blocks and shared among all memory cores in the same memory group. Therefore, unlike the traditional redundancy mechanism, a row (column) block is used as the basic replacement element. Based on the proposed divided redundancy mechanism, a heuristic heterogeneous extended spare pivoting (HESP) redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that repair rates can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example with four memory instances is only 1.12%.