An asynchronous transfer mode (ATM) switch architecture called a shared buffer memory switch whose output cell buffers are shared among all the output ports of the switch is proposed. Experimental measurements and a discussion about the traffic characteristics of the switch architecture are carried out to determine how much buffer memory will be reduced through buffer sharing under various traffic conditions and to roughly estimate how many buffers are needed for the switch to meet certain requirements. The resultant estimate shows that buffer sharing reduces the necessary buffer memory to less than 1/5 of what would otherwise be required, and the required buffer size is about 128 cells/output for a 32*32 switch when considering bursty traffic conditions. LSI implementation is also discussed to show that a 32*32 switch can be composed of about 12 chips mounted on one printed board.>

A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed.>