VLDB 2026 Research / reviewers in the wild / expert
Rajeev Alur
dblp:a/RAlur
· DBLP profile ↗
244ranked-venue papers
177as first author
28since 2021 · last 2025
0000-0003-1733-7083ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 133 · 113 first-author · 5 since 2021Software engineering, systems software and programming languages · 92 · 62 first-author · 10 since 2021Applied, interdisciplinary, general and emerging computing · 20 · 16 first-authorSystems, architecture and hardware · 17 · 10 first-author · 3 since 2021Artificial intelligence and machine learning · 10 · 1 first-author · 8 since 2021Computer networks · 5 · 1 since 2021Databases, data management, data science and information retrieval · 5 · 3 first-author · 3 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2 · 1 first-author · 1 since 2021Human-computer interaction and ubiquitous computing · 2Security and privacy · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Logicbreaks: A Framework for Understanding Subversion of Rule-based InferenceabstractWe study how to subvert large language models (LLMs) from following prompt-specified rules.
We first formalize rule-following as inference in propositional Horn logic, a mathematical system in which rules have the form "if $P$ and $Q$, then $R$" for some propositions $P$, $Q$, and $R$.
Next, we prove that although small transformers can faithfully follow such rules, maliciously crafted prompts can still mislead both theoretical constructions and models learned from data.
Furthermore, we demonstrate that popular attack algorithms on LLMs find adversarial prompts and induce attention patterns that align with our theory.
Our novel logic-based framework provides a foundation for studying LLMs in rule-based settings, enabling a formal analysis of tasks like logical reasoning and jailbreak attacks. Anton Xue, Avishree Khare, Rajeev Alur, Surbhi Goel, Eric Wong 0001 |
ICLR | 3 |
| 2025 | Understanding the Effectiveness of Large Language Models in Detecting Security VulnerabilitiesabstractSecurity vulnerabilities in modern software are prevalent and harmful. While automated vulnerability detection techniques have made promising progress, their scalability and applicability remain challenging. The remarkable performance of Large Language Models (LLMs), such as GPT-4 and CodeLlama, on code-related tasks has prompted recent works to explore if LLMs can be used to detect security vulnerabilities. In this paper, we perform a more comprehensive study by examining a larger and more diverse set of datasets, languages, and LLMs, and qualitatively evaluating detection performance across prompts and vulnerability classes. Concretely, we evaluate the effectiveness of 16 pre-trained LLMs on 5,000 code samples-1,000 randomly selected each from five diverse security datasets. These balanced datasets encompass synthetic and real-world projects in Java and C/C++ and cover 25 distinct vulnerability classes. Our results show that LLMs across all scales and families show modest effectiveness in end-to-end reasoning about vul-nerabilities, obtaining an average accuracy of 62.8% and F1 score of 0.71 across all datasets. LLMs are significantly better at detecting vulnerabilities that typically only need intra-procedural reasoning, such as OS Command Injection and NULL Pointer Dereference. Moreover, LLMs report higher accuracies on these vulnerabilities than popular static analysis tools, such as CodeQL. We find that advanced prompting strategies that involve step-by-step analysis significantly improve performance of LLMs on real-world datasets in terms of F1 score (by up to 0.18 on average). Interestingly, we observe that LLMs show promising abilities at performing parts of the analysis correctly, such as identifying vulnerability-related specifications (e.g., sources and sinks) and leveraging natural language information to understand code behavior (e.g., to check if code is sanitized). We believe our insights can motivate future work on LLM-augmented vulnerability detection systems. Avishree Khare, Saikat Dutta 0001, Ziyang Li 0002, Alaia Solko-Breslin, Rajeev Alur, Mayur Naik |
ICST | 5 |
| 2025 | CTSketch: Compositional Tensor Sketching for Scalable Neurosymbolic LearningabstractMany computational tasks benefit from being formulated as the composition of neural networks followed by a discrete symbolic program. The goal of neurosymbolic learning is to train the neural networks using end-to-end input-output labels of the composite. We introduce CTSketch, a novel, scalable neurosymbolic learning algorithm. CTSketch uses two techniques to improve the scalability of neurosymbolic inference: decompose the symbolic program into sub-programs and summarize each sub-program with a sketched tensor. This strategy allows us to approximate the output distribution of the program with simple tensor operations over the input distributions and the sketches. We provide theoretical insight into the maximum approximation error. Furthermore, we evaluate CTSketch on benchmarks from the neurosymbolic learning literature, including some designed for evaluating scalability. Our results show that CTSketch pushes neurosymbolic learning to new scales that were previously unattainable, with neural predictors obtaining high accuracy on tasks with one thousand inputs, despite supervision only on the final output. Seewon Choi, Alaia Solko-Breslin, Rajeev Alur, Eric Wong 0001 |
NeurIPS | 3 |
| 2024 | Relational Programming with Foundational ModelsabstractFoundation models have vast potential to enable diverse AI applications. The powerful yet incomplete nature of these models has spurred a wide range of mechanisms to augment them with capabilities such as in-context learning, information retrieval, and code interpreting. We propose Vieira, a declarative framework that unifies these mechanisms in a general solution for programming with foundation models. Vieira follows a probabilistic relational paradigm and treats foundation models as stateless functions with relational inputs and outputs. It supports neuro-symbolic applications by enabling the seamless combination of such models with logic programs, as well as complex, multi-modal applications by streamlining the composition of diverse sub-models. We implement Vieira by extending the Scallop compiler with a foreign interface that supports foundation models as plugins. We implement plugins for 12 foundation models including GPT, CLIP, and SAM. We evaluate Vieira on 9 challenging tasks that span language, vision, and structured and vector databases. Our evaluation shows that programs in Vieira are concise, can incorporate modern foundation models, and have comparable or better accuracy than competitive baselines. Ziyang Li 0002, Felix Zhu, Eric Zhao 0007, William Dodds, Neelay Velingker, Rajeev Alur, Mayur Naik |
AAAI | 8 |
| 2024 | Data-Efficient Learning with Neural ProgramsabstractMany computational tasks can be naturally expressed as a composition of a DNN followed by a program written in a traditional programming language or an API call to an LLM. We call such composites "neural programs" and focus on the problem of learning the DNN parameters when the training data consist of end-to-end input-output labels for the composite. When the program is written in a differentiable logic programming language, techniques from neurosymbolic learning are applicable, but in general, the learning for neural programs requires estimating the gradients of black-box components. We present an algorithm for learning neural programs, called ISED, that only relies on input-output samples of black-box components. For evaluation, we introduce new benchmarks that involve calls to modern LLMs such as GPT-4 and also consider benchmarks from the neurosymbolic learning literature. Our evaluation shows that for the latter benchmarks, ISED has comparable performance to state-of-the-art neurosymbolic frameworks. For the former, we use adaptations of prior work on gradient approximations of black-box components as a baseline, and show that ISED achieves comparable accuracy but in a more data- and sample-efficient manner. Alaia Solko-Breslin, Seewon Choi, Ziyang Li 0002, Neelay Velingker, Rajeev Alur, Mayur Naik, Eric Wong 0001 |
NeurIPS | 5 |
| 2024 | MuCache: A General Framework for Caching in Microservice Graphs
Haoran Zhang 0009, Konstantinos Kallas, Spyros Pavlatos, Rajeev Alur, Sebastian Angel, Vincent Liu 0001 |
NSDI | 4 |
| 2024 | TYGR: Type Inference on Stripped Binaries using Graph Neural Networks
Ziyang Li 0002, Anton Xue, Ati Priya Bajaj, Wil Gibbs, Rajeev Alur, Tiffany Bao, Hanjun Dai, Adam Doupé, Mayur Naik, Yan Shoshitaishvili, Ruoyu Wang 0001, Aravind Machiry |
USENIX Security Symposium | 7 |
| 2023 | Policy Synthesis and Reinforcement Learning for Discounted LTLabstractAbstract The difficulty of manually specifying reward functions has led to an interest in using linear temporal logic (LTL) to express objectives for reinforcement learning (RL). However, LTL has the downside that it is sensitive to small perturbations in the transition probabilities, which prevents probably approximately correct (PAC) learning without additional assumptions. Time discounting provides a way of removing this sensitivity, while retaining the high expressivity of the logic. We study the use of discounted LTL for policy synthesis in Markov decision processes with unknown transition probabilities, and show how to reduce discounted LTL to discounted-sum reward via a reward machine when all discount factors are identical. Rajeev Alur, Osbert Bastani, Kishor Jothimurugan, Mateo Perez, Fabio Somenzi, Ashutosh Trivedi 0001 |
CAV (1) | 1 |
| 2023 | Robust Subtask Learning for Compositional GeneralizationabstractCompositional reinforcement learning is a promising approach for training policies to perform complex long-horizon tasks. Typically, a high-level task is decomposed into a sequence of subtasks and a separate policy is trained to perform each subtask. In this paper, we focus on the problem of training subtask policies in a way that they can be used to perform any task; here, a task is given by a sequence of subtasks. We aim to maximize the worst-case performance over all tasks as opposed to the average-case performance. We formulate the problem as a two agent zero-sum game in which the adversary picks the sequence of subtasks. We propose two RL algorithms to solve this game: one is an adaptation of existing multi-agent RL algorithms to our setting and the other is an asynchronous version which enables parallel training of subtask policies. We evaluate our approach on two multi-task environments with continuous states and actions and demonstrate that our algorithms outperform state-of-the-art baselines. Kishor Jothimurugan, Steve Hsu, Osbert Bastani, Rajeev Alur |
ICML | 4 |
| 2023 | Stability Guarantees for Feature Attributions with Multiplicative SmoothingabstractExplanation methods for machine learning models tend not to provide any formal guarantees and may not reflect the underlying decision-making process.
In this work, we analyze stability as a property for reliable feature attribution methods.
We prove that relaxed variants of stability are guaranteed if the model is sufficiently Lipschitz with respect to the masking of features.
We develop a smoothing method called Multiplicative Smoothing (MuS) to achieve such a model.
We show that MuS overcomes the theoretical limitations of standard smoothing techniques and can be integrated with any classifier and feature attribution method.
We evaluate MuS on vision and language models with various feature attribution methods, such as LIME and SHAP, and demonstrate that MuS endows feature attributions with non-trivial stability guarantees. Anton Xue, Rajeev Alur, Eric Wong 0001 |
NeurIPS | 2 |
| 2023 | A Robust Theory of Series Parallel GraphsabstractMotivated by distributed data processing applications, we introduce a class of labeled directed acyclic graphs constructed using sequential and parallel composition operations, and study automata and logics over them. We show that deterministic and non-deterministic acceptors over such graphs have the same expressive power, which can be equivalently characterized by Monadic Second-Order logic and the graded µ-calculus. We establish closure under composition operations and decision procedures for membership, emptiness, and inclusion. A key feature of our graphs, called synchronized series-parallel graphs (SSPG), is that parallel composition introduces a synchronization edge from the newly introduced source vertex to the sink. The transfer of information enabled by such edges is crucial to the determinization construction, which would not be possible for the traditional definition of series-parallel graphs. SSPGs allow both ordered ranked parallelism and unordered unranked parallelism. The latter feature means that in the corresponding automata, the transition function needs to account for an arbitrary number of predecessors by counting each type of state only up to a specified constant, thus leading to a notion of counting complexity that is distinct from the classical notion of state complexity. The determinization construction translates a nondeterministic automaton with n states and k counting complexity to a deterministic automaton with 2 n 2 states and kn counting complexity, and both these bounds are shown to be tight. Furthermore, for nondeterministic automata a bound of 2 on counting complexity suffices without loss of expressiveness. Rajeev Alur, Caleb Stanford |
Proc. ACM Program. Lang. | 1 |
| 2023 | Executing Microservice Applications on Serverless, CorrectlyabstractWhile serverless platforms substantially simplify the provisioning, configuration, and management of cloud applications, implementing correct services on top of these platforms can present significant challenges to programmers. For example, serverless infrastructures introduce a host of failure modes that are not present in traditional deployments. Individual serverless instances can fail while others continue to make progress, correct but slow instances can be killed by the cloud provider as part of resource management, and providers will often respond to such failures by re-executing requests. For functions with side-effects, these scenarios can create behaviors that are not observable in serverful deployments. In this paper, we propose mu2sls, a framework for implementing microservice applications on serverless using standard Python code with two extra primitives: transactions and asynchronous calls. Our framework orchestrates user-written services to address several challenges, such as failures and re-executions, and provides formal guarantees that the generated serverless implementations are correct. To that end, we present a novel service specification abstraction and formalization of serverless implementations that facilitate reasoning about the correctness of a given application’s serverless implementation. This formalization forms the basis of the mu2sls prototype, which we then use to develop a few real-world microservice applications and show that the performance of the generated serverless implementations achieves significant scalability (3-5× the throughput of a sequential implementation) while providing correctness guarantees in the context of faults, re-execution, and concurrency. Konstantinos Kallas, Haoran Zhang 0009, Rajeev Alur, Sebastian Angel, Vincent Liu 0001 |
Proc. ACM Program. Lang. | 3 |
| 2023 | Mobius: Synthesizing Relational Queries with Recursive and Invented PredicatesabstractSynthesizing relational queries from data is challenging in the presence of recursion and invented predicates. We propose a fully automated approach to synthesize such queries. Our approach comprises of two steps: it first synthesizes a non-recursive query consistent with the given data, and then identifies recursion schemes in it and thereby generalizes to arbitrary data. This generalization is achieved by an iterative predicate unification procedure which exploits the notion of data provenance to accelerate convergence. In each iteration of the procedure, a constraint solver proposes a candidate query, and a query evaluator checks if the proposed program is consistent with the given data. The data provenance for a failed query allows us to construct additional constraints for the constraint solver and refine the search. We have implemented our approach in a tool named Mobius. On a suite of 21 challenging recursive query synthesis tasks, Mobius outperforms three state-of-the-art baselines Gensynth, ILASP, and Popper, both in terms of runtime and accuracy. We also demonstrate that the synthesized queries generalize well to unseen data. Aalok Thakkar, Nathaniel Sands, George Petrou, Rajeev Alur, Mayur Naik, Mukund Raghothaman |
Proc. ACM Program. Lang. | 4 |
| 2023 | Relational Query Synthesis ⋈ Decision Tree LearningabstractWe study the problem of synthesizing a core fragment of relational queries called select-project-join (SPJ) queries from input-output examples. Search-based synthesis techniques are suited to synthesizing projections and joins by navigating the network of relational tables but require additional supervision for synthesizing comparison predicates. On the other hand, decision tree learning techniques are suited to synthesizing comparison predicates when the input database can be summarized as a single labelled relational table. In this paper, we adapt and interleave methods from the domains of relational query synthesis and decision tree learning, and present an end-to-end framework for synthesizing relational queries with categorical and numerical comparison predicates. Our technique guarantees the completeness of the synthesis procedure and strongly encourages minimality of the synthesized program. We present Libra, an implementation of this technique and evaluate it on a benchmark suite of 1,475 instances of queries over 159 databases with multiple tables. Libra solves 1,361 of these instances in an average of 59 seconds per instance. It outperforms state-of-the-art program synthesis tools Scythe and PatSQL in terms of both the running time and the quality of the synthesized programs. Aaditya Naik, Aalok Thakkar, Adam Stein, Rajeev Alur, Mayur Naik |
Proc. VLDB Endow. | 4 |
| 2022 | Specification-Guided Learning of Nash Equilibria with High Social WelfareabstractAbstract Reinforcement learning has been shown to be an effective strategy for automatically training policies for challenging control problems. Focusing on non-cooperative multi-agent systems, we propose a novel reinforcement learning framework for training joint policies that form a Nash equilibrium. In our approach, rather than providing low-level reward functions, the user provides high-level specifications that encode the objective of each agent. Then, guided by the structure of the specifications, our algorithm searches over policies to identify one that provably forms an $$\epsilon $$ ϵ -Nash equilibrium (with high probability). Importantly, it prioritizes policies in a way that maximizes social welfare across all agents. Our empirical evaluation demonstrates that our algorithm computes equilibrium policies with high social welfare, whereas state-of-the-art baselines either fail to compute Nash equilibria or compute ones with comparatively lower social welfare. Kishor Jothimurugan, Suguman Bansal, Osbert Bastani, Rajeev Alur |
CAV (2) | 4 |
| 2022 | Correctness in Stream Processing: Challenges and Opportunities
Caleb Stanford, Konstantinos Kallas, Rajeev Alur |
CIDR | 3 |
| 2022 | Stream processing with dependency-guided synchronizationabstractReal-time data processing applications with low latency requirements have led to the increasing popularity of stream processing systems. While such systems offer convenient APIs that can be used to achieve data parallelism automatically, they offer limited support for computations that require synchronization between parallel nodes. In this paper, we propose dependency-guided synchronization (DGS), an alternative programming model for stateful streaming computations with complex synchronization requirements. In the proposed model, the input is viewed as partially ordered, and the program consists of a set of parallelization constructs which are applied to decompose the partial order and process events independently. Our programming model maps to an execution model called synchronization plans which supports synchronization between parallel nodes. Our evaluation shows that APIs offered by two widely used systems---Flink and Timely Dataflow---cannot suitably expose parallelism in some representative applications. In contrast, DGS enables implementations with scalable performance, the resulting synchronization plans offer throughput improvements when implemented manually in existing systems, and the programming overhead is small compared to writing sequential code. Konstantinos Kallas, Filip Niksic, Caleb Stanford, Rajeev Alur |
PPoPP | 4 |
| 2022 | Automatic Repair for Network ProgramsabstractAbstract Debugging imperative network programs is a difficult task for operators as it requires understanding various network modules and complicated data structures. For this purpose, this paper presents an automated technique for repairing network programs with respect to unit tests. Given as input a faulty network program and a set of unit tests, our approach localizes the fault through symbolic reasoning, and synthesizes a patch ensuring that the repaired program passes all unit tests. It applies domain-specific abstraction to simplify network data structures and exploits function summary reuse for modular symbolic analysis. We have implemented the proposed techniques in a tool called NetRep and evaluated it on 10 benchmarks adapted from real-world software-defined network controllers. The evaluation results demonstrate the effectiveness and efficiency of NetRep for repairing network programs. Lei Shi 0011, Yuepeng Wang 0001, Rajeev Alur, Boon Thau Loo |
TACAS (2) | 3 |
| 2022 | Static detection of uncoalesced accesses in GPU programs
Rajeev Alur, Joseph Devietti, Omar S. Navarro Leija, Nimit Singhania |
Formal Methods Syst. Des. | 1 |
| 2021 | Abstract Value Iteration for Hierarchical Reinforcement LearningabstractWe propose a novel hierarchical reinforcement learning framework for control with continuous state and action spaces. In our framework, the user specifies subgoal regions which are subsets of states; then, we (i) learn options that serve as transitions between these subgoal regions, and (ii) construct a high-level plan in the resulting abstract decision process (ADP). A key challenge is that the ADP may not be Markov; we propose two algorithms for planning in the ADP that address this issue. Our first algorithm is conservative, allowing us to prove theoretical guarantees on its performance, which help inform the design of subgoal regions. Our second algorithm is a practical one that interweaves planning at the abstract level and learning at the concrete level. In our experiments, we demonstrate that our approach outperforms state-of-the-art hierarchical reinforcement learning algorithms on several challenging benchmarks. Kishor Jothimurugan, Osbert Bastani, Rajeev Alur |
AISTATS | 3 |
| 2021 | Verisig 2.0: Verification of Neural Network Controllers Using Taylor Model PreconditioningabstractAbstract This paper presents Verisig 2.0, a verification tool for closed-loop systems with neural network (NN) controllers. We focus on NNs with tanh/sigmoid activations and develop a Taylor-model-based reachability algorithm through Taylor model preconditioning and shrink wrapping. Furthermore, we provide a parallelized implementation that allows Verisig 2.0 to efficiently handle larger NNs than existing tools can. We provide an extensive evaluation over 10 benchmarks and compare Verisig 2.0 against three state-of-the-art verification tools. We show that Verisig 2.0 is both more accurate and faster, achieving speed-ups of up to 21x and 268x against different tools, respectively. Radoslav Ivanov, Taylor J. Carpenter, James Weimer, Rajeev Alur, George J. Pappas, Insup Lee 0001 |
CAV (1) | 4 |
| 2021 | Compositional Reinforcement Learning from Logical SpecificationsabstractWe study the problem of learning control policies for complex tasks given by logical specifications. Recent approaches automatically generate a reward function from a given specification and use a suitable reinforcement learning algorithm to learn a policy that maximizes the expected reward. These approaches, however, scale poorly to complex tasks that require high-level planning. In this work, we develop a compositional learning approach, called DIRL, that interleaves high-level planning and reinforcement learning. First, DIRL encodes the specification as an abstract graph; intuitively, vertices and edges of the graph correspond to regions of the state space and simpler sub-tasks, respectively. Our approach then incorporates reinforcement learning to learn neural network policies for each edge (sub-task) within a Dijkstra-style planning algorithm to compute a high-level plan in the graph. An evaluation of the proposed approach on a set of challenging control benchmarks with continuous state and action spaces demonstrates that it outperforms state-of-the-art baselines. Kishor Jothimurugan, Suguman Bansal, Osbert Bastani, Rajeev Alur |
NeurIPS | 4 |
| 2021 | Example-guided synthesis of relational queriesabstractProgram synthesis tasks are commonly specified via input-output examples. Existing enumerative techniques for such tasks are primarily guided by program syntax and only make indirect use of the examples. We identify a class of synthesis algorithms for programming-by-examples, which we call Example-Guided Synthesis (EGS), that exploits latent structure in the provided examples while generating candidate programs. We present an instance of EGS for the synthesis of relational queries and evaluate it on 86 tasks from three application domains: knowledge discovery, program analysis, and database querying. Our evaluation shows that EGS outperforms state-of-the-art synthesizers based on enumerative search, constraint solving, and hybrid techniques in terms of synthesis time, quality of synthesized programs, and ability to prove unrealizability. Aalok Thakkar, Aaditya Naik, Nathaniel Sands, Rajeev Alur, Mayur Naik, Mukund Raghothaman |
PLDI | 4 |
| 2021 | Synchronization SchemasabstractWe present a type-theoretic framework for data stream processing for real-time decision making, where the desired computation involves a mix of sequential computation, such as smoothing and detection of peaks and surges, and naturally parallel computation, such as relational operations, key-based partitioning, and map-reduce. Our framework unifies sequential (ordered) and relational (unordered) data models. In particular, we define synchronization schemas as types, and series-parallel streams (SPS) as objects of these types. A synchronization schema imposes a hierarchical structure over relational types that succinctly captures ordering and synchronization requirements among different kinds of data items. Series-parallel streams naturally model objects such as relations, sequences, sequences of relations, sets of streams indexed by key values, time-based and event-based windows, and more complex structures obtained by nesting of these. We introduce series-parallel stream transformers (SPST) as a domain-specific language for modular specification of deterministic transformations over such streams. SPSTs provably specify only monotonic transformations allowing streamability, have a modular structure that can be exploited for correct parallel implementation, and are composable allowing specification of complex queries as a pipeline of transformations. Rajeev Alur, Phillip Hilliard, Zachary G. Ives, Konstantinos Kallas, Konstantinos Mamouras, Filip Niksic, Caleb Stanford, Val Tannen, Anton Xue |
PODS | 1 |
| 2021 | Network Traffic Classification by Program SynthesisabstractAbstract Writing classification rules to identify interesting network traffic is a time-consuming and error-prone task. Learning-based classification systems automatically extract such rules from positive and negative traffic examples. However, due to limitations in the representation of network traffic and the learning strategy, these systems lack both expressiveness to cover a range of applications and interpretability in fully describing the traffic’s structure at the session layer. This paper presents Sharingan system, which uses program synthesis techniques to generate network classification programs at the session layer. Sharingan accepts raw network traces as inputs and reports potential patterns of the target traffic in NetQRE, a domain specific language designed for specifying session-layer quantitative properties. We develop a range of novel optimizations that reduce the synthesis time for large and complex tasks to a matter of minutes. Our experiments show that Sharingan is able to correctly identify patterns from a diverse set of network traces and generates explainable outputs, while achieving accuracy comparable to state-of-the-art learning-based systems. Lei Shi 0011, Boon Thau Loo, Rajeev Alur |
TACAS (1) | 4 |
| 2021 | Colored nested words
Rajeev Alur, Dana Fisman |
Formal Methods Syst. Des. | 1 |
| 2021 | Verifying the Safety of Autonomous Systems with Neural Network ControllersabstractThis article addresses the problem of verifying the safety of autonomous systems with neural network (NN) controllers. We focus on NNs with sigmoid/tanh activations and use the fact that the sigmoid/tanh is the solution to a quadratic differential equation. This allows us to convert the NN into an equivalent hybrid system and cast the problem as a hybrid system verification problem, which can be solved by existing tools. Furthermore, we improve the scalability of the proposed method by approximating the sigmoid with a Taylor series with worst-case error bounds. Finally, we provide an evaluation over four benchmarks, including comparisons with alternative approaches based on mixed integer linear programming as well as on star sets. Radoslav Ivanov, Taylor J. Carpenter, James Weimer, Rajeev Alur, George J. Pappas, Insup Lee 0001 |
ACM Trans. Embed. Comput. Syst. | 4 |
| 2021 | Compositional Learning and Verification of Neural Network ControllersabstractRecent advances in deep learning have enabled data-driven controller design for autonomous systems. However, verifying safety of such controllers, which are often hard-to-analyze neural networks, remains a challenge. Inspired by compositional strategies for program verification, we propose a framework for compositional learning and verification of neural network controllers. Our approach is to decompose the task (e.g., car navigation) into a sequence of subtasks (e.g., segments of the track), each corresponding to a different mode of the system (e.g., go straight or turn). Then, we learn a separate controller for each mode, and verify correctness by proving that (i) each controller is correct within its mode, and (ii) transitions between modes are correct. This compositional strategy not only improves scalability of both learning and verification, but also enables our approach to verify correctness for arbitrary compositions of the subtasks. To handle partial observability (e.g., LiDAR), we additionally learn and verify a mode predictor that predicts which controller to use. Finally, our framework also incorporates an algorithm that, given a set of controllers, automatically synthesizes the pre- and postconditions required by our verification procedure. We validate our approach in a case study on a simulation model of the F1/10 autonomous car, a system that poses challenges for existing verification tools due to both its reliance on LiDAR observations, as well as the need to prove safety for complex track geometries. We leverage our framework to learn and verify a controller that safely completes any track consisting of an arbitrary sequence of five kinds of track segments. Radoslav Ivanov, Kishor Jothimurugan, Steve Hsu, Shaan Vaidya, Rajeev Alur, Osbert Bastani |
ACM Trans. Embed. Comput. Syst. | 5 |
| 2020 | Case study: verifying the safety of an autonomous racing car with a neural network controllerabstractThis paper describes a verification case study on an autonomous racing car with a neural network (NN) controller. Although several verification approaches have been recently proposed, they have only been evaluated on low-dimensional systems or systems with constrained environments. To explore the limits of existing approaches, we present a challenging benchmark in which the NN takes raw LiDAR measurements as input and outputs steering for the car. We train a dozen NNs using reinforcement learning (RL) and show that the state of the art in verification can handle systems with around 40 LiDAR rays. Furthermore, we perform real experiments to investigate the benefits and limitations of verification with respect to the sim2real gap, i.e., the difference between a system's modeled and real performance. We identify cases, similar to the modeled environment, in which verification is strongly correlated with safe behavior. Finally, we illustrate LiDAR fault patterns that can be used to develop robust and safe RL algorithms. Radoslav Ivanov, Taylor J. Carpenter, James Weimer, Rajeev Alur, George J. Pappas, Insup Lee 0001 |
HSCC | 4 |
| 2020 | Space-efficient Query Evaluation over Probabilistic Event StreamsabstractReal-time decision making in IoT applications relies upon space-efficient evaluation of queries over streaming data. To model the uncertainty in the classification of data being processed, we consider the model of probabilistic strings --- sequences of discrete probability distributions over a finite set of events, and initiate the study of space complexity of streaming computation for different classes of queries over such probabilistic strings. Rajeev Alur, Yu Chen 0039, Kishor Jothimurugan, Sanjeev Khanna |
LICS | 1 |
| 2020 | REAFFIRM: Model-Based Repair of Hybrid Systems for Improving ResiliencyabstractModel-based design offers a promising approach for assisting developers to build reliable and secure cyber-physical systems in a systematic manner. In this methodology, a designer first constructs a model, with mathematically precise semantics, of the system under design, and performs extensive analysis with respect to correctness requirements before generating the implementation from the model. However, as new vulnerabilities are discovered, requirements evolve aimed at ensuring resiliency. There is currently a shortage of an inexpensive, automated software that can effectively repair the initial design, and a model-based system developer regularly needs to redesign and reimplement the system from scratch. In this paper, we propose a new methodology along with a MATLAB software called REAFFIRM to facilitate the model-based repair for improving the resiliency of cyber-physical systems. REAFFIRM takes as inputs 1) an original hybrid system modeled as a Simulink/Stateflow diagram, 2) a given resiliency pattern specified as a model transformation script, and 3) a safety requirement expressed as a Signal Temporal Logic formula, and outputs a repaired model which satisfies the requirement. The tool consists of two main modules, model transformation followed by model synthesis. While the latter component is built on top of the falsification tool Breach, to implement the former, we introduce a new model transformation language for hybrid systems, which we call HATL, to allow a designer to specify resiliency patterns. To evaluate the proposed approach, we use REAFFIRM to automatically synthesize the repaired models of four different case studies. Luan Viet Nguyen, Gautam Mohan, James Weimer, Oleg Sokolsky, Insup Lee 0001, Rajeev Alur |
MEMOCODE | 6 |
| 2020 | DiffStream: differential output testing for stream processing programsabstractHigh performance architectures for processing distributed data streams, such as Flink, Spark Streaming, and Storm, are increasingly deployed in emerging data-driven computing systems. Exploiting the parallelism afforded by such platforms, while preserving the semantics of the desired computation, is prone to errors, and motivates the development of tools for specification, testing, and verification. We focus on the problem of differential output testing for distributed stream processing systems, that is, checking whether two implementations produce equivalent output streams in response to a given input stream. The notion of equivalence allows reordering of logically independent data items, and the main technical contribution of the paper is an optimal online algorithm for checking this equivalence. Our testing framework is implemented as a library called DiffStream in Flink. We present four case studies to illustrate how our framework can be used to (1) correctly identify bugs in a set of benchmark MapReduce programs, (2) facilitate the development of difficult-to-parallelize high performance applications, and (3) monitor an application for a long period of time with minimal performance overhead. Konstantinos Kallas, Filip Niksic, Caleb Stanford, Rajeev Alur |
Proc. ACM Program. Lang. | 4 |
| 2020 | Streamable regular transductions
Rajeev Alur, Dana Fisman, Konstantinos Mamouras, Mukund Raghothaman, Caleb Stanford |
Theor. Comput. Sci. | 1 |
| 2019 | Verisig: verifying safety properties of hybrid systems with neural network controllersabstractThis paper presents Verisig, a hybrid system approach to verifying safety properties of closed-loop systems using neural networks as controllers. We focus on sigmoid-based networks and exploit the fact that the sigmoid is the solution to a quadratic differential equation, which allows us to transform the neural network into an equivalent hybrid system. By composing the network's hybrid system with the plant's, we transform the problem into a hybrid system verification problem which can be solved using state-of-the-art reachability tools. We show that reachability is decidable for networks with one hidden layer and decidable for general networks if Schanuel's conjecture is true. We evaluate the applicability and scalability of Verisig in two case studies, one from reinforcement learning and one in which the neural network is used to approximate a model predictive controller. Radoslav Ivanov, James Weimer, Rajeev Alur, George J. Pappas, Insup Lee 0001 |
HSCC | 3 |
| 2019 | Detecting security leaks in hybrid systems with information flow analysisabstractInformation flow analysis is an effective way to check useful security properties, such as whether secret information can leak to adversaries. Despite being widely investigated in the realm of programming languages, information-flow-based security analysis has not been widely studied in the domain of cyber-physical systems (CPS). CPS provide interesting challenges to traditional type-based techniques, as they model mixed discrete-continuous behaviors and are usually expressed as a composition of state machines. In this paper, we propose a lightweight static analysis methodology that enables information security properties for CPS models. We introduce a set of security rules for hybrid automata that characterizes the property of non-interference. Based on those rules, we propose an algorithm that generates security constraints between each sub-component of hybrid automata, and then transforms these constraints into a directed dependency graph to search for non-interference violations. The proposed algorithm can be applied directly to parallel compositions of automata without resorting to model-flattening techniques. Our static checker works on hybrid systems modeled in Simulink/Stateflow format and decides whether or not the model satisfies non-interference given a user-provided security annotation for each variable. Moreover, our approach can also infer the security labels of variables, allowing a designer to verify the correctness of partial security annotations. We demonstrate the potential benefits of the proposed methodology on two case studies. Luan Viet Nguyen, Gautam Mohan, James Weimer, Oleg Sokolsky, Insup Lee 0001, Rajeev Alur |
MEMOCODE | 6 |
| 2019 | A Composable Specification Language for Reinforcement Learning TasksabstractReinforcement learning is a promising approach for learning control policies for robot tasks. However, specifying complex tasks (e.g., with multiple objectives and safety constraints) can be challenging, since the user must design a reward function that encodes the entire task. Furthermore, the user often needs to manually shape the reward to ensure convergence of the learning algorithm. We propose a language for specifying complex control tasks, along with an algorithm that compiles specifications in our language into a reward function and automatically performs reward shaping. We implement our approach in a tool called SPECTRL, and show that it outperforms several state-of-the-art baselines. Kishor Jothimurugan, Rajeev Alur, Osbert Bastani |
NeurIPS | 2 |
| 2019 | Data-trace types for distributed stream processing systemsabstractDistributed architectures for efficient processing of streaming data are increasingly critical to modern information processing systems. The goal of this paper is to develop type-based programming abstractions that facilitate correct and efficient deployment of a logical specification of the desired computation on such architectures. In the proposed model, each communication link has an associated type specifying tagged data items along with a dependency relation over tags that captures the logical partial ordering constraints over data items. The semantics of a (distributed) stream processing system is then a function from input data traces to output data traces, where a data trace is an equivalence class of sequences of data items induced by the dependency relation. This data-trace transduction model generalizes both acyclic synchronous data-flow and relational query processors, and can specify computations over data streams with a rich variety of partial ordering and synchronization characteristics. We then describe a set of programming templates for data-trace transductions: abstractions corresponding to common stream processing tasks. Our system automatically maps these high-level programs to a given topology on the distributed implementation platform Apache Storm while preserving the semantics. Our experimental evaluation shows that (1) while automatic parallelization deployed by existing systems may not preserve semantics, particularly when the computation is sensitive to the ordering of data items, our programming abstractions allow a natural specification of the query that contains a mix of ordering constraints while guaranteeing correct deployment, and (2) the throughput of the automatically compiled distributed code is comparable to that of hand-crafted distributed implementations. Konstantinos Mamouras, Caleb Stanford, Rajeev Alur, Zachary G. Ives, Val Tannen |
PLDI | 3 |
| 2019 | Modular quantitative monitoringabstractIn real-time decision making and runtime monitoring applications, declarative languages are commonly used as they facilitate modular high-level specifications with the compiler guaranteeing evaluation over data streams in an efficient and incremental manner. We introduce the model of Data Transducers to allow modular compilation of queries over streaming data. A data transducer maintains a finite set of data variables and processes a sequence of tagged data values by updating its variables using an allowed set of operations. The model allows unambiguous nondeterminism, exponentially succinct control, and combining values from parallel threads of computation. The semantics of the model immediately suggests an efficient streaming algorithm for evaluation. The expressiveness of data transducers coincides with streamable regular transductions , a robust and streamable class of functions characterized by MSO-definable string-to-DAG transformations with no backward edges. We show that the novel features of data transducers, unlike previously studied transducers, make them as succinct as traditional imperative code for processing data streams, but the structuring of the transition function permits modular compilation. In particular, we show that operations such as parallel composition, union, prefix-sum, and quantitative analogs of combinators for unambiguous parsing, can be implemented by natural and succinct constructions on data transducers. To illustrate the benefits of such modularity in compilation, we define a new language for quantitative monitoring, QRE-Past, that integrates features of past-time temporal logic and quantitative regular expressions. While this combination allows a natural specification of a cardiac arrhythmia detection algorithm in QRE-Past, compilation of QRE-Past specifications into efficient monitors comes for free thanks to succinct constructions on data transducers. Rajeev Alur, Konstantinos Mamouras, Caleb Stanford |
Proc. ACM Program. Lang. | 1 |
| 2018 | Accelerating search-based program synthesis using learned probabilistic modelsabstractA key challenge in program synthesis concerns how to efficiently search for the desired program in the space of possible programs. We propose a general approach to accelerate search-based program synthesis by biasing the search towards likely programs. Our approach targets a standard formulation, syntax-guided synthesis (SyGuS), by extending the grammar of possible programs with a probabilistic model dictating the likelihood of each program. We develop a weighted search algorithm to efficiently enumerate programs in order of their likelihood. We also propose a method based on transfer learning that enables to effectively learn a powerful model, called probabilistic higher-order grammar, from known solutions in a domain. We have implemented our approach in a tool called Euphony and evaluate it on SyGuS benchmark problems from a variety of domains. We show that Euphony can learn good models using easily obtainable solutions, and achieves significant performance gains over existing general-purpose as well as domain-specific synthesizers. Woosuk Lee, Kihong Heo, Rajeev Alur, Mayur Naik |
PLDI | 3 |
| 2018 | Block-Size Independence for GPU Programs
Rajeev Alur, Joseph Devietti, Nimit Singhania |
SAS | 1 |
| 2018 | Compositional and symbolic synthesis of reactive controllers for multi-agent systems
Rajeev Alur, Salar Moarref, Ufuk Topcu |
Inf. Comput. | 1 |
| 2018 | Real-Time Decision Policies With Predictable PerformanceabstractAs methods and tools for cyber-physical systems (CPS) grow in capabilities and use, one-size-fits-all solutions start to show their limitations. In particular, tools and languages for programming an algorithm or modeling a CPS that are specific to the application domain are typically more usable, and yield better performance, than general-purpose languages and tools. In the domain of cardiac arrhythmia monitoring, a small, implantable medical device continuously monitors the patient's cardiac rhythm and delivers electrical therapy when needed. The algorithms executed by these devices are streaming algorithms, so they are best programmed in a streaming language that allows the programmer to reason about the incoming data stream as the basic object, rather than force her to think about lower-level details like state maintenance and minimization. Because these devices are resource-constrained, it is useful if the programming language allowed predictable performance in terms of processing runtime and energy consumption, or more general costs. StreamQRE is a declarative streaming programming language, with an efficient and portable implementation and strong theoretical guarantees. In particular, its evaluation algorithm guarantees constant cost (runtime, memory, energy) per data item and also calculates upper bounds on the per-item cost. Such an estimate of the cost allows early exploration of the algorithmic possibilities, while maintaining a handle on worst case performance, on the basis of which hardware can be designed and algorithms can be tuned. Houssam Abbas, Rajeev Alur, Konstantinos Mamouras, Rahul Mangharam, Alëna Rodionova |
Proc. IEEE | 2 |
| 2018 | NetEgg: A Scenario-Based Programming Toolkit for SDN Policies
Yifei Yuan 0001, Dong Lin, Siri Anil, Harsh Verma, Anirudh Chelluri, Rajeev Alur, Boon Thau Loo |
IEEE/ACM Trans. Netw. | 6 |
| 2017 | GPUDrano: Detecting Uncoalesced Accesses in GPU Programs
Rajeev Alur, Joseph Devietti, Omar S. Navarro Leija, Nimit Singhania |
CAV (1) | 1 |
| 2017 | Automata-Based Stream ProcessingabstractWe propose an automata-theoretic framework for modularly expressing computations on streams of data. With weighted automata as a starting point, we identify three key features that are useful for an automaton model for stream processing: expressing the regular decomposition of streams whose data items are elements of a complex type (e.g., tuple of values), allowing the hierarchical nesting of several different kinds of aggregations, and specifying modularly the parallel execution and combination of various subcomputations. The combination of these features leads to subtle efficiency considerations that concern the interaction between nondeterminism, hierarchical nesting, and parallelism. We identify a syntactic restriction where the nondeterminism is unambiguous and parallel subcomputations synchronize their outputs. For automata satisfying these restrictions, we show that there is a space- and time-efficient streaming evaluation algorithm. We also prove that when these restrictions are relaxed, the evaluation problem becomes inherently computationally expensive. Rajeev Alur, Konstantinos Mamouras, Caleb Stanford |
ICALP | 1 |
| 2017 | StreamQRE: modular specification and efficient evaluation of quantitative queries over streaming dataabstractReal-time decision making in emerging IoT applications typically relies on computing quantitative summaries of large data streams in an efficient and incremental manner. To simplify the task of programming the desired logic, we propose StreamQRE, which provides natural and high-level constructs for processing streaming data. Our language has a novel integration of linguistic constructs from two distinct programming paradigms: streaming extensions of relational query languages and quantitative extensions of regular expressions. The former allows the programmer to employ relational constructs to partition the input data by keys and to integrate data streams from different sources, while the latter can be used to exploit the logical hierarchy in the input stream for modular specifications. We first present the core language with a small set of combinators, formal semantics, and a decidable type system. We then show how to express a number of common patterns with illustrative examples. Our compilation algorithm translates the high-level query into a streaming algorithm with precise complexity bounds on per-item processing time and total memory footprint. We also show how to integrate approximation algorithms into our framework. We report on an implementation in Java, and evaluate it with respect to existing high-performance engines for processing streaming data. Our experimental evaluation shows that (1) StreamQRE allows more natural and succinct specification of queries compared to existing frameworks, (2) the throughput of our implementation is higher than comparable systems (for example, two-to-four times greater than RxJava), and (3) the approximation algorithms supported by our implementation can lead to substantial memory savings. Konstantinos Mamouras, Mukund Raghothaman, Rajeev Alur, Zachary G. Ives, Sanjeev Khanna |
PLDI | 3 |
| 2017 | Quantitative Network Monitoring with NetQREabstractIn network management today, dynamic updates are required for traffic engineering and for timely response to security threats. Decisions for such updates are based on monitoring network traffic to compute numerical quantities based on a variety of network and application-level performance metrics. Today's state-of-the-art tools lack programming abstractions that capture application or session-layer semantics, and thus require network operators to specify and reason about complex state machines and interactions across layers. To address this limitation, we present the design and implementation of NetQRE, a high-level declarative toolkit that aims to simplify the specification and implementation of such quantitative network policies. NetQRE integrates regular-expression-like pattern matching at flow-level as well as application-level payloads with aggregation operations such as sum and average counts. We describe a compiler for NetQRE that automatically generates an efficient implementation with low memory footprint. Our evaluation results demonstrate that NetQRE allows natural specification of a wide range of quantitative network tasks ranging from detecting security attacks to enforcing application-layer network management policies. NetQRE results in high performance that is comparable with optimized manually-written low-level code and is significantly more efficient than alternative solutions, and can provide timely enforcement of network policies that require quantitative network monitoring. Yifei Yuan 0001, Dong Lin, Sajal Marwaha, Rajeev Alur, Boon Thau Loo |
SIGCOMM | 5 |
| 2017 | Scaling Enumerative Program Synthesis via Divide and Conquer
Rajeev Alur, Arjun Radhakrishna, Abhishek Udupa |
TACAS (1) | 1 |
| 2017 | Streaming Tree TransducersabstractThe theory of tree transducers provides a foundation for understanding expressiveness and complexity of analysis problems for specification languages for transforming hierarchically structured data such as XML documents. We introduce streaming tree transducers as an analyzable, executable, and expressive model for transforming unranked ordered trees (and forests) in a single pass. Given a linear encoding of the input tree, the transducer makes a single left-to-right pass through the input, and computes the output in linear time using a finite-state control, a visibly pushdown stack, and a finite number of variables that store output chunks that can be combined using the operations of string-concatenation and tree-insertion. We prove that the expressiveness of the model coincides with transductions definable using monadic second-order logic (MSO). Existing models of tree transducers either cannot implement all MSO-definable transformations, or require regular look-ahead that prohibits single-pass implementation. We show a variety of analysis problems such as type-checking and checking functional equivalence are decidable for our model. Rajeev Alur, Loris D'Antoni |
J. ACM | 1 |
| 2017 | Schedulability of Bounded-Rate Multimode SystemsabstractBounded-rate multimode systems are hybrid systems that switch freely among a finite set of modes, and whose dynamics are specified by a finite number of real-valued variables with mode-dependent rates that vary within given bounded sets. The scheduler repeatedly proposes a time and a mode, while the environment chooses an allowable rate for that mode; the state of the system changes linearly in the direction of the rate. The scheduler aims to keep the state within a safe set, while the environment aims to leave it. We study the problem of existence of a winning scheduler strategy and associated complexity questions. Rajeev Alur, Vojtech Forejt, Salar Moarref, Ashutosh Trivedi 0001 |
ACM Trans. Embed. Comput. Syst. | 1 |
| 2016 | Compositional Synthesis of Reactive Controllers for Multi-agent Systems
Rajeev Alur, Salar Moarref, Ufuk Topcu |
CAV (2) | 1 |
| 2016 | Hedging Bets in Markov Decision ProcessesabstractThe classical model of Markov decision processes with costs or rewards, while widely used to formalize optimal decision making, cannot capture scenarios where there are multiple objectives for the agent during the system evolution, but only one of these objectives gets actualized upon termination. We introduce the model of Markov decision processes with alternative objectives (MDPAO) for formalizing optimization in such scenarios. To compute the strategy to optimize the expected cost/reward upon termination, we need to figure out how to balance the values of the alternative objectives. This requires analysis of the underlying infinite-state process that tracks the accumulated values of all the objectives. While the decidability of the problem of computing the exact optimal strategy for the general model remains open, we present the following results. First, for a Markov chain with alternative objectives, the optimal expected cost/reward can be computed in polynomial-time. Second, for a single-state process with two actions and multiple objectives we show how to compute the optimal decision strategy. Third, for a process with only two alternative objectives, we present a reduction to the minimum expected accumulated reward problem for one-counter MDPs, and this leads to decidability for this case under some technical restrictions. Finally, we show that optimal cost/reward can be approximated up to a constant additive factor for the general problem. Rajeev Alur, Marco Faella, Sampath Kannan, Nimit Singhania |
CSL | 1 |
| 2016 | Regular Programming for Quantitative Properties of Data Streams
Rajeev Alur, Dana Fisman, Mukund Raghothaman |
ESOP | 1 |
| 2016 | Compositional Synthesis with Parametric Reactive ControllersabstractReactive synthesis with the ambitious goal of automatically synthesizing correct-by-construction controllers from high-level specifications, has recently attracted significant attention in system design and control. In practice, complex systems are often not constructed from scratch but from a set of existing building blocks. For example in robot motion planning, a robot usually has a number of predefined motion primitives that can be selected and composed to enforce a high-level objective. In this paper, we propose a novel framework for synthesis from a library of parametric and reactive controllers. Parameters allow us to take advantage of the symmetry in many synthesis problems. Reactivity of the controllers takes into account that the environment may be dynamic and potentially adversarial. We first show how these controllers can be automatically constructed from parametric objectives specified by the user to form a library of parametric and reactive controllers. We then give a synthesis algorithm that selects and instantiates controllers from the library in order to satisfy a given linear temporal logic objective. We implement our algorithms symbolically and illustrate the potential of our method by applying it to an autonomous vehicle case study. Rajeev Alur, Salar Moarref, Ufuk Topcu |
HSCC | 1 |
| 2016 | Colored Nested Words
Rajeev Alur, Dana Fisman |
LATA | 1 |
| 2015 | Synthesis Through Unification
Rajeev Alur, Pavol Cerný, Arjun Radhakrishna |
CAV (2) | 1 |
| 2015 | Automatic Completion of Distributed Protocols with Symmetry
Rajeev Alur, Mukund Raghothaman, Christos Stergiou 0001, Stavros Tripakis, Abhishek Udupa |
CAV (2) | 1 |
| 2015 | Scenario-based programming for SDN policiesabstractRecent emergence of software-defined networks offers an opportunity to design domain-specific programming abstractions aimed at network operators. In this paper, we propose scenario-based programming, a framework that allows network operators to program network policies by describing representative example behaviors. Given these scenarios, our synthesis algorithm automatically infers the controller state that needs to be maintained along with the rules to process network events and update state. We have developed the NetEgg scenario-based programming tool, which can execute the generated policy implementation on top of a centralized controller, but also automatically infers flow-table rules that can be pushed to switches to improve throughput. We study a range of policies considered in the literature and report our experience regarding specifying these policies using scenarios. We evaluate NetEgg based on the computational requirements of our synthesis algorithm as well as the overhead introduced by the generated policy implementation. Our results show that our synthesis algorithm can generate policy implementations in seconds, and the automatically generated policy implementations have performance comparable to their hand-crafted implementations. Yifei Yuan 0001, Dong Lin, Rajeev Alur, Boon Thau Loo |
CoNEXT | 3 |
| 2015 | Keynote talk I: Syntax-guided synthesisabstractThe classical formulation of the program-synthesis problem is to find a program that meets a correctness specification given as a logical formula. Recent work on program synthesis and program optimization illustrates many potential benefits of allowing the user to supplement the logical specification with a syntactic template that constrains the space of allowed implementations. The formulation of the syntax-guided synthesis problem (SyGuS) is aimed at standardizing the core computational problem common to these proposals in a logical framework [1]. The input to the SyGuS problem consists of a background theory, a semantic correctness specification for the desired program given by a logical formula, and a syntactic set of candidate implementations given by a grammar. The computational problem then is to find an implementation from the set of candidate expressions so that it satisfies the specification in the given theory. In this talk, we first describe how a wide range of problems such as automatic synthesis of loop invariants, program optimization, learning programs from examples, and program sketching, can be formalized as SyGuS instances. We then describe three different instantiations of the counter-example-guided-inductive-synthesis (CEGIS) strategy for solving the SyGuS problem. Finally, we discuss our efforts over the past two years on defining the standardized interchange format built on top of SMT-LIB, repository of benchmarks from diverse applications, organization of the annual competition, SyGuS-COMP, of solvers, and experimental evaluation of solution strategies. More information about our project is available at www.sygus.org. This research is supported by the NSF Expeditions in Computing project ExCAPE (award CCF 1138996). Rajeev Alur |
MEMOCODE | 1 |
| 2015 | DReX: A Declarative Language for Efficiently Evaluating Regular String TransformationsabstractWe present DReX, a declarative language that can express all regular string-to string transformations, and can still be efficiently evaluated. The class of regular string transformations has a robust theoretical foundation including multiple characterizations, closure properties, and decidable analysis questions, and admits a number of string operations such as insertion, deletion, substring swap, and reversal. Recent research has led to a characterization of regular string transformations using a primitive set of function combinators analogous to the definition of regular languages using regular expressions. While these combinators form the basis for the language DReX proposed in this paper, our main technical focus is on the complexity of evaluating the output of a DReX program on a given input string. It turns out that the natural evaluation algorithm involves dynamic programming, leading to complexity that is cubic in the length of the input string. Our main contribution is identifying a consistency restriction on the use of combinators in DReX programs, and a single-pass evaluation algorithm for consistent programs with time complexity that is linear in the length of the input string and polynomial in the size of the program. We show that the consistency restriction does not limit the expressiveness, and whether a DReX program is consistent can be checked efficiently. We report on a prototype implementation, and evaluate it using a representative set of text processing tasks. Rajeev Alur, Loris D'Antoni, Mukund Raghothaman |
POPL | 1 |
| 2015 | Pattern-Based Refinement of Assume-Guarantee Specifications in Reactive Synthesis
Rajeev Alur, Salar Moarref, Ufuk Topcu |
TACAS | 1 |
| 2015 | How Can Automatic Feedback Help Students Construct Automata?abstractIn computer-aided education, the goal of automatic feedback is to provide a meaningful explanation of students' mistakes. We focus on providing feedback for constructing a deterministic finite automaton that accepts strings that match a described pattern. Natural choices for feedback are binary feedback (correct/wrong) and a counterexample of a string that is processed incorrectly. Such feedback is easy to compute but might not provide the student enough help. Our first contribution is a novel way to automatically compute alternative conceptual hints. Our second contribution is a rigorous evaluation of feedback with 377 students. We find that providing either counterexamples or hints is judged as helpful, increases student perseverance, and can improve problem completion time. However, both strategies have particular strengths and weaknesses. Since our feedback is completely automatic, it can be deployed at scale and integrated into existing massive open online courses. Loris D'Antoni, Dileep Kini, Rajeev Alur, Sumit Gulwani, Mahesh Viswanathan 0001, Björn Hartmann |
ACM Trans. Comput. Hum. Interact. | 3 |
| 2014 | Symbolic Visibly Pushdown Automata
Loris D'Antoni, Rajeev Alur |
CAV | 2 |
| 2014 | Precise piecewise affine models from input-output dataabstractFormal design and analysis of embedded control software relies on mathematical models of dynamical systems, and such models can be hard to obtain. In this paper, we focus on automatic construction of piecewise affine models from input-output data. Given a set of examples, where each example consists of a d-dimensional real-valued input vector mapped to a real-valued output, we want to compute a set of affine functions that covers all the data points up to a specified degree of accuracy, along with a disjoint partitioning of the space of all inputs defined using a Boolean combination of affine inequalities with one region for each of the learnt functions. While traditional machine learning algorithms such as linear regression can be adapted to learn the set of affine functions, we develop new techniques based on automatic construction of interpolants to derive precise guards defining the desired partitioning corresponding to these functions. We report on a prototype tool, Mosaic, implemented in Matlab. We evaluate its performance using some synthetic data, and compare it against known techniques using data-sets modeling electronic placement process in pick-and-place machines. Rajeev Alur, Nimit Singhania |
EMSOFT | 1 |
| 2014 | NetEgg: Programming Network Policies by ExamplesabstractThe emergence of programmable interfaces to network controllers offers network operators the flexibility to implement a variety of policies. We propose NetEgg, a programming framework that allows a network operator to specify the desired functionality using example behaviors. Our synthesis algorithm automatically infers the state that needs to be maintained to exhibit the desired behaviors along with the rules for processing network packets and updating the state. We report on an initial prototype of NetEgg. Our experiments evaluate the proposed framework based on the number of examples needed to specify a variety of policies considered in the literature, the computational requirements of the synthesis algorithm to translate these examples to programs, and the overhead introduced by the generated implementation for processing packets. Our results show that NetEgg can generate implementations that are consistent with the example behaviors, and have performance comparable to equivalent imperative implementations. Yifei Yuan 0001, Rajeev Alur, Boon Thau Loo |
HotNets | 2 |
| 2014 | Closed-loop verification of medical devices with model abstraction and refinement
Zhihao Jiang 0001, Miroslav Pajic, Rajeev Alur, Rahul Mangharam |
Int. J. Softw. Tools Technol. Transf. | 3 |
| 2013 | Syntax-guided synthesis
Rajeev Alur, Rastislav Bodík, Garvit Juniwal, Milo M. K. Martin, Mukund Raghothaman, Sanjit A. Seshia, Rishabh Singh, Armando Solar-Lezama, Emina Torlak, Abhishek Udupa |
FMCAD | 1 |
| 2013 | Counter-strategy guided refinement of GR(1) temporal logic specifications
Rajeev Alur, Salar Moarref, Ufuk Topcu |
FMCAD | 1 |
| 2013 | On the feasibility of automation for bandwidth allocation problems in data centers
Yifei Yuan 0001, Anduo Wang, Rajeev Alur, Boon Thau Loo |
FMCAD | 3 |
| 2013 | Safe schedulability of bounded-rate multi-mode systemsabstractBounded-rate multi-mode systems (BMS) are hybrid systems that can switch freely among a finite set of modes, and whose dynamics is specified by a finite number of real-valued variables with mode-dependent rates that can vary within given bounded sets. The schedulability problem for BMS is defined as an infinite-round game between two players---the scheduler and the environment---where in each round the scheduler proposes a time and a mode while the environment chooses an allowable rate for that mode, and the state of the system changes linearly in the direction of the rate vector. The goal of the scheduler is to keep the state of the system within a pre-specified safe set using a non-Zeno schedule, while the goal of the environment is the opposite. Green scheduling under uncertainty is a paradigmatic example of BMS where a winning strategy of the scheduler corresponds to a robust energy-optimal policy. We present an algorithm to decide whether the scheduler has a winning strategy from an arbitrary starting state, and give an algorithm to compute such a winning strategy, if it exists. We show that the schedulability problem for BMS is co-NP complete in general, but for two variables it is in PTIME. We also study the discrete schedulability problem where the environment has only finitely many choices of rate vectors in each mode and the scheduler can make decisions only at multiples of a given clock period, and show it to be EXPTIME-complete. Rajeev Alur, Vojtech Forejt, Salar Moarref, Ashutosh Trivedi 0001 |
HSCC | 1 |
| 2013 | Decision Problems for Additive Regular Functions
Rajeev Alur, Mukund Raghothaman |
ICALP (2) | 1 |
| 2013 | Automated Grading of DFA Constructions
Rajeev Alur, Loris D'Antoni, Sumit Gulwani, Dileep Kini, Mahesh Viswanathan 0001 |
IJCAI | 1 |
| 2013 | On the Complexity of Shortest Path Problems on Discounted Cost Graphs
Rajeev Alur, Sampath Kannan, Kevin Tian, Yifei Yuan 0001 |
LATA | 1 |
| 2013 | Regular Functions and Cost Register AutomataabstractWe propose a deterministic model for associating costs with strings that is parameterized by operations of interest (such as addition, scaling, and minimum), a notion of regularity that provides a yardstick to measure expressiveness, and study decision problems and theoretical properties of resulting classes of cost functions. Our definition of regularity relies on the theory of string-to-tree transducers, and allows associating costs with events that are conditioned on regular properties of future events. Our model of cost register automata allows computation of regular functions using multiple “write-only” registers whose values can be combined using the allowed set of operations. We show that the classical shortest-path algorithms as well as the algorithms designed for computing discounted costs can be adapted for solving the min-cost problems for the more general classes of functions specified in our model. Cost register automata with the operations of minimum and increment give a deterministic model that is equivalent to weighted automata, an extensively studied nondeterministic model, and this connection results in new insights and new open problems. Rajeev Alur, Loris D'Antoni, Jyotirmoy V. Deshmukh, Mukund Raghothaman, Yifei Yuan 0001 |
LICS | 1 |
| 2013 | From Monadic Second-Order Definable String Transformations to TransducersabstractCourcelle (1992) proposed the idea of using logic, in particular Monadic second-order logic (MSO), to define graph to graph transformations. Transducers, on the other hand, are executable machine models to define transformations, and are typically studied in the context of string-to-string transformations. Engelfriet and Hoogeboom (2001) studied two-way finite state string-to-string transducers and showed that their expressiveness matches MSO-definable transformations (MSOT). Alur and Cerny (2011) presented streaming transducers-one-way transducers equipped with multiple registers that can store output strings, as an equi-expressive model. Natural generalizations of streaming transducers to string-to-tree (Alur and D'Antoni, 2012) and infinite-string-to-string (Alur, Filiot, and Trivedi, 2012) cases preserve MSO-expressiveness. While earlier reductions from MSOT to streaming transducers used two-way transducers as the intermediate model, we revisit the earlier reductions in a more general, and previously unexplored, setting of infinite-string-to-tree transformations, and provide a direct reduction. Proof techniques used for this new reduction exploit the conceptual tools (composition theorem and finite additive coloring theorem) presented by Shelah (1975) in his alternative proof of Bϋchi's theorem. Using such streaming string-to-tree transducers we show the decidability of functional equivalence for MSO-definable infinite-string-to-tree transducers. Rajeev Alur, Antoine Durand-Gasselin, Ashutosh Trivedi 0001 |
LICS | 1 |
| 2013 | Tutorial I: Syntax-guided synthesis
Rajeev Alur |
MEMOCODE | 1 |
| 2013 | TRANSIT: specifying protocols with concolic snippetsabstractWith the maturing of technology for model checking and constraint solving, there is an emerging opportunity to develop programming tools that can transform the way systems are specified. In this paper, we propose a new way to program distributed protocols using concolic snippets. Concolic snippets are sample execution fragments that contain both concrete and symbolic values. The proposed approach allows the programmer to describe the desired system partially using the traditional model of communicating extended finite-state-machines (EFSM), along with high-level invariants and concrete execution fragments. Our synthesis engine completes an EFSM skeleton by inferring guards and updates from the given fragments which is then automatically analyzed using a model checker with respect to the desired invariants. The counterexamples produced by the model checker can then be used by the programmer to add new concrete execution fragments that describe the correct behavior in the specific scenario corresponding to the counterexample. Abhishek Udupa, Arun Raghavan, Jyotirmoy V. Deshmukh, Sela Mador-Haim, Milo M. K. Martin, Rajeev Alur |
PLDI | 6 |
| 2012 | An Axiomatic Memory Model for POWER Multiprocessors
Sela Mador-Haim, Luc Maranget, Susmit Sarkar, Kayvan Memarian, Jade Alglave, Scott Owens, Rajeev Alur, Milo M. K. Martin, Peter Sewell, Derek Williams |
CAV | 7 |
| 2012 | Optimal scheduling for constant-rate multi-mode systemsabstractConstant-rate multi-mode systems are hybrid systems that can switch freely among a finite set of modes, and whose dynamics is specified by a finite number of real-valued variables with mode-dependent constant rates. The schedulability problem for such systems is to design a mode-switching policy that maintains the state within a specified safety set. The main result of the paper is that schedulability can be decided in polynomial time. We also generalize our result to optimal schedulability problems with average cost and reachability cost objectives. Polynomial-time scheduling algorithms make this class an appealing formal model for design of energy-optimal policies. The key to tractability is that the only constraints on when a scheduler can switch the mode are specified by global objectives. Adding local constraints by associating either invariants with modes, or guards with mode switches, lead to undecidability, and requiring the scheduler to make decisions only at multiples of a given sampling rate, leads to a PSPACE-complete schedulability problem. Rajeev Alur, Ashutosh Trivedi 0001, Dominik Wojtczak |
HSCC | 1 |
| 2012 | Streaming Tree Transducers
Rajeev Alur, Loris D'Antoni |
ICALP (2) | 1 |
| 2012 | Regular Transformations of Infinite StringsabstractThe theory of regular transformations of finite strings is quite mature with appealing properties. This class can be equivalently defined using both logic (Monadic second-order logic) and finite-state machines (two-way transducers, and more recently, streaming string transducers); is closed under operations such as sequential composition and regular choice; and problems such as functional equivalence and type checking, are decidable for this class. In this paper, we initiate a study of transformations of infinite strings. The MSO-based definition for regular string transformations generalizes naturally to infinite strings. We define an equivalent generalization of the machine model of streaming string transducers to infinite strings. A streaming string transducer is a deterministic machine that makes a single pass over the input string, and computes the output fragments using a finite set of string variables that are updated in a copyless manner at each step. We show how Muller acceptance condition for automata over infinite strings can be generalized to associate an infinite output string with an infinite execution. The proof that our model captures all MSO-definable transformations uses two-way transducers. Unlike the case of finite strings, MSO-equivalent definition of two-way transducers over infinite strings needs to make decisions based on omega-regular look-ahead. Simulating this look-ahead using multiple variables with copyless updates, is the main technical challenge in our constructions. Finally, we show that type checking and functional equivalence are decidable for MSO-definable transformations of infinite strings. Rajeev Alur, Emmanuel Filiot, Ashutosh Trivedi 0001 |
LICS | 1 |
| 2012 | Modeling and Verification of a Dual Chamber Implantable Pacemaker
Zhihao Jiang 0001, Miroslav Pajic, Salar Moarref, Rajeev Alur, Rahul Mangharam |
TACAS | 4 |
| 2012 | 2010 CAV award announcement
Orna Grumberg, Moshe Y. Vardi, Joseph Sifakis, Rajeev Alur |
Formal Methods Syst. Des. | 4 |
| 2012 | 2011 CAV award announcement
Moshe Y. Vardi, Thomas A. Henzinger, Rajeev Alur, Marta Z. Kwiatkowska |
Formal Methods Syst. Des. | 3 |
| 2012 | Time-Triggered Implementations of Dynamic ControllersabstractBridging the gap between model-based design and platform-based implementation is one of the critical challenges for embedded software systems. In the context of embedded control systems that interact with an environment, a variety of errors due to quantization, delays, and scheduling policies may generate executable code that does not faithfully implement the model-based design. In this article, we show that the performance gap between the model-level semantics of linear dynamic controllers, for example, the proportional-integral-derivative (PID) controllers and their implementation-level semantics, can be rigorously quantified if the controller implementation is executed on a predictable time-triggered architecture. Our technical approach uses lifting techniques for periodic time-varying linear systems in order to compute the exact error between the model semantics and the execution semantics. Explicitly computing the impact of the implementation on overall system performance allows us to compare and partially order different implementations with various scheduling or timing characteristics. Truong Nghiem, George J. Pappas, Rajeev Alur, Antoine Girard |
ACM Trans. Embed. Comput. Syst. | 3 |
| 2012 | Algorithmic analysis of array-accessing programsabstractFor programs whose data variables range over Boolean or finite domains, program verification is decidable, and this forms the basis of recent tools for software model checking. In this article, we consider algorithmic verification of programs that use Boolean variables, and in addition, access a single read-only array whose length is potentially unbounded, and whose elements range over an unbounded data domain. We show that the reachability problem, while undecidable in general, is (1) Pspace-complete for programs in which the array-accessing for-loops are not nested, (2) decidable for a restricted class of programs with doubly nested loops. The second result establishes connections to automata and logics defining languages over data words. Rajeev Alur, Pavol Cerný, Scott Weinstein |
ACM Trans. Comput. Log. | 1 |
| 2011 | Litmus tests for comparing memory consistency models: how long do they need to be?abstractMemory consistency litmus tests are small parallel programs that are designed to illustrate subtle differences between memory consistency models by exhibiting different outcomes for different models. In this paper, we show that for a class of memory models that is restricted yet expressive enough to include all store-atomic hardware memory models, litmus tests of a bounded size are sufficient for illustrating differences between memory consistency models in this class. We establish a bound of two threads and no more than six memory access instructions for differentiating litmus tests in this class of models. Thus, we can prove equivalence of two specification of memory consistency models in this class by exploring a bounded number of litmus tests. We build a tool for comparing memory models based on this result, and we use the tool to explore and map the space of this class of models. Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin |
DAC | 2 |
| 2011 | Formal verification of hybrid systemsabstractIn formal verification, a designer first constructs a model, with mathematically precise semantics, of the system under design, and performs extensive analysis with respect to correctness requirements. The appropriate mathematical model for embedded control systems is hybrid systems that combines the traditional state-machine based models for discrete control with classical differential-equations based models for continuously evolving physical activities. In this article, we briefly review selected existing approaches to formal verification of hybrid systems, along with directions for future research. Rajeev Alur |
EMSOFT | 1 |
| 2011 | Relating average and discounted costs for quantitative analysis of timed systemsabstractQuantitative analysis and controller synthesis problems for reactive real-time systems can be formalized as optimization problems on timed automata, timed games, and their probabilistic extensions. The limiting average cost and the discounted cost are two standard criteria for such optimization problems. In theory of finite-state probabilistic systems, a number of interesting results are available relating the optimal values according to these two different performance objectives. These results, however, do not directly apply to timed systems due to the infinite state-space of clock valuations. In this paper, we present some conditions under which the existence of the limit of optimal discounted cost objective implies the the existence of limiting average cost to the same value. Using these results we answer an open question posed by Fahrenberg and Larsen, and give simpler proofs of some known decidability results on (probabilistic) timed automata. We also show the determinacy and decidability of average-time games on timed automata, and expected average-time games on probabilistic timed automata. Rajeev Alur, Ashutosh Trivedi 0001 |
EMSOFT | 1 |
| 2011 | Nondeterministic Streaming String Transducers
Rajeev Alur, Jyotirmoy V. Deshmukh |
ICALP (2) | 1 |
| 2011 | Streaming transducers for algorithmic verification of single-pass list-processing programsabstractWe introduce streaming data string transducers that map input data strings to output data strings in a single left-to-right pass in linear time. Data strings are (unbounded) sequences of data values, tagged with symbols from a finite set, over a potentially infinite data domain that supports only the operations of equality and ordering. The transducer uses a finite set of states, a finite set of variables ranging over the data domain, and a finite set of variables ranging over data strings. At every step, it can make decisions based on the next input symbol, updating its state, remembering the input data value in its data variables, and updating data-string variables by concatenating data-string variables and new symbols formed from data variables, while avoiding duplication. We establish PSPACE bounds for the problems of checking functional equivalence of two streaming transducers, and of checking whether a streaming transducer satisfies pre/post verification conditions specified by streaming acceptors over input/output data-strings. Rajeev Alur, Pavol Cerný |
POPL | 1 |
| 2011 | Streaming String Transducers
Rajeev Alur |
WoLLIC | 1 |
| 2011 | Software model checking using languages of nested treesabstractWhile model checking of pushdown systems is by now an established technique in software verification, temporal logics and automata traditionally used in this area are unattractive on two counts. First, logics and automata traditionally used in model checking cannot express requirements such as pre/post-conditions that are basic to analysis of software. Second, unlike in the finite-state world, where the μ-calculus has a symbolic model-checking algorithm and serves as an “assembly language” to which temporal logics can be compiled, there is no common formalism—either fixpoint-based or automata-theoretic—to model-check requirements on pushdown models. In this article, we introduce a new theory of temporal logics and automata that addresses the above issues, and provides a unified foundation for the verification of pushdown systems. The key idea here is to view a program as a generator of structures known as nested trees as opposed to trees. A fixpoint logic (called N T -μ) and a class of automata (called nested tree automata ) interpreted on languages of these structures are now defined, and branching-time model-checking is phrased as language inclusion and membership problems for these languages. We show that N T -μ and nested tree automata allow the specification of a new frontier of requirements usable in software verification. At the same time, their model checking problem has the same worst-case complexity as their traditional analogs, and can be solved symbolically using a fixpoint computation that generalizes, and includes as a special case, “summary”-based computations traditionally used in interprocedural program analysis. We also show that our logics and automata define a robust class of languages—in particular, just as the μ-calculus is equivalent to alternating parity automata on trees, NT-μ is equivalent to alternating parity automata on nested trees. Rajeev Alur, Swarat Chaudhuri, P. Madhusudan |
ACM Trans. Program. Lang. Syst. | 1 |
| 2010 | Model Checking of Linearizability of Concurrent List Implementations
Pavol Cerný, Arjun Radhakrishna, Damien Zufferey, Swarat Chaudhuri, Rajeev Alur |
CAV | 5 |
| 2010 | Generating Litmus Tests for Contrasting Memory Consistency Models
Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin |
CAV | 2 |
| 2010 | Expressiveness of streaming string transducersabstractStreaming string transducers define (partial) functions from input strings to output strings. A streaming string transducer makes a single pass through the input string and uses a finite set of variables that range over strings from the output alphabet. At every step, the transducer processes an input symbol, and updates all the variables in parallel using assignments whose right-hand-sides are concatenations of output symbols and variables with the restriction that a variable can be used at most once in a right-hand-side expression. It has been shown that streaming string transducers operating on strings over infinite data domains are of interest in algorithmic verification of list-processing programs, as they lead to Pspace decision procedures for checking pre/postconditions and for checking semantic equivalence, for a well-defined class of heap-manipulating programs. In order to understand the theoretical expressiveness of streaming transducers, we focus on streaming transducers processing strings over finite alphabets, given the existence of a robust and well-studied class of ``regular'' transductions for this case. Such regular transductions can be defined either by two-way deterministic finite-state transducers, or using a logical MSO-based characterization. Our main result is that the expressiveness of streaming string transducers coincides exactly with this class of regular transductions. Rajeev Alur, Pavol Cerný |
FSTTCS | 1 |
| 2010 | Representation dependence testing using program inversionabstractThe definition of a data structure may permit many different concrete representations of the same logical content. A (client) program that accepts such a data structure as input is said to have a representation dependence if its behavior differs for logically equivalent input values. In this paper, we present a methodology and tool for automated testing of clients of a data structure for representation dependence. In the proposed methodology, the developer expresses the logical equivalence by writing a normalization program f that maps each concrete representation to a canonical one. Our solution relies on automatically synthesizing the one-to-many inverse function of f: given an input value x, we can generate multiple test inputs logically equivalent to x by executing the inverse with the canonical value f(x) as input repeatedly. We present an inversion algorithm for restricted classes of normalization programs including programs mapping arrays to arrays in a typical iterative manner. We present a prototype implementation of the algorithm, and demonstrate how our methodology reveals bugs due to representation dependence in open source software such as Open Office and Picasa using the widely used image format TIFF. TIFF is a challenging case study for our approach. Aditya Kanade 0001, Rajeev Alur, Sriram K. Rajamani, G. Ramalingam |
SIGSOFT FSE | 2 |
| 2010 | Temporal Reasoning for Procedural Programs
Rajeev Alur, Swarat Chaudhuri |
VMCAI | 1 |
| 2010 | Active Learning of Plans for Safety and Reachability Goals With Partial ObservabilityabstractTraditional planning assumes reachability goals and/or full observability. In this paper, we propose a novel solution for safety and reachability planning with partial observability. Given a planning domain, a safety property, and a reachability goal, we automatically learn a safe permissive plan to guide the planning domain so that the safety property is not violated and that can force the planning domain to eventually reach states that satisfy the reachability goal, regardless of how the planning domain behaves. Our technique is based on the active learning of regular languages and symbolic model checking. The planning method first learns a safe plan using the L (*) algorithm, which is an efficient active learning algorithm for regular languages. We then check whether the safe plan learned is also permissive by Alternating-time Temporal Logic (ATL) model checking. If the plan is permissive, it is indeed a safe permissive plan. Otherwise, we identify and add a safe string to converge a safe permissive plan. We describe an implementation of the proposed technique and demonstrate that our tool can efficiently construct safe permissive plans for four sets of examples. Wonhong Nam, Rajeev Alur |
IEEE Trans. Syst. Man Cybern. Part B | 2 |
| 2009 | Automated Analysis of Java Methods for Confidentiality
Pavol Cerný, Rajeev Alur |
CAV | 2 |
| 2009 | Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models
Aditya Kanade 0001, Rajeev Alur, Franjo Ivancic, S. Ramesh 0002, Sriram Sankaranarayanan 0001, K. C. Shashidhar |
CAV | 2 |
| 2009 | Temporal Reasoning about Program Executions
Rajeev Alur |
FoSSaCS | 1 |
| 2009 | On Omega-Languages Defined by Mean-Payoff Conditions
Rajeev Alur, Aldric Degorre, Oded Maler, Gera Weiss |
FoSSaCS | 1 |
| 2009 | Specification and Analysis of Network Resource Requirements of Control Systems
Gera Weiss, Sebastian Fischmeister, Madhukar Anand, Rajeev Alur |
HSCC | 4 |
| 2009 | Modeling and Analysis of Multi-hop Control NetworksabstractWe propose a mathematical framework, inspired by the Wireless HART specification, for modeling and analyzing multi-hop communication networks. The framework is designed for systems consisting of multiple control loops closed over a multi-hop communication network. We separate control, topology, routing, and scheduling and propose formal syntax and semantics for the dynamics of the composed system. The main technical contribution of the paper is an explicit translation of multi-hop control networks to switched systems. We describe a Mathematica notebook that automates the translation of multihop control networks to switched systems, and use this tool to show how techniques for analysis of switched systems can be used to address control and networking co-design challenges. Rajeev Alur, Alessandro D'Innocenzo, Karl Henrik Johansson, George J. Pappas, Gera Weiss |
IEEE Real-Time and Embedded Technology and Applications Symposium | 1 |
| 2009 | Adding nesting structure to wordsabstractWe propose the model of nested words for representation of data with both a linear ordering and a hierarchically nested matching of items. Examples of data with such dual linear-hierarchical structure include executions of structured programs, annotated linguistic data, and HTML/XML documents. Nested words generalize both words and ordered trees, and allow both word and tree operations. We define nested word automata —finite-state acceptors for nested words, and show that the resulting class of regular languages of nested words has all the appealing theoretical properties that the classical regular word languages enjoys: deterministic nested word automata are as expressive as their nondeterministic counterparts; the class is closed under union, intersection, complementation, concatenation, Kleene-*, prefixes, and language homomorphisms; membership, emptiness, language inclusion, and language equivalence are all decidable; and definability in monadic second order logic corresponds exactly to finite-state recognizability. We also consider regular languages of infinite nested words and show that the closure properties, MSO-characterization, and decidability of decision problems carry over. The linear encodings of nested words give the class of visibly pushdown languages of words, and this class lies between balanced languages and deterministic context-free languages. We argue that for algorithmic verification of structured programs, instead of viewing the program as a context-free language over words, one should view it as a regular language of nested words (or equivalently, a visibly pushdown language), and this would allow model checking of many properties (such as stack inspection, pre-post conditions) that are not expressible in existing specification logics. We also study the relationship between ordered trees and nested words, and the corresponding automata: while the analysis complexity of nested word automata is the same as that of classical tree automata, they combine both bottom-up and top-down traversals, and enjoy expressiveness and succinctness benefits over tree automata. Rajeev Alur, P. Madhusudan |
J. ACM | 1 |
| 2008 | Ranking Automata and Games for Prioritized Requirements
Rajeev Alur, Aditya Kanade 0001, Gera Weiss |
CAV | 1 |
| 2008 | Symbolic analysis for improving simulation coverage of Simulink/Stateflow modelsabstractAimed at verifying safety properties and improving simula-tion coverage for hybrid systems models of embedded control software, we propose a technique that combines numerical simulation and symbolic methods for computing state-sets. We consider systems with linear dynamics described in the commercial modeling tool Simulink/Stateflow. Given an ini-tial state x, and a discrete-time simulation trajectory, our method computes a set of initial states that are guaranteed to be equivalent to x, where two initial states are consid-ered to be equivalent if the resulting simulation trajectories contain the same discrete components at each step of the simulation. We illustrate the benefits of our method on two case studies. One case study is a benchmark proposed in the literature for hybrid systems verification and another is a Simulink demo model from Mathworks. Rajeev Alur, Aditya Kanade 0001, S. Ramesh 0002, K. C. Shashidhar |
EMSOFT | 1 |
| 2008 | RTComposer: a framework for real-time components with scheduling interfacesabstractWe present a framework for component-based design and scheduling of real-time embedded software. Each component has a clearly specified interface that includes the methods used for sensing, computation, and actuation, along with a requirement given as a regular set of macro-schedules. Each macro-schedule is an infinite sequence that specifies, for every time slot, the set of component methods invoked in that slot. The macro-scheduler composes the specifications of all the components, along with the platform specification that constrains which methods can be executed within a single slot, to generate a feasible macro-schedule. Within a slot, we use logical execution time semantics, and this micro-scheduling is implemented on top of a native priority-based scheduler. With this approach, each component can be specified and analyzed in a platform-independent way, and at the same time, the performance can vary with changing load and changing processing speed. We describe an implementation using Real-Time Java. Scheduling specifications can be given as periodic tasks, or using temporal logic, or as omega-automata. Components can be added dynamically, and non-real-time components are allowed. We demonstrate the benefits of the approach using case studies. Rajeev Alur, Gera Weiss |
EMSOFT | 1 |
| 2008 | Regular Specifications of Resource Requirements for Embedded Control SoftwareabstractFor embedded control systems, a schedule for the allocation of resources to a software component can be described by an infinite word whose ith symbol models the resources used at the ith sampling interval. Dependency of performance on schedules can be formally modeled by an automaton (omega-regular language) which captures all the schedules that keep the system within performance requirements. We show how such an automaton is constructed for linear control designs and exponential stability or settling time performance requirements. Then, we explore the use of the automaton for online scheduling and for schedulability analysis. As a case study, we examine how this approach can be applied for the LQG control design. We demonstrate, by examples, that online schedulers can be used to guarantee performance in worst-case condition together with good performance in normal conditions. We also provide examples of schedulability analysis. Rajeev Alur, Gera Weiss |
IEEE Real-Time and Embedded Technology and Applications Symposium | 1 |
| 2008 | Introduction
Rajeev Alur, George J. Pappas |
Formal Methods Syst. Des. | 1 |
| 2008 | Automatic symbolic compositional verification by learning assumptions
Wonhong Nam, P. Madhusudan, Rajeev Alur |
Formal Methods Syst. Des. | 3 |
| 2008 | First-Order and Temporal Logics for Nested WordsabstractNested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure of parse trees and other tree-structured data, such as XML. We provide new temporal logics for finite and infinite nested words, which are natural extensions of LTL, and prove that these logics are first-order expressively-complete. One of them is based on adding a "within" modality, evaluating a formula on a subword, to a logic CaRet previously studied in the context of verifying properties of recursive state machines (RSMs). The other logic, NWTL, is based on the notion of a summary path that uses both the linear and nesting structures. For NWTL we show that satisfiability is EXPTIME-complete, and that model-checking can be done in time polynomial in the size of the RSM model and exponential in the size of the NWTL formula (and is also EXPTIME-complete). Finally, we prove that first-order logic over nested words has the three-variable property, and we present a temporal logic for nested words which is complete for the two-variable fragment of first-order. Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin |
Log. Methods Comput. Sci. | 1 |
| 2007 | First-Order and Temporal Logics for Nested WordsabstractNested words are a structured model of execution paths in procedural programs, reflecting their call and return nesting structure. Finite nested words also capture the structure of parse trees and other tree-structured data, such as XML. We provide new temporal logics for finite and infinite nested words, which are natural extensions of LTL, and prove that these logics are first-order expressively- complete. One of them is based on adding a "within" modality, evaluating a formula on a subword, to a logic CaRet previously studied in the context of verifying properties of recursive state machines. The other logic is based on the notion of a summary path that combines the linear and nesting structures. For that logic, both model-checking and satisfiability are shown to be EXPTIME-complete. Finally, we prove that first-order logic over nested words has the three-variable property, and we present a temporal logic for nested words which is complete for the two- variable fragment of first-order. Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin |
LICS | 1 |
| 2007 | CheckFence: checking consistency of concurrent data types on relaxed memory modelsabstractConcurrency libraries can facilitate the development of multi-threaded programs by providing concurrent implementations of familiar data types such as queues or sets. There exist many optimized algorithms that can achieve superior performance on multiprocessors by allowing concurrent data accesses without using locks. Unfortunately, such algorithms can harbor subtle concurrency bugs. Moreover, they requirememory ordering fences to function correctly on relaxed memory models. Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin |
PLDI | 2 |
| 2007 | Marrying words and treesabstractTraditionally, data that has both linear and hierarchical structure, such as annotated linguistic data, is modeled using ordered trees and queried using tree automata. In this paper, we argue that nested words and automata over nested words offer a better way to capture and process the dual structure. Nested words generalize both words and ordered trees, and allow both word and tree operations. We study various classes of automata over nested words, and show that while they enjoy expressiveness and succinctness benefits over word and tree automata, their analysis complexity and closure properties are analogous to the corresponding word and tree special cases. In particular, we show that finite-state nested word automata can be exponentially more succinct than tree automata, and pushdown nested word automata include the two incomparable classes of context-free word languages and context-free tree languages. Rajeev Alur |
PODS | 1 |
| 2007 | Model Checking on Trees with Path Equivalences
Rajeev Alur, Pavol Cerný, Swarat Chaudhuri |
TACAS | 1 |
| 2007 | Dispatch sequences for embedded control models
Rajeev Alur, Arun Chandrashekharapuram |
J. Comput. Syst. Sci. | 1 |
| 2006 | Learning-Based Symbolic Assume-Guarantee Reasoning with Automatic Decomposition
Wonhong Nam, Rajeev Alur |
ATVA | 2 |
| 2006 | Languages of Nested Trees
Rajeev Alur, Swarat Chaudhuri, P. Madhusudan |
CAV | 1 |
| 2006 | Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin |
CAV | 2 |
| 2006 | Adding Nesting Structure to Words
Rajeev Alur, P. Madhusudan |
Developments in Language Theory | 1 |
| 2006 | Time-triggered implementations of dynamic controllersabstractBridging the gap between model-based design and platform-based implementation is one of the critical challenges for embedded software systems.In the context of embedded control systems that interact with an environment, a variety of errors due to quantization, delays, and scheduling policies may generate executable code that does not faithfully implement the model-based design. In this paper, we show that the performance gap between the model-level semantics of proportional-integral-derivative (PID) controllers and their implementation-level semantics can be rigorously quantified if the controller implementation is executed on a predictable time-triggered architecture. Our technical approach uses lifting techniques for periodic, time-varying linear systems in order to compute the exact error between the model semantics and the execution semantics. Explicitly computing the impact of the implementation on overall system performance allows us to compare and partially order different implementations with various scheduling or timing characteristics. Truong Nghiem, George J. Pappas, Rajeev Alur, Antoine Girard |
EMSOFT | 3 |
| 2006 | Branching Pushdown Tree Automata
Rajeev Alur, Swarat Chaudhuri |
FSTTCS | 1 |
| 2006 | Preserving Secrecy Under Refinement
Rajeev Alur, Pavol Cerný, Steve Zdancewic |
ICALP (2) | 1 |
| 2006 | Games for formal design and verification of reactive systemsabstractSummary form only given. With recent advances in algorithms for state-space traversal and in techniques for automatic abstraction of source code, model checking has emerged as a key tool for analyzing and debugging software systems. This talk discusses the role of games in modeling and analysis of software systems. Games are useful in modeling open systems where the distinction among the choices controlled by different components is made explicit. We first describe the model checker Mocha that supports a game-based temporal logic for writing requirements, and its applications to analysis of multi-party security protocols. Then, we describe how to automatically extract dynamic interfaces for Java classes using predicate abstraction for extracting a Boolean model from a class file, and learning algorithms for constructing the most general strategy for invoking the methods of the model. We discuss an implementation in the tool JIST - Java Interface Synthesis Tool and demonstrate that the tool can construct interfaces, accurately and efficiently, for sample Java2SDK library' classes Rajeev Alur |
MEMOCODE | 1 |
| 2006 | A fixpoint calculus for local and global program flowsabstractWe define a new fixpoint modal logic, the visibly pushdown μ-calculus (VP-μ), as an extension of the modal μ-calculus. The models of this logic are execution trees of structured programs where the procedure calls and returns are made visible. This new logic can express pushdown specifications on the model that its classical counterpart cannot, and is motivated by recent work on visibly pushdown languages [4]. We show that our logic naturally captures several interesting program specifications in program verification and dataflow analysis. This includes a variety of program specifications such as computing combinations of local and global program flows, pre/post conditions of procedures, security properties involving the context stack, and interprocedural dataflow analysis properties. The logic can capture flow-sensitive and inter-procedural analysis, and it has constructs that allow skipping procedure calls so that local flows in a procedure can also be tracked. The logic generalizes the semantics of the modal μ-calculus by considering summaries instead of nodes as first-class objects, with appropriate constructs for concatenating summaries, and naturally captures the way in which pushdown models are model-checked. The main result of the paper is that the model-checking problem for VP-μ is effectively solvable against pushdown models with no more effort than that required for weaker logics such as CTL. We also investigate the expressive power of the logic VP-μ: we show that it encompasses all properties expressed by a corresponding pushdown temporal logic on linear structures (caret [2]) as well as by the classical μ-calculus. This makes VP-μ the most expressive known program logic for which algorithmic software model checking is feasible. In fact, the decidability of most known program logics (μ-calculus, temporal logics LTL and CTL, caret, etc.) can be understood by their interpretation in the monadic second-order logic over trees. This is not true for the logic VP-μ, making it a new powerful tractable program logic. Rajeev Alur, Swarat Chaudhuri, P. Madhusudan |
POPL | 1 |
| 2006 | Counterexample-guided predicate abstraction of hybrid systems
Rajeev Alur, Thao Dang 0001, Franjo Ivancic |
Theor. Comput. Sci. | 1 |
| 2006 | Modular strategies for recursive game graphs
Rajeev Alur, Salvatore La Torre, P. Madhusudan |
Theor. Comput. Sci. | 1 |
| 2006 | Predicate abstraction for reachability analysis of hybrid systemsabstractEmbedded systems are increasingly finding their way into a growing range of physical devices. These embedded systems often consist of a collection of software threads interacting concurrently with each other and with a physical, continuous environment. While continuous dynamics have been well studied in control theory, and discrete and distributed systems have been investigated in computer science, the combination of the two complexities leads us to the recent research on hybrid systems . This paper addresses the formal analysis of such hybrid systems. Predicate abstraction has emerged to be a powerful technique for extracting finite-state models from infinite-state discrete programs. This paper presents algorithms and tools for reachability analysis of hybrid systems by combining the notion of predicate abstraction with recent techniques for approximating the set of reachable states of linear systems using polyhedra. Given a hybrid system and a set of predicates, we consider the finite discrete quotient whose states correspond to all possible truth assignments to the input predicates. The tool performs an on-the-fly exploration of the abstract system. We present the basic techniques for guided search in the abstract state-space, optimizations of these techniques, implementation of these in our verifier, and case studies demonstrating the promise of the approach. We also address the completeness of our abstraction-based verification strategy by showing that predicate abstraction of hybrid systems can be used to prove bounded safety. Rajeev Alur, Thao Dang 0001, Franjo Ivancic |
ACM Trans. Embed. Comput. Syst. | 1 |
| 2005 | Symbolic Compositional Verification by Learning Assumptions
Rajeev Alur, P. Madhusudan, Wonhong Nam |
CAV | 1 |
| 2005 | The Benefits of Exposing Calls and Returns
Rajeev Alur |
CONCUR | 1 |
| 2005 | Congruences for Visibly Pushdown Languages
Rajeev Alur, Viraj Kumar, P. Madhusudan, Mahesh Viswanathan 0001 |
ICALP | 1 |
| 2005 | Synthesis of interface specifications for Java classesabstractWhile a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequencing of method calls the client must invoke is usually undocumented. In this paper, we propose a novel solution for automatically extracting such temporal specifications for Java classes. Given a Java class, and a safety property such as “the exception E should not be raised”, the corresponding (dynamic) interface is the most general way of invoking the methods in the class so that the safety property is not violated. Our synthesis method first constructs a symbolic representation of the finite state-transition system obtained from the class using predicate abstraction. Constructingthe interface then corresponds to solving a partial-information two-player game on this symbolic graph. We present a sound approach to solve this computationally-hard problem approximately using algorithms for learning finite automata and symbolic model checking for branching-time logics. We describe an implementation of the proposed techniques in the tool JIST — Java Interface Synthesis Tool—and demonstrate that the tool can construct interfaces accurately and efficiently for sample Java2SDK library classes. Categories and Subject Descriptors: D.2.4 [Software Engineering] Software/Program Verification-formal methods, model checking; D.2.1 [Software Engineering] Requirements/Specification-methodologies, tools; D.2.2 [Software Rajeev Alur, Pavol Cerný, P. Madhusudan, Wonhong Nam |
POPL | 1 |
| 2005 | Dispatch Sequences for Embedded Control ModelsabstractWe consider the problem of mapping a set of control components to an executable implementation. The standard approach to this problem involves mapping control blocks to periodic tasks, and then generating a schedule. This schedule is platform-dependent, and its execution requires real-time operating system support. We propose an alternative approach which involves generating a dispatch sequence of control blocks in a platform-independent manner. Our solution relies on assigning relative complexity and relative importance measures to control components, and is an adaptation of classical scheduling algorithms such as earliest-deadline-first. We show the benefits of our approach using simulation experiments on two case studies. Rajeev Alur, Arun Chandrashekharapuram |
IEEE Real-Time and Embedded Technology and Applications Symposium | 1 |
| 2005 | Quantifying the Gap between Embedded Control Models and Time-Triggered ImplementationsabstractMapping a set of feedback control components to executable code introduces errors due to a variety of factors such as discretization, computational delays, and scheduling policies. We argue that the gap between the model and the implementation can be rigorously quantified leading to predictability if the implementation is viewed as a sequence of control blocks executed in statically allocated time slots on a time-triggered platform. For linear systems controlled by linear controllers, we show how to calculate the exact error between the model-level semantics and the execution semantics of an implementation, allowing us to compare different implementations. The calculated error of different implementations is demonstrated using simulations on illustrative examples Hakan Yazarel, Antoine Girard, George J. Pappas, Rajeev Alur |
RTSS | 4 |
| 2005 | On-the-Fly Reachability and Cycle Detection for Recursive State Machines
Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, P. Madhusudan |
TACAS | 1 |
| 2005 | Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin |
VMCAI | 2 |
| 2005 | Deciding Global Partial-Order Properties
Rajeev Alur, Kenneth L. McMillan, Doron A. Peled |
Formal Methods Syst. Des. | 1 |
| 2005 | Symbolic computational techniques for solving games
Rajeev Alur, P. Madhusudan, Wonhong Nam |
Int. J. Softw. Tools Technol. Transf. | 1 |
| 2005 | Realizability and verification of MSC graphs
Rajeev Alur, Kousha Etessami, Mihalis Yannakakis |
Theor. Comput. Sci. | 1 |
| 2005 | PrefaceabstractNo abstract available. Rajeev Alur, Insup Lee 0001 |
ACM Trans. Embed. Comput. Syst. | 1 |
| 2005 | Analysis of recursive state machinesabstractRecursive state machines (RSMs) enhance the power of ordinary state machines by allowing vertices to correspond either to ordinary states or to potentially recursive invocations of other state machines. RSMs can model the control flow in sequential imperative programs containing recursive procedure calls. They can be viewed as a visual notation extending Statecharts-like hierarchical state machines, where concurrency is disallowed but recursion is allowed. They are also related to various models of pushdown systems studied in the verification and program analysis communities.After introducing RSMs and comparing their expressiveness with other models, we focus on whether verification can be efficiently performed for RSMs. Our first goal is to examine the verification of linear time properties of RSMs. We begin this study by dealing with two key components for algorithmic analysis and model checking, namely, reachability (Is a target state reachable from initial states?) and cycle detection (Is there a reachable cycle containing an accepting state?). We show that both these problems can be solved in time O ( n θ 2 ) and space O ( n θ), where n is the size of the recursive machine and θ is the maximum, over all component state machines, of the minimum of the number of entries and the number of exits of each component. From this, we easily derive algorithms for linear time temporal logic model checking with the same complexity in the model. We then turn to properties in the branching time logic CTL*, and again demonstrate a bound linear in the size of the state machine, but only for the case of RSMs with a single exit node. Rajeev Alur, Michael Benedikt, Kousha Etessami, Patrice Godefroid, Thomas W. Reps, Mihalis Yannakakis |
ACM Trans. Program. Lang. Syst. | 1 |
| 2004 | Games for Formal Design and Verification of Reactive Systems
Rajeev Alur |
ATVA | 1 |
| 2004 | A model-based approach to integrating security policies for embedded devicesabstractEmbedded devices like smartcards can now run multiple interacting applications. A particular challenge in this domain is to dynamically integrate diverse security policies. In this paper we show how a framework based on a concise formal model lets us securely customize a payment card equipped with a programmable chip. We present policy automata, a formal model of computations that grant or deny access to a resource. This model combines defeasible logic with state machines, representing complex policies as combinations of simpler modular policies. We use the model in a framework for specifying, merging and analyzing modular policies. This framework is implemented as Polaris, a tool which analyzes policy automata to reveal potential conflicts or redundancies, and compiles automata into Java Card applets. Michael McDougall, Rajeev Alur, Carl A. Gunter |
EMSOFT | 2 |
| 2004 | Variable Reuse for Efficient Image Computation
Zijiang Yang 0006, Rajeev Alur |
FMCAD | 2 |
| 2004 | Optimal Reachability for Weighted Timed Games
Rajeev Alur, Mikhail Bernadsky, P. Madhusudan |
ICALP | 1 |
| 2004 | Visibly pushdown languagesabstractWe propose the class of visibly pushdown languages as embeddings of context-free languages that is rich enough to model program analysis questions and yet is tractable and robust like the class of regular languages. In our definition, the input symbol determines when the pushdown automaton can push or pop, and thus the stack depth at every position. We show that the resulting class Vpl of languages is closed under union, intersection, complementation, renaming, concatenation, and Kleene-*, and problems such as inclusion that are undecidable for context-free languages are Exptime-complete for visibly pushdown automata. Our framework explains, unifies, and generalizes many of the decision procedures in the program analysis literature, and allows algorithmic verification of recursive programs with respect to many context-free properties including access control properties via stack inspection and correctness of procedures with respect to pre and post conditions. We demonstrate that the class Vpl is robust by giving two alternative characterizations: a logical characterization using the monadic second order (MSO) theory over words augmented with a binary matching predicate, and a correspondence to regular tree languages. We also consider visibly pushdown languages of infinite words and show that the closure properties, MSO-characterization and the characterization in terms of regular trees carry over. The main difference with respect to the case of finite words turns out to be determinizability: nondeterministic Büchi visibly pushdown automata are strictly more expressive than deterministic Muller visibly pushdown automata. Rajeev Alur, P. Madhusudan |
STOC | 1 |
| 2004 | A Temporal Logic of Nested Calls and Returns
Rajeev Alur, Kousha Etessami, P. Madhusudan |
TACAS | 1 |
| 2004 | Polyhedral Flows in Hybrid Automata
Rajeev Alur, Sampath Kannan, Salvatore La Torre |
Formal Methods Syst. Des. | 1 |
| 2004 | Formal specifications and analysis of the computer-assisted resuscitation algorithm (CARA) Infusion Pump Control System
Rajeev Alur, David Arney, Elsa L. Gunter, Insup Lee 0001, Jaime Lee, Wonhong Nam, Frederick Pearce, Stephen Van Albert, Jiaxiang Zhou |
Int. J. Softw. Tools Technol. Transf. | 1 |
| 2004 | Optimal paths in weighted timed automata
Rajeev Alur, Salvatore La Torre, George J. Pappas |
Theor. Comput. Sci. | 1 |
| 2004 | Deterministic generators and games for Ltl fragmentsabstractDeciding infinite two-player games on finite graphs with the winning condition specified by a linear temporal logic (Ltl) formula, is known to be 2Exptime-complete. In this paper, we identify Ltl fragments of lower complexity. Solving Ltl games typically involves a doubly exponential translation from Ltl formulas to deterministic ω-automata. First, we show that the longest distance (length of the longest simple path) of the generator is also an important parameter, by giving an O ( d log n )-space procedure to solve a Büchi game on a graph with n vertices and longest distance d . Then, for the Ltl fragment of the Boolean combinations of formulas obtained only by eventualities and conjunctions, we provide a translation to deterministic generators of exponential size and linear longest distance, show both of these bounds to be optimal, and prove the corresponding games to be Pspace-complete. Introducing next modalities in this fragment, we give a translation to deterministic generators still of exponential size but also with exponential longest distance, show both of these bounds to be optimal, and prove the corresponding games to be Exptime-complete. For the fragment resulting by further adding disjunctions, we provide a translation to deterministic generators of doubly exponential size and exponential longest distance, show both of these bounds to be optimal, and prove the corresponding games to be Expspace. We also show tightness of the double exponential bound on the size as well as the longest distance for deterministic generators of Ltl formulas without next and until modalities. Finally, we identify a class of deterministic Büchi automata corresponding to a fragment of Ltl with restricted use of always and until modalities, for which deciding games is Pspace-complete. Rajeev Alur, Salvatore La Torre |
ACM Trans. Comput. Log. | 1 |
| 2004 | Modular refinement of hierarchic reactive machinesabstractScalable formal analysis of reactive programs demands integration of modular reasoning techniques with existing analysis tools. Modular reasoning principles such as abstraction, compositional refinement, and assume-guarantee reasoning are well understood for architectural hierarchy that describes the communication structure between component processes, and have been shown to be useful. In this paper, we develop the theory of modular reasoning for behavior hierarchy that describes control structure using hierarchic modes. From Statecharts to UML, behavior hierarchy has been an integral component of many software design languages, but only syntactically. We present the hierarchic reactive modules language that retains powerful features such as nested modes, mode reuse, exceptions, group transitions, history, and conjunctive modes, and yet has a semantic notion of mode hierarchy. We present an observational trace semantics for modes that provides the basis for mode refinement. We show the refinement to be compositional with respect to the mode constructors, and develop an assume-guarantee reasoning principle. Rajeev Alur, Radu Grosu |
ACM Trans. Program. Lang. Syst. | 1 |
| 2003 | Modular Strategies for Infinite Games on Recursive Graphs
Rajeev Alur, Salvatore La Torre, P. Madhusudan |
CAV | 1 |
| 2003 | Compression of Partially Ordered Strings
Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, Sudipto Guha, Mihalis Yannakakis |
CONCUR | 1 |
| 2003 | Playing Games with Boxes and Diamonds
Rajeev Alur, Salvatore La Torre, P. Madhusudan |
CONCUR | 1 |
| 2003 | Generating embedded software from hierarchical hybrid modelsabstractBenefits of high-level modeling and analysis are significantly enhanced if code can be generated automatically from a model such that the correspondence between the model and the code is precisely understood. For embedded control software, hybrid systems is an appropriate modeling paradigm because it can be used to specify continuous dynamics as well as discrete switching between modes. Establishing a formal relationship between the mathematical semantics of a hybrid model and the actual executions of the corresponding code is particularly challenging due to sampling and switching errors. In this paper, we describe an approach to compile the modeling language Charon that allows hierarchical specifications of interacting hybrid systems. We show how to exploit the semantics of Charon to generate code from a model in a modular fashion, and identify sufficient conditions on the model that guarantee the absence of switching errors in the compiled code. The approach is illustrated by compiling a model for coordinated motion of legs for walking onto Sony's AIBO robot. Rajeev Alur, Franjo Ivancic, Jesung Kim, Insup Lee 0001, Oleg Sokolsky |
LCTES | 1 |
| 2003 | Counter-Example Guided Predicate Abstraction of Hybrid Systems
Rajeev Alur, Thao Dang 0001, Franjo Ivancic |
TACAS | 1 |
| 2003 | Modular Strategies for Recursive Game Graphs
Rajeev Alur, Salvatore La Torre, P. Madhusudan |
TACAS | 1 |
| 2003 | Hierarchical modeling and analysis of embedded systemsabstractThis paper describes the modeling language CHARON for modular design of interacting hybrid systems. The language allows specification of architectural as well as behavioral hierarchy and discrete as well as continuous activities. The modular structure of the language is not merely syntactic, but is exploited by analysis tools and is supported by a formal semantics with an accompanying compositional theory of refinement. We illustrate the benefits of CHARON in the design of embedded control software using examples from automated highways concerning vehicle coordination. Rajeev Alur, Thao Dang 0001, Joel M. Esposito, Yerang Hur, Franjo Ivancic, Vijay Kumar 0001, Insup Lee 0001, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky |
Proc. IEEE | 1 |
| 2003 | Inference of Message Sequence ChartsabstractSoftware designers draw message sequence charts for early modeling of the individual behaviors they expect from the concurrent system under design. Can they be sure that precisely the behaviors they have described are realizable by some implementation of the components of the concurrent system? If so, can we automatically synthesize concurrent state machines realizing the given MSCs? If, on the other hand, other unspecified and possibly unwanted scenarios are "implied" by their MSCs, can the software designer be automatically warned and provided the implied MSCs? In this paper, we provide a framework in which all these questions are answered positively. We first describe the formal framework within which one can derive implied MSCs and then provide polynomial-time algorithms for implication, realizability, and synthesis. Rajeev Alur, Kousha Etessami, Mihalis Yannakakis |
IEEE Trans. Software Eng. | 1 |
| 2002 | Predictable programs in barcodesabstractWe explore the challenges for making the programming interfaces for embedded devices open and safe, and present a prototype architecture for delivering verified programs using barcodes. In particular, we consider programs for microwave ovens, which provide a basic open API for controlling cooking times. In our architecture, recipes are written in Java, and their safety properties are formally verified using the model checker Spin. We use off-the-shelf utilities for compressing the byte code, and use two-dimensional barcodes for program delivery. We report on experiments that demonstrate the feasibility of the proposed architecture for predictability and delivery. Alwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur |
CASES | 4 |
| 2002 | Exploiting Behavioral Hierarchy for Efficient Model Checking
Rajeev Alur, Michael McDougall, Zijiang Yang 0006 |
CAV | 1 |
| 2002 | Visual Programming for Modeling and Simulation of Biomolecular Regulatory Networks
Rajeev Alur, Calin Belta, Franjo Ivancic, Vijay Kumar 0001, Harvey Rubin, Jonathan Schug, Oleg Sokolsky, Jonathan Webb |
HiPC | 1 |
| 2002 | Alternating-time temporal logicabstractTemporal logic comes in two varieties: linear-time temporal logic assumes implicit universal quantification over all paths that are generated by the execution of a system; branching-time temporal logic allows explicit existential and universal quantification over all paths. We introduce a third, more general variety of temporal logic: alternating-time temporal logic offers selective quantification over those paths that are possible outcomes of games, such as the game in which the system and the environment alternate moves. While linear-time and branching-time logics are natural specification languages for closed systems, alternating-time logics are natural specification languages for open systems. For example, by preceding the temporal operator "eventually" with a selective path quantifier, we can specify that in the game between the system and the environment, the system has a strategy to reach a certain state. The problems of receptiveness, realizability, and controllability can be formulated as model-checking problems for alternating-time formulas. Depending on whether or not we admit arbitrary nesting of selective path quantifiers and temporal operators, we obtain the two alternating-time temporal logics ATL and ATL*.ATL and ATL* are interpreted over concurrent game structures . Every state transition of a concurrent game structure results from a choice of moves, one for each player. The players represent individual components and the environment of an open system. Concurrent game structures can capture various forms of synchronous composition for open systems, and if augmented with fairness constraints, also asynchronous composition. Over structures without fairness constraints, the model-checking complexity of ATL is linear in the size of the game structure and length of the formula, and the symbolic model-checking algorithm for CTL extends with few modifications to ATL. Over structures with weak-fairness constraints, ATL model checking requires the solution of 1-pair Rabin games, and can be done in polynomial time. Over structures with strong-fairness constraints, ATL model checking requires the solution of games with Boolean combinations of Büchi conditions, and can be done in PSPACE. In the case of ATL*, the model-checking problem is closely related to the synthesis problem for linear-time formulas, and requires doubly exponential time. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman |
J. ACM | 1 |
| 2001 | Analysis of Recursive State Machines
Rajeev Alur, Kousha Etessami, Mihalis Yannakakis |
CAV | 1 |
| 2001 | Verifying Network Protocol Implementations by Symbolic Refinement Checking
Rajeev Alur, Bow-Yaw Wang |
CAV | 1 |
| 2001 | Realizability and Verification of MSC Graphs
Rajeev Alur, Kousha Etessami, Mihalis Yannakakis |
ICALP | 1 |
| 2001 | JMOCHA: A Model Checking Tool that Exploits Design StructureabstractModel checking is a practical tool for automated debugging of embedded software. In model checking, a high-level description of a system is compared against a logical correctness requirement to discover inconsistencies. Since model checking is based on exhaustive state-space exploration and the size of the state space of a design grows exponentially with the size of the description, scalability remains a challenge. We have thus developed techniques for exploiting modular design structure during model checking, and the model checker jMocha (Java MOdel-CHecking Algorithm) is based on this theme. Instead of manipulating unstructured state-transition graphs, it supports the hierarchical modeling framework of reactive modules. jMocha is a growing interactive software environment for specification, simulation and verification, and is intended as a vehicle for the development of new verification algorithms and approaches. It is written in Java and uses native C-code BDD libraries from VIS. jMocha offers: (1) a GUI that looks familiar to Windows/Java users; (2) a simulator that displays traces in a message sequence chart fashion; (3) requirements verification both by symbolic and enumerative model checking; (4) implementation verification by checking trace containment; (5) a proof manager that aids compositional and assume-guarantee reasoning; and (6) SLANG (Scripting LANGuage) for the rapid and structured development of new verification algorithms. jMocha is available publicly at; it is a successor and extension of the original Mocha tool that was entirely written in C. Rajeev Alur, Luca de Alfaro, Radu Grosu, Thomas A. Henzinger, M. Kang, Christoph M. Kirsch, Rupak Majumdar, Freddy Y. C. Mang, Bow-Yaw Wang |
ICSE | 1 |
| 2001 | Shared Variables Interaction DiagramsabstractScenario-based specifications offer an intuitive and visual way of describing design requirements of distributed software systems. For the communication paradigm based on messages, message sequence charts (MSC) offer a standardized and formal notation amenable to formal analysis. In this paper we define shared variables interaction diagrams (SVID) as the counterpart of MSCs when processes communicate via shared variables. After formally defining SVIDs, we develop an intuitive as well as formal definition of refinement for SVIDs. This notion provides a basis for systematically adding details to SVID requirements. Rajeev Alur, Radu Grosu |
ASE | 1 |
| 2001 | Deterministic Generators and Games for LTL FragmentsabstractDeciding infinite two-player games on finite graphs with the winning condition specified by a linear temporal logic (LTL) formula is known to be 2EXPTIME-complete. In this paper, we identify LTL fragments of lower complexity. Solving LTL games typically involves a doubly-exponential translation from LTL formulas to deterministic /spl omega/-automata. First, we show that the longest distance (length of the longest simple path) of the generator is also an important parameter, by giving an O(d log n)-space procedure to solve a Buchi game on a graph with n vertices and longest distance d. Then, for the LTL fragment with only eventualities and conjunctions, we provide a translation to deterministic generators of exponential size and linear longest distance, show both of these bounds to be optimal and prove the corresponding games to be PSPACE-complete. Introducing "next" modalities in this fragment, we provide a translation to deterministic generators that is still of exponential size but also with exponential longest distance, show both bounds to be optimal and prove the corresponding games to be EXPTIME-complete. For the fragment resulting by further adding disjunctions, we provide a translation to deterministic generators of doubly-exponential size and exponential longest distance, show both bounds to be optimal and prove the corresponding games to be EXPSPACE. Finally, we show tightness of the double-exponential bound on the size as well as the longest distance for deterministic generators for LTL, even in the absence of "next" and "until" modalities. Rajeev Alur, Salvatore La Torre |
LICS | 1 |
| 2001 | Partial-Order Reduction in Symbolic State-Space Exploration
Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani |
Formal Methods Syst. Des. | 1 |
| 2001 | Introduction
Rajeev Alur, Thomas A. Henzinger |
Inf. Comput. | 1 |
| 2001 | Parametric temporal logic for "model measuring"abstractWe extend the standard model checking paradigm of linear temporal logic, LTL, to a “model measuring” paradigm where one can obtain more quantitative information beyond a “Yes/No” answer. For this purpose, we define a parametric temporal logic , PLTL, which allows statements such as “a request p is followed in at most x steps by a response q ,” where x is a free variable. We show how one can, given a formula ***( x 1 ...,x k ) of PLTL and a system model K satisfies the property ***, but if so find valuations which satisfy various optimality criteria. In particular, we present algorithms for finding valuations which minimize (or maximize) the maximum (or minimum) of all parameters. Theses algorithms exhibit the same PSPACE complexity as LTL model checking. We show that our choice of syntax for PLTL lies at the threshold of decidability for parametric temporal logics, in that several natural extensions have undecidable “model measuring” problems. Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron A. Peled |
ACM Trans. Comput. Log. | 1 |
| 2001 | Model checking of hierarchical state machinesabstractModel checking is emerging as a practical tool for detecting logical errors in early stages of system design. We investigate the model checking of sequential hierarchical (nested) systems, i.e., finite-state machines whose states themselves can be other machines. This nesting ability is common in various software design methodologies, and is available in several commercial modeling tools. The straightforward way to analyze a hierarchical machine is to flatten it (thus incurring an exponential blow up) and apply a model-checking tool on the resulting ordinary FSM. We show that this flattening can be avoided. We develop algorithms for verifying linear-time requirements whose complexity is polynomial in the size of the hierarchical machine. We also address the verification of branching time requirements and provide efficient algorithms and matching lower bounds. Rajeev Alur, Mihalis Yannakakis |
ACM Trans. Program. Lang. Syst. | 1 |
| 2000 | Efficient Reachability Analysis of Hierarchical Reactive Machines
Rajeev Alur, Radu Grosu, Michael McDougall |
CAV | 1 |
| 2000 | Exploiting Hierarchical Structure for Efficient Formal Verification
Rajeev Alur |
CONCUR | 1 |
| 2000 | Automated Refinement Checking for Asynchronous Processes
Rajeev Alur, Radu Grosu, Bow-Yaw Wang |
FMCAD | 1 |
| 2000 | Inference of message sequence chartsabstractSoftware designers draw Message Sequence Charts for early modeling of the individual behaviors they expect from the concurrent system under design. Can they be sure that precisely the behaviors they have described are realizable by some implementation of the components of the concurrent system? If so, can one automatically synthesize concurrent state machines realizing the given MSCs? If, on the other hand, other unspecified and possibly unwanted scenarios are “implied” by their MSCs, can the software designer be automatically warned and provided the implied MSCs? Rajeev Alur, Kousha Etessami, Mihalis Yannakakis |
ICSE | 1 |
| 2000 | Modular Refinement of Hierarchic Reactive MachinesabstractScalable formal analysis of reactive programs demands integration of modular reasoning techniques with existing analysis tools. Principles such as abstraction, compositional refinement, and assume-guarantee reasoning are well understood for architectural hierarchy that describes the communication structure between component processes, and have been shown to be useful. In this paper, we develop the theory of modular reasoning for behavior hierarchy that describes control structure using hierarchic modes. From STATECHARTS to UML, behavior hierarchy has been an integral component of many software design languages, but only syntactically. We present the hierarchic reactive modules language that retains powerful features such as nested modes, mode reuse, exceptions, group transitions, history, and conjunctive modes, and yet has a semantic notion of mode hierarchy. We present an observational trace semantics for modes that provides the basis for mode refinement. We show the refinement to be compositional with respect to the mode constructors, and develop an assume-guarantee reasoning principle. Rajeev Alur, Radu Grosu |
POPL | 1 |
| 2000 | Model-Checking of Correctness Conditions for Concurrent ObjectsabstractThe notions of serializability, linearizability, and sequential consistency are used in the specification of concurrent systems. We show that the model checking problem for each of these properties can be cast in terms of the containment of one regular language in another regular language shuffled using a semicommutative alphabet. The three model checking problems are shown to be, respectively, in P space , in E xpspace , and undecidable. Rajeev Alur, Kenneth L. McMillan, Doron A. Peled |
Inf. Comput. | 1 |
| 2000 | Discrete abstractions of hybrid systemsabstractA hybrid system is a dynamical system with both discrete and continuous state changes. For analysis purposes, it is often useful to abstract a system in a way that preserves the properties being analysed while hiding the details that are of no interest. We show that interesting classes of hybrid systems can be abstracted to purely discrete systems while preserving all properties that are definable in temporal logic. The classes that permit discrete abstractions fall into two categories. Either the continuous dynamics must be restricted, as is the case for timed and rectangular hybrid systems, or the discrete dynamics must be restricted, as is the case for o-minimal hybrid systems. In this paper, we survey and unify results from both areas. Rajeev Alur, Thomas A. Henzinger, Gerardo Lafferriere, George J. Pappas |
Proc. IEEE | 1 |
| 1999 | Timed Automata
Rajeev Alur |
CAV | 1 |
| 1999 | Automating Modular Verification
Rajeev Alur, Luca de Alfaro, Thomas A. Henzinger, Freddy Y. C. Mang |
CONCUR | 1 |
| 1999 | "Next" Heuristic for On-the-Fly Model Checking
Rajeev Alur, Bow-Yaw Wang |
CONCUR | 1 |
| 1999 | Model Checking of Message Sequence Charts
Rajeev Alur, Mihalis Yannakakis |
CONCUR | 1 |
| 1999 | Communicating Hierarchical State Machines
Rajeev Alur, Sampath Kannan, Mihalis Yannakakis |
ICALP | 1 |
| 1999 | Parametric Temporal Logic for "Model Measuring"
Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron A. Peled |
ICALP | 1 |
| 1999 | Introduction
Rajeev Alur, Thomas A. Henzinger |
Formal Methods Syst. Des. | 1 |
| 1999 | Introduction
Rajeev Alur, Thomas A. Henzinger |
Formal Methods Syst. Des. | 1 |
| 1999 | Reactive Modules
Rajeev Alur, Thomas A. Henzinger |
Formal Methods Syst. Des. | 1 |
| 1999 | Undecidability of Partial Order Logics
Rajeev Alur, Doron A. Peled |
Inf. Process. Lett. | 1 |
| 1999 | Event-Clock Automata: A Determinizable Class of Timed Automata
Rajeev Alur, Limor Fix, Thomas A. Henzinger |
Theor. Comput. Sci. | 1 |
| 1998 | MOCHA: Modularity in Model Checking
Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran |
CAV | 1 |
| 1998 | Alternating Refinement Relations
Rajeev Alur, Thomas A. Henzinger, Orna Kupferman, Moshe Y. Vardi |
CONCUR | 1 |
| 1998 | Performance Evaluation and Prediction
Allen D. Malony, Rajeev Alur |
Euro-Par | 2 |
| 1998 | Efficient Formal Verification of Hierarchical Descriptions
Rajeev Alur |
FSTTCS | 1 |
| 1998 | Deciding Global Partial-Order Properties
Rajeev Alur, Kenneth L. McMillan, Doron A. Peled |
ICALP | 1 |
| 1998 | Membership Questions for Timed and Hybrid AutomataabstractTimed and hybrid automata are extensions of finite state machines for formal modeling of embedded systems with both discrete and continuous components. Reachability problems for these automata are well studied and have been implemented in verification tools. For the purpose of effective error reporting and testing, we consider the membership problems for such automata. We consider different types of membership problems depending on whether the path (i.e. edge sequence), or the trace (i.e. event sequence), or the timed trace (i.e. timestamped event sequence), is specified. We give comprehensive results regarding the complexity of these membership questions for different types of automata, such as timed automata and linear hybrid automata, with and without /spl epsiv/ transitions. In particular we give an efficient O(n/spl middot/m/sup 2/) algorithm for generating timestamps corresponding to a path of length n in a timed automaton with m clocks. This algorithm is implemented in the verifier COSPAN to improve its diagnostic feedback during timing verification. Second, we show that for automata without /spl epsiv/ transitions, the membership question is NP complete for different types of automata whether or not the timestamps are specified along with the trace. Third, we show that for automata with /spl epsiv/ transitions, the membership question is as hard as the reachability question even for timed traces: it is PSPACE complete for timed automata, and undecidable for slight generalizations. Rajeev Alur, Robert P. Kurshan, Mahesh Viswanathan 0001 |
RTSS | 1 |
| 1998 | Model Checking of Hierarchical State MachinesabstractModel checking is emerging as a practical tool for detecting logical errors in early stages of system design. We investigate the model checking of hierarchical (nested) systems, i.e. finite state machines whose states themselves can be other machines. This nesting ability is common in various software design methodologies and is available in several commercial modeling tools. The straightforward way to analyze a hierarchical machine is to flatten it (thus, incurring an exponential blow up) and apply a model checking tool on the resulting ordinary FSM. We show that this flattening can be avoided. We develop algorithms for verifying linear time requirements whose complexity is polynomial in the size of the hierarchical machine. We address also the verification of branching time requirements and provide efficient algorithms and matching lower bounds. Rajeev Alur, Mihalis Yannakakis |
SIGSOFT FSE | 1 |
| 1998 | Symbolic Exploration of transition Hierarchies
Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani |
TACAS | 1 |
| 1998 | Finitary FairnessabstractFairness is a mathematical abstraction: in a multiprogramming environment, fairness abstracts the details of admissible (“fair”) schedulers; in a distributed environment, fairness abstracts the relative speeds of processors. We argue that the standard definition of fairness often is unnecessarily weak and can be replaced by the stronger, yet still abstract, notion of finitary fairness. While standard weak fairness requires that no enabled transition is postponed forever, finitary weak fairness requires that for every computation of a system there is an unknown bound k such that no enabled transition is postponed more than k consecutive times. In general, the finitary restriction fin ( F ) of any given fairness requirement F is the union of all ω-regular safety properties contained in F . The adequacy of the proposed abstraction is shown in two ways. Suppose we prove a program property under the assumption of finitary fairness. In a multiprogramming environment, the program then satisfies the property for all fair finite-state schedulers. In a distributed environment, the program then satisfies the property for all choices of lower and upper bounds on the speeds (or timings) of processors. The benefits of finitary fairness are twofold. First, the proof rules for verifying liveness properties of concurrent programs are simplified: well-founded induction over the natural numbers is adequate to prove termination under finitary fairness. Second, the fundamental problem of consensus in a faulty asynchronous distributed environment can be solved assuming finitary fairness. Rajeev Alur, Thomas A. Henzinger |
ACM Trans. Program. Lang. Syst. | 1 |
| 1997 | Partial-Order Reduction in Symbolic State Space Exploration
Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani |
CAV | 1 |
| 1997 | Modularity for Timed and Hybrid Systems
Rajeev Alur, Thomas A. Henzinger |
CONCUR | 1 |
| 1997 | Alternating-time Temporal LogicabstractTemporal logic comes in two varieties: linear-time temporal logic assumes implicit universal quantification over all paths that are generated by system moves; branching-time temporal logic allows explicit existential and universal quantification over all paths. We introduce a third, more general variety of temporal logic: alternating-time temporal logic offers selective quantification over those paths that are possible outcomes of games, such as the game in which the system and the environment alternate moves. While linear-time and branching-time logics are natural specification languages for closed systems, alternating-time logics are natural specification languages for open systems. For example, by preceding the temporal operator "eventually" with a selective path quantifier, we can specify that in the game between the system and the environment, the system has a strategy to reach a certain state. Also the problems of receptiveness, realizability, and controllability can be formulated as model-checking problems for alternating-time formulas. Rajeev Alur, Thomas A. Henzinger, Orna Kupferman |
FOCS | 1 |
| 1997 | Model-Checking of Real-Time Systems: A Telecommunications Application (Experience Report)abstractWe describe the application of model checking tools to analyze a real-time software challenge in the design of Lucent Technologies' 5ESS telephone switching system.We use two tools: COSPAN for checking real-time properties, and TPWB for checking probabilistic specifications.We report on the feedback given by the tools, and based on our experience, discuss the advantages and the limitations of the approach used. Rajeev Alur, Lalita Jategaonkar Jagadeesan, Joseph J. Kott, James Von Olnhausen |
ICSE | 1 |
| 1997 | Computing Accumulated Delays in Real-time Systems
Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger |
Formal Methods Syst. Des. | 1 |
| 1997 | Time-Adaptive Algorithms for SynchronizationabstractWe consider concurrent systems in which there is an unknown upper bound on memory access time. Such a model is inherently different from the asynchronous model, where no such bound exists, and also from timing-based models, where such a bound exists and is known a priori. The appeal of our model lies in the fact that while it abstracts from implementation details, it is a better approximation of real concurrent systems than the asynchronous model. Furthermore, it is stronger than the asynchronous model, enabling us to design algorithms for problems that are unsolvable in the asynchronous model. Two basic synchronization problems, consensus and mutual exclusion, are investigated in a shared-memory environment that supports atomic read/write registers. We show that $\Theta(\Delta\frac{\log \Delta}{\log\log \Delta})$ is an upper and lowerbound on the time complexity of consensus, where $\Delta$ is the (unknown) upper bound on memory access time. For the mutual exclusion problem, we design an efficient algorithm that takes advantage of the fact that some upper bound on memory access time exists. The solutions for both problems are even more efficient in the absence of contention, in which case their time complexity is a constant. Rajeev Alur, Hagit Attiya, Gadi Taubenfeld |
SIAM J. Comput. | 1 |
| 1997 | Real-Time System = Discrete System + Clock Variables
Rajeev Alur, Thomas A. Henzinger |
Int. J. Softw. Tools Technol. Transf. | 1 |
| 1996 | Verifying Abstractions of Timed Systems
Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton |
CONCUR | 2 |
| 1996 | Reactive ModulesabstractWe present a formal model for concurrent systems. The model represents synchronous and asynchronous components in a uniform framework that supports compositional (assume-guarantee) and hierarchical (stepwise refinement) reasoning. While synchronous models are based on a notion of atomic computation step, and asynchronous models remove that notion by introducing stuttering, our model is based on a flexible notion of what constitutes a computation step: by applying an abstraction operator to a system, arbitrarily many consecutive steps can be collapsed into a single step. The abstraction operator, which may turn an asynchronous system into a synchronous one, allows us to describe systems at various levels of temporal detail. For describing systems at various levels of spatial detail, we use a hiding operator that may turn a synchronous system into an asynchronous one. We illustrate the model with diverse examples from synchronous circuits, asynchronous shared-memory programs, and synchronous message passing. Rajeev Alur, Thomas A. Henzinger |
LICS | 1 |
| 1996 | Model-Checking of Correctness Conditions for Concurrent ObjectsabstractThe notions of serializability, linearizability and sequential consistency are used in the specification of concurrent systems. We show that the model checking problem for each of these properties can be cast in terms of the containment of one regular language in another regular language shuffled using a semi-commutative alphabet. The three model checking problems are shown to be, respectively, in PSPACE, in EXPSPACE, and undecidable. Rajeev Alur, Kenneth L. McMillan, Doron A. Peled |
LICS | 1 |
| 1996 | Fast Timing-Based Algorithms
Rajeev Alur, Gadi Taubenfeld |
Distributed Comput. | 1 |
| 1996 | Contention-Free Complexity of Shared Memory Algorithms
Rajeev Alur, Gadi Taubenfeld |
Inf. Comput. | 1 |
| 1996 | The Benefits of Relaxing Punctuality
Rajeev Alur, Tomás Feder, Thomas A. Henzinger |
J. ACM | 1 |
| 1996 | Automatic Symbolic Verification of Embedded SystemsabstractPresents a model-checking procedure and its implementation for the automatic verification of embedded systems. The system components are described as hybrid automata-communicating machines with finite control and real-valued variables that represent continuous environment parameters such as time, pressure and temperature. The system requirements are specified in a temporal logic with stop-watches, and verified by symbolic fixpoint computation. The verification procedure-implemented in the Cornell Hybrid Technology tool, HyTech-applies to hybrid automata whose continuous dynamics is governed by linear constraints on the variables and their derivatives. We illustrate the method and the tool by checking safety, liveness, time-bounded and duration requirements of digital controllers, schedulers and distributed algorithms. Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho |
IEEE Trans. Software Eng. | 1 |
| 1995 | Local Liveness for Compositional Modeling of Fair Reactive Systems
Rajeev Alur, Thomas A. Henzinger |
CAV | 1 |
| 1995 | Model-Checking of Causality PropertiesabstractA temporal logic for causality (T/sub LC/) is introduced. The logic is interpreted over causal structures corresponding to partial order executions of programs. For causal structures describing the behavior of a finite fixed set of processes, a T/sub LC/-formula can, equivalently, be interpreted over their linearizations. The main result of the paper is a tableau construction that gives a singly-exponential translation from a T/sub LC/ formula /spl psi/ to a Streett automaton that accepts the set of linearizations satisfying /spl psi/. This allows both checking the validity of T/sub LC/ formulas and model-checking of program properties. As the logic T/sub LC/ does not distinguish among different linearizations of the same partial order execution, partial order reduction techniques can be applied to alleviate the state-space explosion problem of model-checking. Rajeev Alur, Doron A. Peled, Wojciech Penczek |
LICS | 1 |
| 1995 | Distinguishing tests for nondeterministic and probabilistic machinesabstractWe study the problem of uniquely identifying the initial state of a given finite-state machine from among a set of possible choices, based on the input-output behavior. Equivalently, given a set of machines, the problem is to design a test that distinguishes among them. We consider nondeterministic machines as well as probabilistic machines. In both cases, we show that it is Pspace-complete to decide whether there is a preset distinguishing strategy (i.e. a sequence of inputs fixed in advance), and it is Exptime-complete to decide whether there is an adaptive distinguishing strategy (i.e. when the next input can be chosen based on the outputs observed so far). The probabilistic testing is closely related to probabilistic games, or Markov Decision Processes, with incomplete information. We also provide optimal bounds for deciding whether such games have strategies winning with probability 1. 1 Introduction Finite-state machines have been widely used to model systems in diverse areas o... Rajeev Alur, Costas Courcoubetis, Mihalis Yannakakis |
STOC | 1 |
| 1995 | Timing Verification by Successive Approximation
Rajeev Alur, Alon Itai, Robert P. Kurshan, Mihalis Yannakakis |
Inf. Comput. | 1 |
| 1995 | The Algorithmic Analysis of Hybrid SystemsabstractWe present a general framework for the formal specification and algorithmic analysis of hybrid systems. A hybrid system consists of a discrete program with an analog environment. We model hybrid systems as finite automata equipped with variables that evolve continuously with time according to dynamical laws. For verification purposes, we restrict ourselves to linear hybrid systems, where all variables follow piecewise-linear trajectories. We provide decidability and undecidability results for classes of linear hybrid systems, and we show that standard program-analysis techniques can be adapted to linear hybrid systems. In particular, we consider symbolic model-checking and minimization procedures that are based on the reachability analysis of an infinite state space. The procedures iteratively compute state sets that are definable as unions of convex polyhedra in multidimensional real space. We also present approximation techniques for dealing with systems for which the iterative procedures do not converge. Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, Thomas A. Henzinger, Pei-Hsin Ho, Xavier Nicollin, Alfredo Olivero, Joseph Sifakis, Sergio Yovine |
Theor. Comput. Sci. | 1 |
| 1994 | A Determinizable Class of Timed Automata
Rajeev Alur, Limor Fix, Thomas A. Henzinger |
CAV | 1 |
| 1994 | The Observational Power of Clocks
Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger |
CONCUR | 1 |
| 1994 | Finitary FairnessabstractFairness is a mathematical abstraction: in a multiprogramming environment, fairness abstracts the details of admissible ("fair") schedulers; in a distributed environment, fairness abstracts the speeds of independent processors. We argue that the standard definition of fairness often is unnecessarily weak and can be replaced by the stronger, yet still abstract, notion of finitary fairness. While standard weak fairness requires that no enabled transition is postponed forever, finitary weak fairness requires that for every run of a system there is an unknown bound k such that no enabled transition is postponed more than k consecutive times. In general, the finitary restriction fin(F) of any given fairness assumption F is the union of all w-regular safety properties that are contained in F. The adequacy of the proposed abstraction is demonstrated in two ways. Suppose that we prove a program property under the assumption of finitary fairness. In a multiprogramming environment, the program then satisfies the property for all fair finite-state schedulers. In a distributed environment, the program then satisfies the property for all choices of lower and upper bounds on the speeds (or timings) of processors.> Rajeev Alur, Thomas A. Henzinger |
LICS | 1 |
| 1994 | Contention-free Complexity of Shared Memory AlgorithmsabstractWorst-case time complexity is a measure of the maximumtime needed to solve a problem over all runs. Contention-free time complexity indicates the maximum time needed when a process executes by itself, without competition from other processes. Since contention is rare in well-designed systems, it is important to design algorithms which perform well in the absence of contention. We study the contention-free time complexity of shared memory algorithms using two measures: step complexity, which counts the number of accesses to shared registers; and register complexity, which measures the number of different registers accessed. Depending on the system architecture, one of the two measures more accurately reflects the elapsed time. We provide lower and upper bounds for the contention-free step and register complexity of solving the mutual exclusion problem as a function of the number of processes and the size of the largest register that can be accessed in one atomic step. We also present bo... Rajeev Alur, Gadi Taubenfeld |
PODC | 1 |
| 1994 | Time-adaptive algorithms for synchronizationabstractWe consider concurrent systems in which there is an unknown upper bound on memory access time. Such a model is inherently different from asynchronous model where no such bound exists, and also from timing-based models where such a bound exists and is known a priori. The appeal of our model lies in the fact that while it abstracts from implementation details, it is a better approximation of real concurrent systems compared to the asynchronous model. Furthermore, it is stronger than the asynchronous model enabling us to design algorithms for problems that are unsolvable in the asynchronous model. Two basic synchronization problems, consensus and mutual exclusion, are investigated in a shared memory environment that supports atomic read/write registers. We show that \\Theta(\\Delta log \\Delta log log \\Delta ) is an upper and lower bound on the time complexity of consensus, where \\Delta is the (unknown) upper bound on memory access time. For the mutual exclusion problem, we design an effic... Rajeev Alur, Hagit Attiya, Gadi Taubenfeld |
STOC | 1 |
| 1994 | A Really Temporal LogicabstractWe introduce a temporal logic for the specification of real-time systems. Our logic, TPTL, employs a novel quantifier construct for referencing time: the freeze quantifier binds a variable to the time of the local temporal context. TPTL is both a natural language for specification and a suitable formalism for verification. We present a tableau-based decision procedure and a model-checking algorithm for TPTL. Several generalizations of TPTL are shown to be highly undecidable. Rajeev Alur, Thomas A. Henzinger |
J. ACM | 1 |
| 1994 | A Theory of Timed Automata
Rajeev Alur, David L. Dill |
Theor. Comput. Sci. | 1 |
| 1993 | Computing Accumulated Delays in Real-time Systems
Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger |
CAV | 1 |
| 1993 | Automatic Symbolic Verification of Embedded SystemsabstractWe present a model checking procedure and its implementation for the automatic verification of embedded systems. Systems are represented by hybrid automata - machines with finite control and real-valued variables modeling continuous environment parameters such as time, pressure, and temperature. System properties are specified in a real-time temporal logic and verified by symbolic computation. The verification procedure, implemented in Mathematica, is used to prove digital controllers and distributed algorithms correct. The verifier checks safety, liveness, time-bounded, and duration properties of hybrid automata.> Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho |
RTSS | 1 |
| 1993 | Parametric real-time reasoningabstract. Traditional approaches to the algorithmic verification of real-time systems are limited to checking program correctness with respect to concrete timing properties (e.g., "message delivery within 10 milliseconds"). We address the more realistic and more ambitious problem of deriving symbolic constraints on the timing properties required of real-time systems (e.g., "message delivery within the time it takes to execute two assignment statements"). To model this problem, we introduce parametric timed automata --- finite-state machines whose transitions are constrained with parametric timing requirements. The emptiness question for parametric timed automata is central to the verification problem. On the negative side, we show that in general this question is undecidable. On the positive side, we provide algorithms for checking the emptiness of restricted classes of parametric timed automata. The practical relevance of these classes is illustrated with several verification examples. There ... Rajeev Alur, Thomas A. Henzinger, Moshe Y. Vardi |
STOC | 1 |
| 1993 | Model-Checking in Dense Real-time
Rajeev Alur, Costas Courcoubetis, David L. Dill |
Inf. Comput. | 1 |
| 1993 | Real-Time Logics: Complexity and Expressiveness
Rajeev Alur, Thomas A. Henzinger |
Inf. Comput. | 1 |
| 1992 | Minimization of Timed Transition Systems
Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, David L. Dill, Howard Wong-Toi |
CONCUR | 1 |
| 1992 | Back to the Future: Towards a Theory of Timed Regular LanguagesabstractThe authors introduce two-way timed automata-timed automata that can move back and forth while reading a timed word. Two-wayness in its unrestricted form leads, like nondeterminism, to the undecidability of language inclusion. However, if they restrict the number of times an input symbol may be revisited, then two-wayness is both harmless and desirable. The authors show that the resulting class of bounded two-way deterministic timed automata is closed under all boolean operations, has decidable (PSPACE-complete) emptiness and inclusion problems, and subsumes all decidable real-time logics we know. They obtain a strict hierarchy of real-time properties: deterministic timed automata can accept more languages as the bound on the number of times an input symbol may be revisited is increased. This hierarchy is also enforced by the number of alternations between past and future operators in temporal logic. The combination of the results leads to a decision procedure for a real-time logic with past operators.> Rajeev Alur, Thomas A. Henzinger |
FOCS | 1 |
| 1992 | An implementation of three algorithms for timing verification based on automata emptinessabstractThree algorithms for checking the emptiness of a timed transition system have been implemented. The first algorithm performs a straightforward reachability analysis on sets of states of the system, rather than on individual states. This corresponds to stepping symbolically through the system many states at a time. The other two algorithms are minimization algorithms. These simultaneously perform reachability analysis and minimization from an implicit system description. The paradigm for verification is to test for the emptiness of the set of all timed system executions that violate a requirements specification. Preliminary results over two simple examples indicate that memory usage is a more limiting factor than time.> Rajeev Alur, Costas Courcoubetis, David L. Dill, Nicolas Halbwachs, Howard Wong-Toi |
RTSS | 1 |
| 1992 | Results about Fast Mutual ExclusionabstractA fast mutual exclusion algorithm where only five accesses to the shared memory are needed in order to enter a critical section in the absence of contention is presented. In the presence of contention, the winning process may need to delay itself for 3* Delta time units, where Delta is an upper bound on the time taken by the slowest process to execute a statement involving an access to the shared memory. It is also proven that there is not two (or more) process mutual exclusion algorithm with an upper bound on the number of times a winning process needs to access the shared memory in order to enter its critical section in the presence of contention. However, under the assumption that busy-waiting counts as just one step, the authors present, for every fixed parameter k, an algorithm with the property that from a state where no process tries to enter its critical section, as long as the number of contenders does not exceed k, the time complexity of the winning process is a linear function of k. Finally, the ideas from the mutual exclusion algorithm are used to implement a fast and simple consensus algorithm.> Rajeev Alur, Gadi Taubenfeld |
RTSS | 1 |
| 1991 | Model-Checking for Probabilistic Real-Time Systems (Extended Abstract)
Rajeev Alur, Costas Courcoubetis, David L. Dill |
ICALP | 1 |
| 1991 | The Benefits of Relaxing PunctualityabstractThe most natural, compositional, way of modeling real-time systems uses a dense domain for time.The satistiability of timing constraints that are capable of expressing punctuality in this model, however, is known to be undecidable.We introduce a temporal language that can constrain the time difference between events only with finite, yet arbitrary, precision and show the resulting logic to be EXPSPACE-complete.This result allows us to develop an algorithm for the verification of timing properties of real-time systems with a dense semantics. Rajeev Alur, Tomás Feder, Thomas A. Henzinger |
PODC | 1 |
| 1990 | Automata For Modeling Real-Time Systems
Rajeev Alur, David L. Dill |
ICALP | 1 |
| 1990 | Model-Checking for Real-Time SystemsabstractThis research extends CTL model-checking to the analysis of real-time systems, whose correctness depends on the magnitudes of the timing delays. For specifications, the syntax of CTL is extended to allow quantitative temporal operators. The formulas of the resulting logic, TCTL, are interpretation over continuous computation trees, trees in which paths are maps from the set of nonnegative reals to system states. To model finite-state systems the notion of timed graphs is introduced-state-transition graphs extended with a mechanism that allows the expression of constant bounds on the delays between the state transition. As the main result, an algorithm is developed for model checking, that is, for determining the truth of a TCTL formula with respect to a timed graph. It is argued that choosing a dense domain, instead of a discrete domain, to model time does not blow up the complexity of the model-checking problem. On the negative side, it is shown that the denseness of the underlying time domain makes TCTL II/sub 1//sup 1/-hard. The question of deciding whether a given TCTL formula is implementable by a timed graph is also undecidable.> Rajeev Alur, Costas Courcoubetis, David L. Dill |
LICS | 1 |
| 1990 | Real-time Logics: Complexity and ExpressivenessabstractA unifying framework for the study of real-time logics is developed. In analogy to the untimed case, the underlying classical theory of timed state sequences is identified, it is shown to be nonelementarily decidable, and its complexity and expressiveness are used as a point of reference. Two orthogonal extensions of PTL (timed propositional temporal logic and metric temporal logic) that inherit its appeal are defined: they capture elementary, yet expressively complete, fragments of the theory of timed state sequences, and thus are excellent candidates for practical real-time specification languages.> Rajeev Alur, Thomas A. Henzinger |
LICS | 1 |
| 1989 | A Really Temporal LogicabstractA real-time temporal logic for the specification of reactive systems is introduced. The novel feature of the logic, TPTL, is the adoption of temporal operators as quantifiers over time variables; every modality binds a variable to the time(s) it refers to. TPTL is demonstrated to be both a natural specification language and a suitable formalism for verification and synthesis. A tableau-based decision procedure and model-checking algorithm for TPTL are presented. Several generalizations of TPTL are shown to be highly undecidable.> Rajeev Alur, Thomas A. Henzinger |
FOCS | 1 |