Networks of workstations provide an economic solution for scalable computing because they do not require specialized components. Even though recent advances have shown that it is possible to obtain high bandwidth between applications, interconnect latency remains a serious concern. We present CNI, a cluster network interface that not only provides both low latency and high bandwidth but also efficiently supports multiple programming paradigms. This is done by functionally coupling the network adaptor board more closely to the CPU without changing the standard workstation architecture. CNI results in performance gains for applications, substantially reducing communication overhead and delay.

A new formal model for variable-delay simulators is presented for comparing the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous models. Using this new model the author shows that parallelism is not a nondecreasing function of time base. She bounds parallelism, however, by two functions that converge to the unit-delay parallelism as the time base increases, preserving the intuition that coarser timing models result in greater parallelism. In addition, the author corroborates the model predictions via an empirical study and discusses the impact of the results on synchronous and conservative asynchronous parallel simulations.>

The author addresses the issue of how well circuit parallelism scales with circuit size. Empirical studies using a single representation, switch-level, and two different timing models are presented. The results show that, in general, parallelism does not scale linearly with circuit size, and that the relationship between parallelism and circuit size is much more complex. The author first describes the simulators and methodology used to measure circuit parallelism. The circuit parallelism and percentage of parallelism of nine circuits, ranging in size from 200 to 61600 transistors, are described. Parallelism measurements from different instances of three circuit families are presented to show that, even within circuit families, relative parallelism is not constant for different instances.>

A model for studying the effects of timing models and synchronization strategies for event-driven parallel logic-level simulation is presented. Two timing models, variable-delay and unit-delay, and two synchronization strategies, synchronous and conservative asynchronous, are discussed. The average parallelism of circuits using the two timing models are compared, and the execution times of circuits using various timing models and synchronization strategies are considered. It is shown that the circuit parallelism using unit-delay timing provides an upper bound on that of any timebase used in variable-delay timing and that with either timing model, the execution time of the conservative asynchronous strategy is a lower bound over the synchronous strategy, assuming an unlimited number of processors. However, assuming that all events take the same amount of time, it is shown that with unit-delay timing, the execution time of the synchronous strategy equals that of the asynchronous strategy.>

The authors apply a formal model described by M.L. Bailey and L. Snyder (Distributed Simulation, SCS, 1989, p.157-63) to the more difficult problem of comparing three different synchronization strategies: synchronous, conservative asynchronous, and optimistic asynchronous. They show that with unlimited processors, for variable-delay and unit-delay timing, conservative>