This paper proposes the definition of core components of the healthcare domain that can be used as basic building blocks for the development of mHealth applications. Using Natural Language Processing techniques, we systematically analyze all health interventions defined in the Nursing Interventions Classification taxonomy to define a comprehensive set of basic components. Our results show that it is feasible to define a finite set of core components from the nursing domain language that can be further composed into health care plans thus establishing a foundation for developing mHealth solutions with reduced technical effort.

Summary Considering the constrained resources of mobile devices, a thorough performance evaluation of a mobile application is crucial. However, performance evaluation in the mobile domain is still a manual and time‐consuming task. The diversity of mobile devices only increases the complexity of this task. We propose EPE‐Mobile, a framework to automate early performance estimation in mobile applications. It is composed of a configurable library of basic operations and an engine that automatically creates a synthetic program based on the specification of a new app. The synthetic program that EPE‐Mobile generates provides feedback for mobile developers at the first design stages and before the actual implementation of a new application. The fast evaluation can also guide developers in optimizing their applications or in choosing devices with the best trade‐off between cost and performance to run a given application. Finally, developers can reuse the data collection infrastructure of the framework to collect performance data during all development stages. We validate the proposed framework using 4 applications from the Android Play Store. Based on their specifications, 4 synthetic programs were generated and executed on different devices. We compared the results to those obtained from the execution of the actual applications in the same devices. Experimental results show that it is possible to create synthetic applications with similar behavior to that of real applications and, thus, classify devices based on the actual application needs. The framework uses aspect‐oriented programming to collect the metrics of interest. This approach provides increased modularity and separation of concerns, thus facilitating the improvement of the framework itself, by adding other metrics or basic operations.

This paper proposes a strategy to assist the designer in evaluating the impact of a design choice with respect to the non-functional requirements in embedded systems. We use several regression models to predict physical metrics from design metrics in order to estimate the impact on performance of software changes in the early stages of its development. This prediction can be used both during maintenance and during the first design to compare alternative module decompositions or design changes before implementation. Such an early estimation allows an efficient design space exploration with no penalty in the development time, which are crucial aspects for an embedded system.

In this paper, a fault tolerance technique is proposed for the protection of NoC interconnects. The technique is based on data splitting and retransmission, providing for high NoC-based SoC reliability. For error detection, the proposed approach splits the communication data into two parity encoded halves. For error correction, only the erroneous half is doubled and retransmitted. Compared to the use of a conventional Hamming Code, we show that, for medium to large NoCs, the approach proposed in this work is less silicon costly, leads to the design of faster fault-free routers and, for the majority of faults, presents no performance degradation at system level.

In this paper, we propose a method to detect crosstalk faults within and among channels of mesh NoCs, using a global test strategy that is based on a particular set of test paths and test packet. All test paths must be activated simultaneously without resource conflict. The test packet is built using Maximal Aggressor Fault (MAF) vectors. The test strategy is capable of detecting 100% of the considered faults. The test application time grows quadratically with the NoC increase, but can be drastically improved by means of two alternative approaches also proposed in the paper. Those local approaches are based on simultaneously testing multiple victims or NoC regions unlikely to aggress each other. The test time then grows linearly and shows a very modest derivative.

This embedded tutorial presents an overview of the issues related to the test, diagnosis and fault-tolerance of Networks-on-chip (NoCs). The main motivation is the increasing interest on NoC-based designs in academia and industry. This new design option is becoming an important trend because of its advantages on tackling the challenges of a complex SoC design. However, to become a real standard or an industrial reality, it is important that the issues related to its testing are also well understood and dominated. Initially, the challenges to test and diagnose faults in NoCs are presented. A NoC is basically made up of three main components: network interface, routers and communication channels. To start with the network interface and routers, many works presented the problem of NoC testing suggesting that a wide variety of standard DfT solutions can be used. However, a deeper evaluation of the approaches brought from board-level and chip-level testing, shows that much better results, in terms of silicon overhead, test time and diagnosability, can be obtained if test approaches specific for NoCs are used. Testing and diagnosis of NoC channels is also important. The huge number of interconnects allied to the shrinking of the chip dimensions make the NoC prone to a growing number of interconnect faults. The capability of detecting interconnect faults in NoC-based SoCs is mandatory for yield improvement. Moreover, fault diagnosis of NoC interconnect links can help fault tolerance approaches to mitigate the faults and to maintain the network service. The most influent NoC test and diagnosis strategies are presented and comparatively discussed in this tutorial. In fact, the correctness of the on-chip network behavior is a feature that must be ensured, not only in test mode, but also during the mission of the system. In mission mode, all system communication is implemented through the NoC and designers assume a certain Quality of Service (QoS) level according to specific design techniques. However, current technologies are becoming quite sensitive to noise and cosmic particles that can cause transient faults. Thus, it is important to ensure that the NoC service is not compromised by those faults. This way, fault tolerance techniques for the communication infrastructure must be considered when designing a NoC-based system. Various techniques to detect and recover from transient and permanent faults are discussed in this embedded tutorial. For the last years a number of testing and fault tolerance approaches have been proposed for NoCs. Although this is a relatively new topic, current research covers already a considerable spectrum and its analysis at this point can help to summarize the scientific and technological advances made so far and to identify the open issues that still need to be tackled.

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

We propose a method to diagnose interconnect short-circuit faults in mesh 7oCs. The fault model comprises all shorts between any two wires of a defined 7oC neighborhood. Test sequences are applied in 7oC functional mode. Experimental results show that 93% of the interconnect shorts can be diagnosed.

In this work we analyze four techniques to protect a cryptographic core, which can be combined to allow for several implementations with different area overheads and protection levels. Experimental results show their efficiency in protecting the core against fault attacks, while being flexible enough to leave other design aspects to be explored by the core provider.

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.

This work intends to evaluate the effect of a single event upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an accurate analysis of the impact of SEU and crosstalk over the router service. Results show that such faults may affect the router behavior, causing loss of packets, errors in packet information or even compromising the router service, provoking permanent routing problems

As the technology scales down into deep sub-micron domain, more IP cores are integrated in the same die and new communication architectures are used to meet performance and power constraints. However, the same technologic advance makes devices and interconnects more sensitive to new types of malfunctions and failures, such as crosstalk and transient faults. This paper proposes fault tolerant techniques to protect NoC routers against the occurrence of soft errors and crosstalk at the same time, with minimum area and performance overhead. Experimental results show that a cost-effective protection alternative can be achieved by the combination of error correction codes and time redundancy techniques

On-chip integrated network, the so-called network-on-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC'02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution

Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models

Network-on-chip is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. A mismatch between the NoC channel width and the core test wrapper width can adversely affect test efficiency. In addition, stringent power constraints on today's high-density systems exacerbate the test scheduling problem. In this paper, we propose a method for efficiently utilizing the on-chip network for power-aware test scheduling in NoCs. We make use of on-chip clocking to speed up test data transfer by selectively using faster clocks to test certain cores; other cores receive slower clocks to limit test power consumption. A method is presented to determine the clock rate distribution among cores. Experimental results for the ITC '02 benchmarks show that the new method leads to substantial reduction in overall test application time, while satisfying power constraints.

Network-on-a-chip (NoC) is becoming a promising paradigm of core-based system. We propose a new method for test scheduling in NoC. The method is based on the use of a dedicated routing path for the test of each core. We show that test scheduling under this approach is NP-complete and present an ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an efficient heuristic. We then improve the heuristic by including BISTs and precedence constraints. Experimental results for the ITC'02 SoC benchmarks show that the new method leads to substantial reduction on test application time compared to previous work. The inclusion of BIST tests and precedence constraints provides a comprehensive solution for test scheduling in NoC.

Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results for the ITC'02 SOC Test Benchmarks show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously proposed technique for the reuse of an on-chip network is extended to consider power consumption during test, while minimizing the system testing time. Experimental results with the ITC'02 SoC benchmarks show that although power constraints can preclude the full exploration of the network parallelism, this platform is still a powerful mechanism for the system test time reduction at a very low cost.

The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.

This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the consideration of different optimization factors (area, ping and test time) during the global TAM and test schedule definition. This expansion of concerns makes possible an efficient yet fine-grained search in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test design.

This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.

The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8/sup th/ order analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

This work presents a new diagnosis method for use in an adaptive analog tester. The tester is able to detect faults in any linear circuit by learning a reference behaviour in a first step, and comparing this behaviour against the output of the circuit under test in a second step. Considering the same basic structure, the diagnosis method consists on injecting probable faults in a mathematical model of the circuit and later comparing its output with the output of the real faulty circuit. This method has been successfully applied to a case study, a biquad filter. Component soft, large, and hard deviations, and faults in operational amplifiers were considered. The results obtained from practical experiments with this analog circuit are discussed in the paper.

As next generation chips embedding MEMS appear, fault-based and defect-oriented tests for MEMS parts become important for cost-effective production testing. This paper presents realistic fault modeling and simulation techniques for suspended thermal MEMS, an already successful domain of application.

In this work a Computer-Aided Testing (CAT) tool is proposed that brings a systematic way of dealing with testing problems in emerging microsystems. Experiments with case-studies illustrate the techniques and tools embedded in the CAT environment. Some of the open problems that shall be addressed in the near future as an extension to this work are also discussed.