The integration of cellular networks and unmanned aerial vehicle (UAV) swarm communications is expected to be a promising technology to provide ubiquitous network connectivity for various UAV assisted Internet of Things (IoT) applications. To support these IoT applications with stringent requirement of rate performance, this paper explores the maximum sum rate performance for the cellular-connected UAV swarm communications. The sum rate maximization can be formulated as a nonlinear and nonconvex optimization problem with the constraints of transmit power of UAVs, elevation angle, azimuth angle and height of antenna array equipped at base station (BS). According to the Karush–Kuhn–Tucker (KKT) optimality conditions and the standard interference function, we propose an iterative algorithm to solve the problem, wherein the problem is transformed into a concave optimization problem by utilizing the rate approximation and logarithmic transformations. The iterative algorithm is proved to converge to a global solution for the approximated concave optimization problem. Finally, simulation results are provided to indicate the effect of some important system parameters on the sum rate performance in the system.

Feature selection has been playing an important role in analyzing the high-dimension and low-sample-size gene expression profiles towards high classification performance of diseases and deep understanding of the underlying biological mechanisms. Besides classification performance, the stability of selected features is another non-ignorable factor in evaluating a feature selector, since stable feature selection results enhance the confidence of selected features for true biomarker discovery and further biological validation. In this study, we propose a novel feature selection method under the ensemble learning framework. Specifically, we take Fast Correlation Based Filter as the base feature selector to analyze subsamples of microarray data. We then present several aggregation methods to combine multiple feature subsets. Finally, two stability measures are used to quantify the robustness of feature selectors to data variations. Our comparative empirical study on publicly available datasets demonstrates the superiority of the proposed methods over its competitors in obtaining high stability scores and classification accuracy.

Behavior identification plays an important role in supporting homecare for the elderly living alone. In literature, plenty of algorithms have been designed to identify behaviors of the elderly by learning features or extracting patterns from sensor data. However, most of them adopted probabilistic models or supervised learning to identify behaviors based on labeled sensor data. This paper proposes a behavior identification algorithm (BIA) using unsupervised learning based on unlabeled sensor data for the elderly living alone in smart home. This paper presents the observation of elder behaviors with three features: Event Order, Time Length Similarity and Time Interval Similarity features. Based on these features of behavior observations, two properties of behaviors, including the Event Shift and Histogram Shape Similarity properties, are presented. According to these properties, the proposed BIA is developed. Finally, performance results show that the proposed BIA outperforms the existing unsupervised machine learning mechanisms in terms of the behavior identification precision and recall.

The irregularity detection of daily behaviors for the elderly is an important issue in homecare. Plenty of mechanisms have been developed to detect the health condition of the elderly based on the explicit irregularity of several biomedical parameters or some specific behaviors. However, few research works focus on detecting the implicit irregularity involving the combination of diverse behaviors, which can assess the cognitive and physical wellbeing of elders but cannot be directly identified based on sensor data. This paper proposes an Implicit IRregularity Detection (IIRD) mechanism that aims to detect the implicit irregularity by developing the unsupervised learning algorithm based on daily behaviors. The proposed IIRD mechanism identifies the distance and similarity between daily behaviors, which are important features to distinguish the regular and irregular daily behaviors and detect the implicit irregularity of elderly health condition. Performance results show that the proposed IIRD outperforms the existing unsupervised machine-learning mechanisms in terms of the detection accuracy and irregularity recall.

In indoor environment, passive human detection and localisation are important enabling technologies for elder healthcare, emergence rescue and target tracking applications. Recently, the fine‐grained channel state information (CSI) of Wi‐Fi was adopted for indoor localisation due to the low‐cost Wi‐Fi network interface card and available firmware modifications for CSI extraction. However, due to multipath fading and spatial‐temporal dynamics of wireless channel, stable CSI extraction is a challenging task to achieve reliable CSI fingerprint matching. In this study, the sensitivity of CSI is first analysed and stable CSI fingerprints can be obtained by reducing the variance from interference and white noise. The stable CSI fingerprints are then classified by quadratic discriminant analysis to achieve location matching. Extensive experiments have been conducted to justify the system performance. The results reveal that the proposed indoor passive localisation system outperforms passive CSI‐MIMO system in terms of performance.

Barrier coverage has received much attention in the last decade and has been an import issue in wireless sensor networks. In the previous study, a number of researchers have presented algorithms for coping with the barrier coverage problem. However, these studies consider that sensors are equipped with batteries and the sensing model applies Boolean Sensing Model (BSM). The sensor using battery as its energy source can lead to the battery change problem which is difficult and inconvenient. Unlike previous studies, this work aims to resolve the barrier coverage problem but considers solar-powered sensors and applies the Probabilistic Sensing Model (PSM). A barrier coverage mechanism, called MSQ (Maximizing surveillance quality algorithm), is proposed aiming to maximize boundary surveillance quality. Performance experiments show that the proposed MSQ mechanism outperforms existing studies in terms of surveillance quality.

Radio frequency based device-free passive localization has been actively studied. An important issue with this technique is that a large amount of sensor nodes are usually deployed in localization environments, causing high deployment cost, high computation complexity and other drawbacks. To reduce the number of nodes while maintaining high localization accuracy, this paper proposes a fingerprint-based node deployment mechanism, which saves hardware cost, speeds up node deployment process as well as maintains a similar accuracy. The experiments are conducted in two environments with considerably different sizes of 150 m2and 25 m2. Maintaining the accuracies above 95%, the proposed mechanism can efficiently reduce the total number of nodes in large room by 54.55% and in small room by 68.75%. Especially, the localization response time sharply reduces by 93.08% in the large room and 79.87% in the small room.

Target coverage problems have received much attention in recent years. In a large monitoring environment where targets are distributed over an entire monitored region, deploying static sensors leads to high hardware costs because a high number of sensors may be required to achieve network connectivity. This paper considers the target-patrol issue where a set of mobile data mules (DMs) are dispatched to efficiently patrol the given targets under a predefined time constraint. The targets are assigned weights indicating their importance, where more important targets should be visited more frequently by the DMs. Accordingly, this paper proposes a time-constrained weighted targets patrolling (TCWTP) algorithm for locally constructing efficient patrol paths, thereby ensuring globally stable intervals between visits to all target points. A performance analysis revealed that the proposed TCWTP mechanism outperforms existing works in terms of the average interval between visits, quality of monitoring satisfaction ratio, and monitoring fairness ratio.

Wrapper based gene selection methods tend to obtain better classification accuracy than filter methods, while it is much more time consuming. Accelerating this process without degrading the high accuracy is of great value for researchers to better analyze gene expression profiles. In this paper, we explore to reduce the time complexity of wrapper based gene selection method with K-Nearest-Neighbor (KNN) classifier embedded. Instead of taking KNN as a black box, we incrementally construct and maintain a classifier distance matrix to speed up the gene selection process. Experiments on six publicly available microarrays were first conducted to show the effectiveness of incremental wrapper based gene selection method with KNN. Then, to demonstrate the performance gain in time cost reduction, we analyzed the time complexity and experimentally evaluated it. Both theoretical analysis and experimental results prove that the proposed approach greatly accelerates the gene selection process without degrading the classification accuracy.

Gene selection plays a crucial role in the analysis of microarray data with high dimensionality and small sample size. Incremental wrapper based feature subset selection (FSS) methods, among various feature selection approaches, tend to obtain high quality feature subset and better classification accuracy than filter methods, while it is much more time consuming since the interdependence and redundancy between features is evaluated in a wrapper way. In this paper, we explore to introduce Markov Blanket (MB) into incremental wrapper based FSS process. Rather than evaluate the quality of all the features ranked by a filter method, our proposal eliminates features that are redundant to the newly selected one via MB during the wrapper evaluation process to reduce the number of wrappers, enabling us to select the relevant features and eliminate redundant ones efficiently. To verify the effectiveness and efficiency of the proposed approach, experimental comparisons on six publicly available microarray data are conducted with two typical classifiers with different metrics, Naïve Bayes and 1-Nearest-Neighbor. Experimental results demonstrate that our approach greatly speeds up the feature selection process, obtains more compact feature subset and achieves better classification accuracy compared to that without MB for both two-category and multi-category problems.

We conducted a survey indicating the wide variety of computer literacy and computer skills among college students. Most teachers suggest that new teaching strategies should be deployed. To resolve these issues, we propose a strategy for improving learning performance in the Introduction to Computers class based on the concepts of crowdsourcing and flipped classroom. The design strategy attempts to resolve common issues in training teachers, designing teaching activities, and sharing knowledge and teaching experiences simultaneously. To accomplish the above goals, we make use of a crowdsourcing system which serves multiple purposes including (1) the innovation of teaching ideas; (2) the enhancement of instructor engagement and training process; and (3) the improvement of sharing knowledge and teaching experiences. To verify the proposed approach, an experiment involving over 10,000 students will be conducted.

One of the critical goals in code optimization for multi-processor-system-on-a-chip (MPSoC) architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles. While conventional data locality optimization techniques can be used for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the on-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block. In order to test the effectiveness of our approach, we implemented it using a publicly-available compiler infrastructure and conducted experiments with twelve data-intensive embedded applications. Our results show that optimizing data locality for shared data elements is very useful in practice.

In this paper, we present a novel method to render colorful 3D fractals based on so-called color-control sphere (CSS) and our improved escape-time algorithm. In the method, each point, called parameter point, in parameter domain is first judged whether it is an escape-point or not by an iteration loop, under the governing of a discrete dynamic system. Once the iteration loop is exited, an orbiting point corresponding to the parameter point is then mapped to a mapped-point in CCS and the distance from the mapped-point to the center of CCS is evaluated. Subsequently, a color for rendering the parameter point can be obtained by employing a predefined color-control function in CCS with respect to the distance. Finally, all surface points, which are taken as a set of initial points of the discrete dynamic system, of arbitrary shape embedded in the parameter domain are rendered with their corresponding colors. As a result, a pseudo-3D fractal can be archived on the 3D surface.

This paper proposes and experimentally evaluates a compiler-driven approach that operates an on-chip scratch-pad memory (SPM) assuming different latencies for the different SPM lines. Our goal is to reduce execution cycles without creating any reliability problems due to variations in access latencies. The proposed scheme achieves its goal by evaluating the reuse of different data items and adopting a reuse and latency aware data-to-SPM placement. It also employs data migration within SPM when it helps to cut down the number of execution cycles further. We also discuss an alternate scheme that can reduce latency of select SPM locations by controlling a circuit level mechanism in software to further improve performance. We implemented our approach within an optimizing compiler and tested its effectiveness through extensive simulations. Our experiments with twelve embedded application codes show that the proposed approach performs much better than the worst-case based design paradigm (16.2% improvement on the average) and comes close (within 5.7%) to an hypothetical best-case design (i.e., one with no process variation) where every SMP locations uniformly have low latency

Compilers designed for current embedded systems must be capable of addressing multiple constraints such as low power, high performance, small memory footprint and form factor, and high reliability at the same time. In particular, optimizing for one constraint should be performed carefully, considering its impact on other constraints. Recent trends indicate that transient errors are becoming increasingly important in embedded systems. Focusing on an embedded chip multiprocessor and array-intensive applications, this paper demonstrates how reliability against transient errors can be improved without impacting execution time by utilizing idle processors for duplicating some of the computations of the active processors. It also shows how a balance between power savings and reliability improvement can be struck using a metric called the energy-delay-fallibility product. Our experimental results indicate that the "percentage of duplicated computations" is a useful high-level metric for studying the tradeoffs among performance, power, and reliability

Soft errors are becoming a common problem in current systems due to the scaling of technology that results in the use of smaller devices, lower voltages, and power-saving techniques. In this work, we focus on soft errors that can occur in the objects created in heap memory, and investigate techniques for enhancing the immunity to soft errors through various object duplication schemes. The idea is to access the duplicate object when the checksum associated with the primary object indicates an error. We implemented several duplication based schemes and conducted extensive experiments. Our results clearly show that this spectrum of schemes enable us to balance the tradeoffs between error rate and heap space consumption.

Increasing employment of chip multiprocessors in embedded computing platforms requires a fresh look at conventional code parallelization schemes. In particular, any compiler-based parallelization scheme for chip multiprocessors should account for the fact that interprocessor communication is cheaper than off-chip memory accesses in these architectures. Based on this observation, this paper proposes a constraint network based approach to code parallelization for chip multiprocessors. Constraint networks have proven to be a useful mechanism for modeling and solving computationally intensive tasks in artificial intelligence. They operate by expressing a problem as a set of variables, variable domains and constraints and define a search procedure that tries to satisfy the constraints (an acceptable subset of them) by assigning values to variables from their specified domains. This paper demonstrates that it is possible to use a constraint network based formulation for the problem of code parallelization for chip multiprocessors. Our experimental evaluation shows that not only a constraint network based approach is feasible for our problem but also highly desirable since it outperforms all other parallelization schemes tested in our experiments.

There exist many embedded applications such as those executing on set-top boxes, wireless base stations, HDTV, and mobile handsets that are structured as nested loops and benefit significantly from software managed memory. Prior work on scratchpad memories (SPMs) focused primarily on applications with regular data access patterns. Unfortunately, some embedded applications do not fit in this category and consequently conventional SPM management schemes will fail to produce the best results for them. In this work, we propose a novel compilation strategy for data SPMs for embedded applications that exhibit irregular data access patterns. Our scheme divides the task of optimization between compiler and runtime. The compiler processes each loop nest and inserts code to collect information at runtime. Then, the code is modified in such a fashion that, depending on the collected information, it dynamically chooses to use or not to use the data SPM for a given set of accesses to irregular arrays. Our results indicate that this approach is very successful with the applications that have irregular patterns and improves their execution cycles by about 54% over a state-of-the-art SPM management technique and 23% over the conventional cache memories. Also, the additional code size overhead incurred by our approach is less than 5% for all the applications tested

Reducing power consumption is quickly becoming a first-class optimization metric for many high-performance parallel computing platforms. One of the techniques employed by many prior proposals along this direction is voltage scaling and past research used it on different components such as networks, CPUs, and memories. In contrast to most of the existent efforts on voltage scaling that target a single component (CPU, network or memory components), this paper proposes and experimentally evaluates a voltage/frequency scaling algorithm that considers CPU and communication links in a mesh network at the same time. More specifically, it scales voltages/frequencies of both CPUs in the network and the communication links among them in a coordinated fashion (instead of one after another) such that energy savings are maximized without impacting execution time. Our experiments with several tree-based sparse matrix computations reveal that the proposed integrated voltage scaling approach is very effective in practice and brings 13% and 17% energy savings over the pure CPU and pure communication link voltage scaling schemes, respectively. The results also show that our savings are consistent with the different network sizes and different sets of voltage/frequency levels.

In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance, since studies of programs have shown that instructions that manipulate address registers constitute a significant portion of the overall instruction count (up to 55%). This work presents a compiler-based optimization strategy to “reduce the code size in embedded systems.” Our strategy maximizes the use of indirect addressing modes with postincrement/decrement capabilities available in DSP processors. These modes can be exploited by ensuring that successive references to variables access consecutive memory locations. To achieve this spatial locality, our approach uses both access pattern modification (program code restructuring) and memory storage reordering (data layout restructuring). Experimental results on a set of benchmark codes show the effectiveness of our solution and indicate that our approach outperforms the previous approaches to the problem. In addition to resulting in significant reductions in instruction memory (storage) requirements, the proposed technique improves execution time.

While lots of prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This is unfortunate since in general the performance-oriented techniques influence energy behavior of the cache, and the energy-oriented techniques usually increase program execution cycles. The overall energy and performance behavior of caches in embedded systems when multiple techniques co-exist remains an open research problem. This paper studies this interaction and illustrates how performance and energy optimizations affect each other. We also point out several potential optimizations that could be based on this study.

The application code size is a critical design factor for many embedded systems. Unfortunately, most available compilers optimize primarily for speed of execution rather than code density. As a result, the compiler-generated code can be much larger than necessary. In particular, in the DSP domain, the past research found that optimizing address code generation can be very important since address code can account for over 50% of all program bits. This paper presents a compiler-directed scheme to minimize the number of instructions to be generated to manipulate address registers found in DSP architectures. As opposed to most of the prior techniques that attempt to reduce the number of such instructions through careful address register assignment, this paper proposes modifying loop access patterns in array-intensive signal processing applications. In addition, it demonstrates how the proposed scheme can cooperate with a data layout optimizer for increasing its benefits further. We also discuss how optimizations that target effective address code generation can conflict with data locality-enhancing transformations. We evaluate the proposed approach using twelve array-intensive embedded applications. Our experimental results indicate that the proposed approach not only leads to significant reductions in code size but also outperforms prior efforts on reducing code size of array-intensive DSP applications.

While loop restructuring based code optimization for array intensive applications has been successful in the past, it has several problems such as the requirement of checking dependences (legality issues) and transformation of all of the array references within the loop body indiscriminately (while some of the references can benefit from the transformation, others may not). As a result, data transformations, i.e., transformations that modify memory layout of array data instead of loop structure have been proposed. One of the problems associated with data transformations is the difficulty of selecting a memory layout for an array that is acceptable to the entire program (not just to a single loop). In this paper, we formulate the problem of determining the memory layouts of arrays as a constraint network, and explore several methods of solution in a systematic way. Our experiments provide strong support in favor of employing constraint processing, and point out future research directions.

Utilizing on-chip caches in embedded multiprocessor-system-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at hardware and compilation levels, operating system (OS) can also play major role as it sees the global access pattern information across applications. This paper proposes a cache-conscious OS process scheduling strategy based on data reuse. The proposed scheduler implements two complementary approaches. First, the processes that do not share any data between them are scheduled at different cores if it is possible to do so. Second, the processes that could not be executed at the same time (due to dependences) but share data among each other are mapped to the same processor core so that they share the cache contents. Our experimental results using this new data locality aware OS scheduling strategy are promising, and show significant improvements in task completion times.

Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we witness an unprecedented proliferation of embedded/mobile applications. Most of the environments that execute these applications have severe power, performance, and memory space constraints that need to be accounted for. In particular, memory limitations can present serious challenges to embedded software designers. The current solutions to this problem include sophisticated packaging techniques and code optimizations for effective memory utilization. While the first solution is not scalable, the second one is restricted by intrinsic data dependences in the code that prevent code restructuring. In this paper, we explore an alternate approach for reducing memory space requirements of embedded applications. The idea is to re-compute the result of a code block (potentially multiple times) instead of storing it in memory and performing a memory operation whenever needed. The main benefit of this approach is that it reduces memory space requirements, that is, no memory space is reserved for storing the result of the code block in question.

Soft errors are transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive components. While many systems implement hardware-based protection techniques like ECC and other approaches to ensure an acceptable level of robustness against these errors, such solutions are generally very rigid and costly. Recent research discussed checksum-based software solutions that can be used in the context of array-intensive computations. While a checksum-based scheme can be more flexible than a hardware-based approach to reliability, it can also bring significant runtime overheads. Focusing on array-intensive applications, this paper proposes a compiler-directed data-centric strategy that maximizes reuse of checksums. A unique characteristic of the proposed scheme is that it can work with a given checksum assignment, and automatically - under compiler guidance - restructures the entire application code to maximize checksum reuse. This scheme can reduce checksum recomputing even further by inter-procedural checksum reuse. Our experiments clearly show that the proposed approach reduces the number of checksum calculations required by the previous work.

Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. The advantage of placing multiple cores into a single die is that it reduces on-chip communication costs (in terms of both execution cycles and power consumption) between the processor cores that are traditionally very high in conventional high-performance parallel architectures (such as SMPs). However, on the negative side, this tighter integration exerts an even higher pressure on off-chip accesses to the memory system. This makes minimizing the number of off-chip accesses a critical optimization goal.This paper discusses a compiler-based solution to this problem for the embedded applications that perform stencil computations. An important characteristic of this solution is that it distinguishes between the intra-processor data reuse and inter-processor data reuse. The first of these captures the data reuse that occurs across loop iterations assigned to the same processor, whereas the second one represents the data reuse that takes place across the loop iterations assigned to different processors. The proposed approach then optimizes inter-processor reuse by re-organizing the loop iterations of each processor carefully, considering how data elements are shared across processors. The goal is to ensure that the different processors access the shared data within a short period of time, so that the data can be captured in the on-chip memory space at the time of the reuse. This paper also presents an evaluation of the proposed optimization and compares it to an alternate scheme that optimizes data locality for each processor in isolation. The results obtained by applying our implementation to eight loop-intensive benchmark codes from the embedded computing domain show that our approach improves over the mentioned alternate scheme by 15.6% on average.

Network power optimization is becoming increasingly important as the sizes of the data manipulated by parallel applications and the complexity of inter-processor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows that these schemes can be effective in certain cases, they share the common drawback of not being able to predict the link active and idle times very accurately. This paper, instead, proposes a compiler-based scheme that determines the last use of communication links at each loop nest and inserts explicit link turn-off calls in the application source. Specifically, for each loop nest, the compiler inserts a turn-off call per communication link. Each turned-off link is reactivated upon the next access to it. We automated this approach within a parallelizing compiler and applied it to eight array-intensive embedded applications.

One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely costly from both performance and power angles. While conventional data locality optimization techniques can be used for improving data access pattern of each processor independently, such techniques usually do not consider locality for shared data. This paper proposes a strategy that reduces the number of off-chip references due to shared data. It achieves this goal by restructuring a parallelized application code in such a fashion that a given data block is accessed by parallel processors within the same time frame, so that its reuse is maximized while it is in the on-chip memory space. This tends to minimize the number of off-chip references since the accesses to a given data block are clustered within a short period of time during execution. Our approach employs a polyhedral tool that helps us isolate computations that manipulate a given data block.

Ensuring integrity of heap resident data is critical for many embedded systems. Ever-scaling process technology combined with power-saving techniques employed in embedded systems is increasing vulnerability of such systems to hardware-related errors such as soft errors. While such errors are transient and do not harm the architecture, they can corrupt data. In this study, we explore solutions to the inter-object connectivity problem in heap memory of Java-based embedded environments. Our objective is to ensure that the connections between the objects are consistent. In particular, we want to detect the cases where an inter-object link disappears or points to a wrong object. To address this problem, we propose a rule based approach, where the application programmer expresses the important connectivity rules to be satisfied using a special rule language, and a modified JVM (Java virtual machine) checks these rules at runtime.

In the context of data-intensive embedded applications, there have been two complementary approaches to data locality problem: restructuring code and restructuring data layout. Conceivably, an integrated approach that combines these two can generate much better results than each individual approach. However, there is an inherent difficulty in optimizing both data layout and loop access pattern simultaneously under a unified setting. This difficulty occurs due to the fact that a given data structure can be accessed by different loop nests of the application, and each such loop nest can demand a different memory layout transformation for the said data structure. This results in a coupling problem, where the behaviors of two (or more) loop nests are coupled to each other as a result of data sharing between them. In this paper, we present a constraint network (CN) based formulation of the integrated loop-data optimization problem. We present two alternate solutions to the data locality problem with our CN based formulation and discuss the pros and cons of each scheme. The first solution is a pure backtracking based one, whereas the second one improves upon the first one by employing three additional optimizations, including backjumping.

Reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. Most of the prior efforts on network power optimization are hardware-based schemes. These schemes are predictive by definition as they control communication link status based on the observations made In the past. Since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. This paper proposes a compiler driven approach to communication link voltage management. In this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. This information along with network topology is used for identifying the link access patterns. These patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. Our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. We exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which In turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.

Recent trends in embedded computing indicates an increasing use of scratch-pad memories (SPMs) as on-chip store for instructions and data. An important characteristic of these memory components is that they are managed by software, instead of hardware. Ever-scaling process technology and employment of several power-saving techniques in embedded systems (e.g., voltage scaling) make these systems particularly vulnerable to soft errors and other transient errors. Therefore, it is very important in practice to consider the impact of soft errors in SPMs. While it is possible to employ classical memory protection mechanisms such as parity checks and ECC, each of these has its drawbacks. Specifically, a pure parity-based protection cannot correct any errors, and ECCs can be an overkill in the normal operation state when no soft error is experienced. This paper proposes an alternate approach to protect SPMs against soft errors. The proposed approach is based on data block duplication under compiler control. More specifically, an optimizing compiler duplicates data blocks within the SPM and protects each data block by parity if such a duplication does not hurt performance. The goal of this scheme is to provide only parity protection for data blocks (and reduce the overheads at runtime when no error occurs) but correct errors using the duplicate (when an error occurs in the primary copy), provided that the duplicate is not corrupted.

In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9/spl deg/C (4.3/spl deg/C) when averaged over all the applications tested, incurring small performance/power penalties.

A critical component of a real-time operating system (RTOS) is its process scheduler. While the prior research on process scheduling focuses mostly on meeting hard/soft deadlines, preemption and priory assignment related issues, problems arise from existence of cache memories are largely ignored. Focusing on data accesses and a cache based embedded system, this paper proposes an adaptive locality-conscious process scheduling algorithm. The main goal of the proposed algorithm is to exploit (reuse) the contents of the on-chip cache memory to the highest extent possible. The algorithm tries to achieve its goal by determining the order in which the processes get scheduled such that the successively-executing processes share a large number of data elements. We implemented our scheduler within a customized simulation platform and simulated it using a set of benchmark codes. Our experimental results reveal that the proposed scheduling algorithm is very successful in practice, and reduces process completion times significantly for both rate-monotonic scheduling (RMS) and earliest-deadline-first scheduling (EDF). We also explain how process code transformations can be used for increasing the savings achieved by the locality-conscious scheduler, and show how the proposed approach operates with a base scheduler such as RMS and EDF.

The demand for high-performance architectures and powerful battery-operated mobile devices has accentuated the need for power optimization. While many power-oriented hardware optimization techniques have been proposed and incorporated in current systems, the increasingly critical power constraints have made it essential to look for software-level optimizations as well. The compiler can play a pivotal role in addressing the power constraints of a system as it wields a significant influence on the application's runtime behavior. This paper presents a novel Energy-Aware Compilation (EAC) framework that estimates and optimizes energy consumption of a given code, taking as input the architectural and technological parameters, energy models, and energy/performance/code size constraints. The framework has been validated using a cycle-accurate architectural-level energy simulator and found to be within 6% error margin while providing significant estimation speedup. The estimation speed of EAC is the key to the number of optimization alternatives that can be explored within a reasonable compilation time. As shown in this paper, EAC allows compiler writers and system designers to investigate power-performance tradeoffs of traditional compiler optimizations and to develop energy-conscious high-level code transformations.

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a set of code optimization strategies. We first evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using a different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67 percent energy savings at the expense of up to 17 percent performance loss in a set of array-intensive applications. To eliminate this performance penalty, we also discuss and evaluate a processor preactivation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut down and preactivation can be very effective in reducing energy consumption without increasing execution time. We then generalize our strategy and present an application parallelization strategy based on integer linear programming (ILP). Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each loop nest based on the objective function and additional compilation constraints provided by the user/programmer. Our initial experience with this constraint-based optimization strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under multiple energy and performance constraints.

Reconfigurable computing has become an important part of research in software systems and computer architecture. While prior research on reconfigurable computing have addressed architectural and compilation/programming aspects to some extent, there is still not much consensus on what kind of operating system (OS) support should be provided. In this paper, we focus on OS process scheduler, and demonstrate how it can be customized considering the needs of reconfigurable hardware. Our process scheduler is configuration sensitive, that is, it reuses the current FPGA configuration as much as possible. Our extensive experimental results show that the proposed scheduler is superior to classical scheduling algorithms such first-come-first-serve (FCFS) and shortest job first (SJF).

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. We propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.

This paper presents two letter-to-sound (LTS) methods in building a small-footprint multilingual text-to-speech (TTS) engine. For the languages where there exist a systematic relationship between a word format and its pronunciation, we employ a rule-based method. Otherwise, we use a trainingbased method. In the second method, we adopted optimal sequence to implement the process of letter-to-phoneme alignment, and use CART to train the decision tree and store the results in an efficient way. Despite their merits and disadvantages, the experimental results on six languages demonstrate these methods are effective to reach an acceptable LTS precision within a reasonable small size.

Bank locality can be defined as localizing the number of load/store accesses to a small set of memory banks at a given time. An optimizing compiler can modify a given input code to improve its bank locality. There are several practical advantages of enhancing bank locality, the most important of which is reduced memory energy consumption. Recent trends indicate that energy consumption is fast becoming a first-order design parameter as processor-based systems continue to become more complex and multi-functional. Off-chip memory energy consumption in particular can be a limiting factor in many embedded system designs. This paper presents a novel compiler-based strategy for maximizing the benefits of low-power operating modes available in some recent DRAM-based multi-bank memory systems. In this strategy, the compiler uses linear algebra to represent and optimize bank locality in a mathematical framework. We discuss that exploiting bank locality can be cast as loop (iteration space) and array layout (data space) transformations. We also present experimental data showing the effectiveness of our optimization strategy. Our results show that exploiting bank locality can result in large energy savings.

We present a compiler-oriented strategy to reduce the memory system energy consumption due to instruction accesses and increase performance by exploiting scratch pad memories. Scratch pad memories (SPMs) are alternatives to conventional cache memories in embedded computing. These small on-chip memories, like caches, provide fast and low-power access to data and instructions; but, they differ from caches in that their contents are managed by software instead of hardware. Our compiler framework keeps the most frequently used instructions in SPM and dynamically changes the contents of the SPM as the (instruction) working set of the application changes.