ABSTRACT Children often suffer wrist trauma in daily life and typically require radiologists to analyse and interpret X‐ray images before undergoing surgical treatment. The development of deep learning has enabled neural networks to serve as computer‐aided diagnosis (CAD) tools, assisting doctors and experts in medical image diagnostics. Since the you only look once version‐8 (YOLOv8) model has achieved satisfactory success in object detection tasks, it has been applied to various fracture detection tasks. This work introduces four variants of feature contexts excitation‐YOLOv8 (FCE‐YOLOv8) model, each incorporating a different FCE module (i.e., modules of squeeze‐and‐excitation (SE), global context (GC), gather‐excite (GE), and Gaussian context transformer (GCT)) to enhance the model performance. Experimental results on the GRAZPEDWRI‐DX dataset demonstrate that our proposed YOLOv8+GC‐M3 model improves the value from 65.78% to 66.32%, outperforming the state‐of‐the‐art (SOTA) model while reducing inference time. Furthermore, our proposed YOLOv8+SE‐M3 model achieves the highest value of 67.07%, exceeding the SOTA performance. The implementation of this work is publicly available at https://github.com/RuiyangJu/FCE‐YOLOv8 .

Memory requirements (for storing intermediate signals) and critical path are essential issues for 2-D (or multidimensional) transforms. This paper presents new algorithms and hardware architectures to address the above issues in 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the merits of low transpose memory (TM), low latency, and regular signal flow, making it suitable for very large-scale integration implementation. The TM requirement of theN×N2-D 5/3 mode LDWT and 2-D 9/7 mode LDWT are 2Nand 4N, respectively. Comparison results indicate that the proposed hardware architecture has a lower lifting-based low TM size requirement than the previous architectures. As a result, it can be applied to real-time visual operations such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding applications.

This work proposes a new Stereo Vision-Based Self-Localization System (SVBSLS) for the RoboCup soccer humanoid league rules for the 2010 competition. The humanoid robot integrates the information from the pan/tilt motors and stereo vision to accomplish the self-localization and measure the distance of the robot and the soccer ball. The proposed approach uses the trigonometric function to find the coarse distances from the robot to the landmark and the robot to the soccer ball, and then it further adopts the artificial neural network technique to increase the precision of the distance. The statistics approach is also used to calculate the relationship between the humanoid robot and the position of the landmark for self-localization. The experimental results indicate that the localization system of SVBSLS in this research work has 100% average accuracy ratio for localization. The average error of distance from the humanoid soccer robot to the soccer ball is only 0.64 cm.

This work presents a new approach, symmetric mask-based scheme (SMBS), for moving object detection and tracking based on the symmetric mask-based discrete wavelet transform (SMDWT). This work presents a fast algorithm, called 2D SMDWT, to improve the critical issue of the 2D lifting-based Discrete Wavelet Transform (LDWT), and then obtains the benefit of low latency, reduced complexity, and low transpose memory for object detection. The successful moving object detection in a real surrounding environment is a difficult task due to noise issues such as fake motion or Gaussian noise. The SMBS approach can effectively reduce noises with low computing cost in both indoor and outdoor environments. The experimental results indicate that the proposed method can provide precise moving object detection and tracking.

Conventionally a continuous time (CT) cascaded delta-sigma modulator is designed by virtue of the transforming from its equivalent discrete time (DT) cascaded delta-sigma modulator with compensation paths in the analog part. This work presents a new approach that does not need analog compensation paths when implementing a high order cascaded CT delta-sigma modulator. We move the compensation paths to the digital cancellation filters, and it leads to a more efficient architecture in terms of circuitry complexity, power consumption, area cost, and the robustness of circuit non-ideality. A 2-1-1 CT cascaded delta-sigma modulator for audio band application was designed and simulated; the dynamic range is 83.7 dB. The simulation results indicate that the performance of this delta-sigma modulator is competitive to the conventional approach with less hardware complexity and power dissipation.

In this work, we propose a high efficiency hardware architecture of embedded sub-band coding with optimal truncation (ESCOT) with word-level pass concurrent context modeling (Word-Level PCCM) scheme for wavelet-based scalable video coding (SVC). Word-Level PCCM can merge the three-pass process of bit-plane coding into a single pass process. It improves the efficiency of the ESCOT algorithm and reduces the memory requirement and the memory access frequency. Furthermore the parallel architecture scheme for Word-Level PCCM can encode 8 samples concurrently. We use the Artison TSMC 0.18 mum 1P6M standard cell library to design and implement the proposed Word-Level PCCM. The simulation results indicate that the Word-Level PCCM can operate for 1080p with frame rate of 60 fps at clock rate of 125 MHz.

This work presents a fast algorithm, namely 2-D Symmetric Mask-based Discrete Wavelet Transform (SMDWT), to address some critical issues of the 2-D Discrete Wavelet Transform (DWT). Unlike the traditional DWT involving dependent decompositions, the SMDWT itself is subband processing independent, which can significantly reduce complexity. Moreover, DWT cannot directly obtain target subbands, which leads to an extra wasting in transpose memory, critical path, and operation time. These problems can be fully improved with the proposed SMDWT. Nowadays, many applications employ DWT as the core transformation approach, the problems indicated above have motivated researchers to develop fast algorithms for DWT. The proposed SMDWT has been proved as a highly efficient independent processing to yield target subbands which can be applied to real-time visual applications, such as moving object detection and tracking, texture segmentation, image/video compression, and any DWT-based applications.

In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2-D DWT) for motion-JPEG2000. The proposed 2-D DWT architecture consists of a 1-D row processor, internal memory, and a 1-D column processor. The main advantage of this 2-D DWT is to reduce the internal memory requirement significantly. For an N×N image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2-D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2-D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.

Wavelet coding performs better than discrete cosine transform in visual processing. Moreover, it is scalable, which is important for modern video standards. The transpose memory requirement and operation speed are the two major concerns in 2-D lifting-based discrete wavelet transform (LDWT) implementation. This letter presents a novel algorithm, called 2-D symmetric mask-based discrete wavelet transform (SMDWT), to improve the critical issue of the 2-D LDWT, and then obtains the benefit of low-latency reduced complexity, and low transpose memory. The SMDWT also has the advantages of reduced complexity, regular signal coding, short critical path, reduced latency time, and independent subband coding processing. Furthermore, the 2-D LDWT performance can also be easily improved by exploiting an appropriate parallel method inherent to SMDWT. The proposed method has a significantly better lifting-based latency and complexity in 2-D DWT than normal 2-D 5/3 integer LDWT without degradation in image quality. The algorithm can be applied to real-time image/video applications.

The amount of memory required for code-block is one of the most important issues in JPEG2000 encoder chip implementation. This work tries to unify the output scanning order of the 2D-DWT and the processing order of the EBCOT and further to eliminate the code-block memory completely eliminated. We also propose a new architecture for embedded block coding (EBC), code-block switch adaptive embedded block coding (CS-AEBC), which can skip the insignificant bit-planes to reduce the computation time and save power consumption. Besides, a new dynamic rate distortion optimization (RDO) approach is proposed to reduce the computation time when the EBC processes lossy compression operation. The total memory required for the proposed JPEG2000 is only 2KB of internal memory, and the bandwidth required for the external memory is 2.1 B/cycle.

In this work, we propose a high efficiency hardware architecture of embedded sub-band coding with optimal truncation (ESCOT) with pass concurrent context modeling (PCCM) scheme for wavelet-based scalable video coding (SVC). PCCM can merge the three-pass process of bit-plane coding into a single pass process. It improves the efficiency of the ESCOT algorithm and reduces the frequencies of memory access, which can reduce the power consumption. Furthermore we use the parallel architecture scheme of PCCM to encode 4 samples concurrently, which improves the operation speed and can reduce 40% of internal memory requirement. We use Artison TSMC 0.18μm 1P6M standard cell library to design and implement the proposed concurrent context modeling. The simulation results indicate that PCCM can have an operation speedup of 9.5 compared to the standard context modeling of ESCOT, and it can operate for 1080p with frame rate of 30fps at clock rate of 125MHz.

Wavelet coding has been shown to be better than discrete cosine transform (DCT) in image/video processing. Moreover, it has the feature of scalability, which is involved in modern video standards. This work presents novel algorithms, namely 2-D symmetric mask-based discrete wavelet transform (SMDWT), to improve the critical issue of the 2-D lifting-based discrete wavelet transform (LDWT), and then obtains the benefit of low latency, high-speed operation, and low temporal memory. The SMDWT also has the advantages of high-performance embedded periodic extension boundary treatment, reduced complexity, regular signal coding, short critical path, reduced latency time, and independent subband coding processing. Moreover, the 2-D lifting-based DWT performance can also be easily improved by exploiting appropriate parallel method inherently in SMDWT. Comparing with the normal 2-D 5/3 integer lifting-based DWT the proposed method significantly improves lifting-based latency and complexity in 2-D DWT without degradation in image quality. The algorithm can be applied to real-time image/video applications, such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based Scalable Video Coding (SVC).

This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%.

In this paper, a 20-Msample/sec and 12-bit resolution sigma delta modulator for 802.11a applications is presented. The distributed feedback with a forward input and resonator feedback schemes are utilized to implement this modulator. The fifth-order 3-bit quantizer single-loop sigma delta modulator achieves 20-MS/s conversion ratio with 74dB of dynamic range and 70dB of peak signal-to-noise-distortion ratio. The circuit is implemented in a standard 0.18 /spl mu/m 1P6M CMOS technology. The core area is 0.77mm/sup 2/ (1.1 mm /spl times/ 0.7mm) and the power consumption is only 38-mW at 1.8-V supply.

Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By valid-bit pre-decision, it significantly helps in improving the average energy saving of the conventional way-predicting cache without valid-bit pre-decision, especially for with large associativity and small sub-block size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.

Wireless communication that provides voice only is not sufficient to support the necessity of user. It is an important feature of future wireless communication to offer this capability through mobile Internet. Mobile IP allows mobile hosts to change their location and reduce the losing probability of data packets in wireless communication networks. However, Mobile IP still have some defects in handoff and route aspects. Therefore, Cellular IP protocol is proposed for routing of IP diagrams to mobile stations and fast handoff control in a limited geographical area. In this paper, a handoff method is proposed to improve Quality of Service and resource switching management to reduce data packet loss for mobile multimedia communication in hierarchical network. In the future, all-IP network and mobile multimedia communication are two important characteristics, so that IP macromobility and micromobility network architecture are combined for data packets transfer. A Soft-handoff method is also presented to improve Quality of Service (QoS) and resource switching management to reduce data packet loss.

Due to the popularity of broadband network and World Wide Web, network service advances more completely. In spite of lots of network companies suffer deficits, E-Commerce still attracts numerous enterprises to invest in. But consumers have no confidence for electronic transaction, the main reason is security problem. They fret about the data would be stolen, or their accounts would be usurped. Thus the most influential facility is security model. And in the security model, the basic model is authentication. If there is no sturdy authentication, anyone can masquerade others' identities. The major objective of this paper is to propose an agent-based E-Commerce environment and to set up a secure E-marketplace authentication mechanism.

Progressive image transmission is a mechanism that transmits the most significant portion of an image, followed by its less important parts. Applications of such a mechanism include browsing large image files on the Internet. We propose an adaptive mechanism, based on the characteristics of images. The mechanism use neighbor pixels to guess a target pixel value, without actually transmitting the target pixel. An error correction scheme is also designed to cope with a failure guessing. The prototype is tested on 1500 bit-mapped pictures of different categories. Preliminary results should that the transmission rate is lower than others, with reasonable PSNR values of the transmitted images. Interested readers can find the prototype tool and our evaluations at http://www.mine.tku.edu.tw/demos/ProgTransmission.

An experimental low-voltage low-power pipelined analog-to-digital converter is designed and presented in this paper. The power consumption is efficiently reduced by using switched operational amplifiers and dynamic comparators. This chip is designed in a 0.35 /spl mu/m CMOS process. The core area occupies 1450 /spl mu/m/spl times/1100 /spl mu/m. The HSPICE simulation results show that the resolution of this design is 10-bit; the sampling rate is 10 MHz; the peak SNDR is 66 dB, and the power consumption is 15 mW at 1.5 V supply voltage.

A novel general algorithm for signed number division in the residue number system (RNS) is presented. The parity checking technique used for sign and overflow detection in this algorithm is more efficient and practical than conventional methods. Sign magnitude arithmetic division is implemented using binary search. There is no restriction to the dividend and the divisor (except zero divisor), and no quotient estimation is necessary before the division is executed. Only simple operations are needed to accomplish this RBS division. All these characteristics have made the algorithm simple, efficient, and practical for implementation on a real RNS divider.>

A general algorithm for signed number division in residue number systems (RNSs) is presented. A parity checking technique is used to accomplish the sign and overflow detection in this algorithm. Compared with conventional methods of sign and overflow detection, the parity checking method is more efficient and practical. Sign magnitude arithmetic division is implemented using binary search. There is no restriction on the dividend and the divisor (except zero divisor), and no quotient estimation is necessary before the division is started. In hardware implementations, the storage of one table is required for parity checking, and all the other arithmetic operations are completed by calculations. Only simple operations are needed to accomplish this RNS division.>