This study develops a physics-informed neural network (PINN) framework to predict droplet spreading dynamics on unstructured rough surfaces. The trained model effectively captures temporal evolution of the droplet shape, contact line motion, and interfacial deformation. This integration of multiphase physics with neural networks provides a mesh-free and computationally efficient alternative to numerical solvers, enabling rapid analysis and design of wettability-controlled surfaces, microfluidic devices.

Adversarial attacks rely on transferability, where an adversarial example (AE) crafted on a surrogate classifier tends to mislead a target classifier. Recent ensemble methods demonstrate that AEs are less likely to mislead multiple classifiers in an ensemble. This paper proposes a new ensemble training using a Pairwise Adversarially Robust Loss (PARL) that by construction produces an ensemble of classifiers with diverse decision boundaries. PARL utilizes outputs and gradients of each layer with respect to network parameters in every classifier within the ensemble simultaneously. PARL is demonstrated to achieve higher robustness against black-box transfer attacks than previous ensemble methods as well as adversarial training without adversely affecting clean example accuracy. Extensive experiments using standard Resnet20, WideResnet28-10 classifiers demonstrate the robustness of PARL against state-of-the-art adversarial attacks. While maintaining similar clean accuracy and lesser training time, the proposed architecture has a 24.8% increase in robust accuracy (∊= 0.07) from the state-of-the art method. Code is available at: https://github.com/shubhishukla10/PARL

Rapid aiming movement involves quick, accurate, pre-programmed motions used in the context of human-computer and human-robot interaction. It incorporates target forecasting to minimize the duration of tasks requiring rapid aiming. Applications include predicting target icons in UI design, driver intent in automotive technology, and human intent during human-robot collaboration. Conventional approaches often fail to capture human preferences accurately, leading to low prediction accuracy. This work explores an Inverse Reinforcement Learning (IRL)-based system for forecasting human hand movements and intended targets during rapid aiming. Sampling-based Maximum Entropy IRL (SMEIRL) with a sampler and Maximum Entropy Deep IRL (MEDIRL) algorithms were evaluated for prediction accuracy. The proposed sampler efficiently generates sample trajectories for rapid aiming tasks. User studies were conducted to assess target prediction during two tasks involving rapid aiming movement: (1) Pointing in Virtual Reality (VR) and Mixed Reality (MR), and (2) Human-robot handovers. A multimodal target prediction algorithm was analyzed for swift and accurate anticipation of the intended target, considering both hand and eye gaze. Results demonstrate that the proposed approach achieves a prediction accuracy of 98% in MR and 96% in VR for the pointing task using SMEIRL. During human-robot handover task, prediction accuracy using MEDIRL reached 99.9% when less than 20% and 40% of the task was left using only hand motion or both hand and eye gaze, respectively, surpassing state-of-the-art methods using Path Integral-IRL (PI-IRL), Recurrent Neural Network-Inverse Kinematics-Modified Kalman Filtering (RNNIK-MKF), Bayesian Predictor for Human Motion Trajectory (BP-HMT), and Classical kinematics of motion ( \(CM_{k=5}\) ).

In shared autonomy, human-robot handover for object delivery is crucial. Accurate robot predictions of human hand motion and intentions enhance collaboration efficiency. However, low prediction accuracy increases mental and physical demands on the user. In this work, we propose a system for predicting hand motion and intended target during human-robot handover using Inverse Reinforcement Learning (IRL). A set of feature functions were designed to explicitly capture users’ preferences during the task. The proposed approach was experimentally validated through user studies. Results indicate that the proposed method outperformed other state-of-the-art methods (PI-IRL, BP-HMT, RNNIK-MKF and CMk=5) with users feeling comfortable reaching upto 60% of the total distance to the target for handover with 90% target prediction accuracy. The target prediction accuracy reaches 99.9% when less than 20% of the task remains.

Detecting Alzheimer's disease (AD) accurately at an early stage is critical for planning and implementing disease-modifying treatments that can help prevent the progression to severe stages of the disease. In the existing literature, diagnostic test scores and clinical status have been provided for specific time points, and predicting the disease progression poses a significant challenge. However, few studies focus on longitudinal data to build deep-learning models for AD detection. These models are not stable to be relied upon in real medical settings due to a lack of adaptive training and testing. We aim to predict the individual's diagnostic status for the next six years in an adaptive manner where prediction performance improves with the number of patient visits. This study presents a Sequence-Length Adaptive Encoder-Decoder Long Short-Term Memory (SLA-ED LSTM) deep-learning model on longitudinal data obtained from the Alzheimer's Disease Neuroimaging Initiative archive. In the suggested approach, decoder LSTM dynamically adjusts to accommodate variations in training sequence length and inference length rather than being constrained to a fixed length. We evaluated the model performance for various sequence lengths and found that for inference length one, sequence length nine gives the highest average test accuracy and area under the receiver operating characteristic curves of 0.920 and 0.982, respectively. This insight suggests that data from nine visits effectively captures meaningful cognitive status changes and is adequate for accurate model training. We conducted a comparative analysis of the proposed model against state-of-the-art methods, revealing a significant improvement in disease progression prediction over the previous methods. Index Terms- Cognitive impairment, longitudinal data, multimodal data, encoder-decoder LSTM, progression predictionClinical relevanceThe proposed approach has the potential to improve understanding of Alzheimer's disease progression in diagnostics, facilitating early identification of various stages of cognitive decline leading to AD by considering its clinical variability.

Understanding issue threads is an essential aspect of software maintenance and development, aiding developers in effectively addressing and managing software-related issues. These threads typically contain an issue description, comments discussing possible solutions, and often culminate in a pull request where the proposed changes are elaborated. Even though they are crucial, understanding issue threads can be a lot of work because they are often long and complex, particularly in big projects. This paper, therefore, aims to automate the process of issue thread summarization using advanced AI models, specifically the GPT-3.5-Turbo, reducing the time spent and improving the efficiency of the interpretation process. Our approach taps into the potential of the zero-shot learning methodology, enabling the model to produce context-specific summaries without reliance on prior examples. Additionally, we have developed an algorithm that determines the most effective length for these summaries, which enhances their clarity and relevance. The performance of the model is assessed using automated metrics, including ROUGE and BART scores, for extractive and abstractive summary evaluation respectively. Further, we may like to add that summaries of around 30% to 40% of the total size of the issue thread appears to be sufficient, though it varies slightly from case to case. The model’s successful generation of brief, clear, and pertinent summaries not only boosts team communication and project management but also lays the groundwork for its future integration into a comprehensive tool for simplified exploration and comprehension of complex software repositories.

The rising demand for networked embedded systems with machine intelligence has been a catalyst for sustained attempts by the research community to implement Convolutional Neural Networks (CNN) based inferencing on embedded resource-limited devices. Redesigning a CNN by removing costly multiplication operations has already shown promising results in terms of reducing inference energy usage. This paper proposes a new method for replacing multiplications in a CNN by table look-ups. Unlike existing methods that completely modify the CNN operations, the proposed methodology preserves the semantics of the major CNN operations. Conforming to the existing mechanism of the CNN layer operations ensures that the reliability of a standard CNN is preserved. It is shown that the proposed multiplication-free CNN, based on a single activation codebook, can achieve 4.7x, 5.6x, and 3.5x reduction in energy per inference in an FPGA implementation of MNIST-LeNet-5, CIFAR10-VGG-11, and Tiny ImageNet-ResNet-18 respectively. Our results show that the DietCNN approach significantly improves the resource consumption and latency of deep inference for smaller models, often used in embedded systems. Our code is available at: https://github.com/swadeykgp/DietCNN

Microfluidic biochips have recently emerged with significant promise and versatility in automating a variety of biochemical protocols on a tiny chip. Sample preparation, which involves the mixing of fluids with a specified target ratio in the minuscule scale, is an essential component of these protocols. Algorithms that optimize on-chip sample-preparation cost and time are closely intertwined with the underlying mixing model, mixing sequence, and fluidic architecture. Although numerous mixing models have been studied in the literature, their impact on the dynamics of mixing steps is hitherto not fully understood. In this article, we show that various mixing models can be envisaged in the light of prime factorization of integers thus establishing a connection among mixing algorithms, chip architectures, and performance. This insight has led to the development of the proposed factorization-based dilution algorithm (FacDA) considering a generalized mixing model suitable for micro-electrode-dot-array (MEDA) biochips. It further leads to target volume oriented dilution algorithm (TVODA) to cater to user’s demand for an output with a given volume. We formulate the optimization problem on the fabric of the satisfiability modulo theory (SMT) while determining mixing sequences. Simulation results on a large number of test-cases reveal thatFacDAandTVODAoutperform the state-of-the-art dilution algorithms for MEDA biochips with respect to reactant cost, mixing time, and waste production.

Sample preparation, an essential preprocessing step for biochemical protocols, is concerned with the generation of fluids satisfying specific target ratios and error-tolerance. Recent micro-electrode-dot-array (MEDA)-based DMF biochips provide the advantage of supporting both discrete and dynamic mixing models, the power of which has not yet been fully harnessed for implementing on-chip dilution and mixing of fluids. In this paper, we propose a novel factorization-based algorithm called FacDA for efficient and accurate dilution of sample fluid on a MEDA chip. Simulation results reveal that over a large number of test-cases with the mixing volume constraint in the range of 4--10 units, FacDA requires around 38% fewer mixing steps, 52% less sample units, and generates approximately 23% less wastage, all on average, compared to two prior dilution algorithms used for MEDA chips.

Recent studies in algorithmic microfluidics have led to the development of several techniques for automated solution preparation using droplet-based digital microfluidic (DMF) biochips. A major challenge in this direction is to produce a mixture of several reactants with a desired ratio while optimizing reactant cost and preparation time. The sequence of mix-split operations that are to be performed on the droplets is usually represented as a mixing tree (or graph). In this article, we present an efficient mixing algorithm, namely, Mixing Tree with Common Subtrees ( MTCS ), for preparing single-target mixtures. MTCS attempts to best utilize intermediate droplets, which were otherwise wasted, and uses morphing based on permutation of leaf nodes to further reduce the graph size. The technique can be generalized to produce multitarget ratios, and we present another algorithm, namely, Multiple Target Ratios ( MTR ). Additionally, in order to enhance the output load, we also propose an algorithm for droplet streaming called Multitarget Multidemand ( MTMD ). Simulation results on a large set of target ratios show that MTCS can reduce the mean values of the total number of mix-split steps ( T ms ) and waste droplets ( W ) by 16% and 29% over Min-Mix (Thies et al. 2008) and by 22% and 34% over RMA (Roy et al. 2015), respectively. Experimental results also suggest that MTR can reduce the average values of T ms and W by 23% and 44% over the repeated version of Min-Mix , by 30% and 49% over the repeated version of RMA , and by 9% and 22% over the repeated-version of MTCS , respectively. It is observed that MTMD can reduce the mean values of T ms and W by 64% and 85%, respectively, over MTR . Thus, the proposed multitarget techniques MTR and MTMD provide efficient solutions to multidemand, multitarget mixture preparationon a DMF platform.

Classical fault attacks, such as differential fault analysis(DFA) as well as biased fault attacks, such as the differential fault intensity analysis (DFIA), have been a major threat to cryptosystems in recent times. DFA uses pairs of fault-free and faulty ciphertexts to recover the secret key. DFIA, on the other hand, combines principles of side-channel analysis and fault attacks to try and extract the key using faulty ciphertexts only. Till date, no effective countermeasure that can thwart both DFA- as well as DFIA-based attacks has been reported in the literature to the best of our knowledge. In particular, traditional redundancy-based countermeasures that assume uniform fault distributions are found to be vulnerable against the DFIA due to its use of biased fault models. In this paper, we propose a novel generic countermeasure strategy that combines the principles of redundancy with that of fault space transformation to achieve security against both DFA- and DFIA-based attacks on AES-like block ciphers. As a case study, we have applied our proposed technique to obtain temporal and spatial redundancy-based countermeasures for AES-128, and have evaluated their security against both DFA and DFIA via practical experiments on a SASEBO-GII board. Results show that our proposed countermeasure makes it practically infeasible to obtain a single instance of successful fault injection, even in the presence of biased fault models.

Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and quality-of-service guarantees on multiprocessors form an attractive alternative in real-time embedded systems that concurrently run a mix of independent applications with varying timeliness constraints. This article presents ERfair Scheduler with Suspension on Multiprocessors (ESSM) , an efficient, optimal proportional fair scheduler that attempts to reduce system wide energy consumption by locally maximizing the processor suspension intervals while not sacrificing the ERfairness timing constraints of the system. The proposed technique takes advantage of higher execution rates of tasks in underloaded ERfair systems and uses a procrastination scheme to search for time points within the schedule where suspension intervals are locally maximal. Evaluation results reveal that ESSM achieves good sleep efficiency and provides up to 50% higher effective total sleep durations as compared to the Basic-ERfair scheduler on systems consisting of 2 to 20 processors.

Automotive software applications implement a variety of control algorithms, with many of them being safety-critical in nature. A typical design flow starts with modeling these control algorithms using tools like MATLAB/Simulink. However, at this stage, a number of assumptions, like negligible sensor-to-actuator delay and instantaneous computation of the controller software, are often made. In particular, the details of the software implementation and the computing platform, both eventually defining the timing properties of the applications, are not accounted for. Such idealistic assumptions can cause a significant deviation of the control performance compared to what was proven at the modeling stage. This is usually addressed with multiple design iterations, which are costly and may lead to over-provisioned and thus poorly designed systems. In this paper we attempt to address this problem by proposing a design-and tool flow that integrates software-and platform-level timing information into the high-level modeling stage. We outline our proposed flow using concrete, industry-strength design tools.

The recent proliferation of digital microfluidic (DMF) biochips has enabled rapid on-chip implementation of many biochemical laboratory assays or protocols. Sample preprocessing, which includes dilution and mixing of reagents, plays an important role in the preparation of assays. The automation of sample preparation on a digital microfluidic platform often mandates the execution of a mixing algorithm, which determines a sequence of droplet mix-split steps (usually represented as a mixing graph). However, the overall cost and performance of on-chip mixture preparation not only depends on the mixing graph but also on the resource allocation and scheduling strategy, for instance, the placement of boundary reservoirs or dispensers, mixer modules, storage units, and physical design of droplet-routing pathways. In this article, we first present a new mixing algorithm based on a number-partitioning technique that determines a layout-aware mixing tree corresponding to a given target ratio of a number of fluids. The mixing graph produced by the proposed method can be implemented on a chip with a fewer number of crossovers among droplet-routing paths as well as with a reduced reservoir-to-mixer transportation distance. Second, we propose a routing-aware resource-allocation scheme that can be used to improve the performance of a given mixing algorithm on a chip layout. The design methodology is evaluated on various test cases to demonstrate its effectiveness in mixture preparation with the help of two representative mixing algorithms. Simulation results show that on average, the proposed scheme can reduce the number of crossovers among droplet-routing paths by 89.7% when used in conjunction with the new mixing algorithm, and by 75.4% when an earlier algorithm [Thies et al. 2008] is used.

In many biochemical protocols, such as polymerase chain reaction, a mixture of fluids in a certain ratio is repeatedly required, and hence a sufficient quantity of the mixture must be supplied for assay completion. Existing sample-preparation algorithms based on digital microfluidics (DMF) emit two target droplets in one pass, and costly multiple passes are required to sustain the emission of the mixture droplet. To alleviate this problem, we design a streaming engine on a DMF biochip, which optimizes droplet emission depending on the demand and available storage. Simulation results show significant reduction in latency and reactant usage for mixture preparation.

Fault-tolerance of embedded control systems is of great importance, given their wide usage in various domains such as aeronautics, automotive, medical, and so on. Signal perturbations such as small amounts of noise, shift, and spikes, can sometimes severely hamper the performance of the system, apart from complete failure of components and links. Finding minimal counterexamples (perturbations on the system leading to violation of fault-tolerance requirements) can be of great assistance to control system designers in understanding and adjusting the fault-tolerance behavior of the system. Fault injection is an effective method for dependability analysis of such systems. In this paper, we introduce the concept of dominating sets of perturbations, and define a minimal set of counterexamples called the basis. We propose effective methods using a simulation-based fault injection technique on Simulink models for finding the basis set at an early stage of design, given the fault specification and fault-tolerance requirements. Experimental results on two different control system examples from the Simulink automotive library demonstrate the efficacy of the proposed framework.

Digital microfluidic biochips are recently being developed for on-chip implementation of biochemical laboratory assays. Existing mixing algorithms determine the mixing tree or mixing graph from a given target ratio of several biochemical fluids for on-chip mixture preparation. We present an algorithm to determine a reduced mixing tree by sharing the common subtrees within itself. We observe two transformations that preserve the semantics of the tree: (a) permutation of leaf nodes (input fluids/reagents) within the same level of a mixing tree, and (b) level-shifting of a leaf node to the next lower level by duplicating its appearance. The proposed algorithm utilizes both the intermediate droplets obtained after a split operation when a pair of identical subtrees are identified under permutation of leaf nodes at the same level. Simulation results for a large set of target ratios show that our algorithm reduces the mean values of the total number of mix-split steps, waste droplets and the number of mixer modules required for earliest completion by 16%, 29% and 12% over Min-Mix and by 22%, 34% and 20% over RMA, respectively. Moreover, it reduces the number of checkpoint insertions required for dynamic error recovery against incorrect mix-split steps during mixture preparation.

We present a mobility simulation framework that simulates the movement behaviors of people to generate spatiotemporal movement data. There is a growing interest in applications that make use of patterns mined from spatio-temporal data. However, since the availability of actual spatio-temporal movement data in the public domain is limited, it is useful to have simulation frameworks that generate data close to the real life behavior of people, so that data mining techniques can be tested. We argue that modeling group behavior effectively is a key element of any real-life simulation framework, because there are many applications that require the knowledge of groups and events. In this work, we propose generic models to represent individual and group movement behaviors. We present an algorithm that takes various behaviors created using the proposed models, and generates spatio-temporal movement data for as many individuals as needed. Experimental analysis shows the efficacy of the proposed framework handling a broad spectrum of behaviors with high scalability.

In this paper we consider finding solutions for problems represented using AND/OR graphs, which contain tasks that can fail when executed. In our setting each node represent an atomic task which is associated with a failure probability and a rollback penalty. This paper reports the following contributions - (a) an algorithm for finding the optimal ordering of the atomic tasks in a given solution graph which minimizes the expected penalty, (b) an algorithm for finding the optimal ordering in the presence of user defined ordering constraints, and (c) a counter example showing the lack of optimal substructure property for the problem of finding the solution graph having minimum expected penalty, and a pseudo-polynomial algorithm for finding the solution graph with minimum expected penalty.

We present algorithms for generating alternative solutions for explicit acyclic AND/OR structures in non-decreasing order of cost. The proposed algorithms use a best first search technique and report the solutions using an implicit representation ordered by cost. In this paper, we present two versions of the search algorithm -- (a) an initial version of the best first search algorithm, ASG, which may present one solution more than once while generating the ordered solutions, and (b) another version, LASG, which avoids the construction of the duplicate solutions. The actual solutions can be reconstructed quickly from the implicit compact representation used. We have applied the methods on a few test domains, some of them are synthetic while the others are based on well known problems including the search space of the 5-peg Tower of Hanoi problem, the matrix-chain multiplication problem and the problem of finding secondary structure of RNA. Experimental results show the efficacy of the proposed algorithms over the existing approach. Our proposed algorithms have potential use in various domains ranging from knowledge based frameworks to service composition, where the AND/OR structure is widely used for representing problems.

We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.

This paper presents an online scheduling methodology for task graphs with communication edges for multiprocessor embedded systems. The proposed methodology is designed for task graphs which are dynamic in nature either due to the presence of conditional paths or due to presence of tasks whose execution times vary. We have assumed homogeneous processors with broadcast and point-to-point communication models and have presented online algorithms for them. We show that this technique adapts better to variation in task graphs at runtime and provides better schedule length compared to a static scheduling methodology. Experimental results indicate up to 21.5 percent average improvement over purely static schedulers. The effects of model parameters like number of processors, memory, and other task graph parameters on performance are investigated in this paper.

This work presents a static-analysis based method for analyzing the robustness of a given embedded control system design, in the presence of quality-faults in sensors, software components, and inter-connections. The method characterizes the individual components of the system by storing the relations between the precision of inputs and the precision of outputs in what we call, lookup tables (LUTs). A network of LUTs thus formed which represent the given control system is converted into a satisfiability modulo theory (SMT) instance, such that a satisfying assignment corresponds to a potential counterexample (the set of quality-faults which violate the given fault-tolerance requirements) or hot-spot in the design. Hot-spots obtained in this manner are counter-verified through simulation to filter the false-positives. Experimental results on the fault-tolerant fuel controller from Simulink automotive library demonstrate the efficacy of the proposed approach.

This paper presents a heuristic-search algorithm called Memory-bounded Anytime Window A∗ (MAWA∗), which is complete, anytime, and memory bounded. MAWA∗ uses the window-bounded anytime-search methodology of AWA∗ as the basic framework and combines it with the memory-bounded A∗ -like approach to handle restricted memory situations. Simple and efficient versions of MAWA∗ targeted for tree search have also been presented. Experimental results of the sliding-tile puzzle problem and the traveling-salesman problem show the significant advantages of the proposed algorithm over existing methods.

In this work, we present a heuristic search technique (Contract Search) which can be automatically adapted for a specified node expansion limitation. We analyze the node expansion properties of best first search and propose a probabilistic model (rank profile) to characterize heuristic search under restricted expansions. We identify the basic properties of the rank profile and establish its relation with the search space configuration. In Contract Search, we use the rank profile model to formulate an optimal strategy to choose level dependent restriction bounds maximizing the probability of obtaining the goal node under the specified contract. Experimental comparison with anytime search techniques like ARA* and beam search shows that Contract Search outperforms these techniques over a range of constraint specifications.

In this article, we present a heuristic search technique (Contract Search) that can be adapted automatically for a specific node contract. We analyze the node expansion characteristics of best‐first search techniques and identify a probabilistic model (rank profiles) that characterizes the search under restricted expansions. We use the model to formulate an optimal strategy to choose level dependent restriction bounds, maximizing the probability of obtaining the optimal cost goal node under the specified contract. We analyze the basic properties of the rank profiles and establish its relation with the search space configuration and heuristic error distributions. We suggest an approximation scheme for the profile function for unknown search spaces. We show how the basic framework can be adapted to achieve different objectives (like optimizing the expected quality) considering multiple goals and approximate solutions. Experimental comparison with anytime search techniques like ARA* and beam search on a number of search problems shows that Contract Search outperforms these techniques over a range of contract specifications.

Overheating of computer chips leads to degradation of performance and reliability. Therefore, preventing chips from overheating in spite of increased performance requirements has emerged as a major challenge. Since the cost of cooling has been rising steadily, various architecture and application design techniques are used to prevent chip overheating. Temperature-aware task scheduling has emerged as an important application design methodology for addressing this problem in multiprocessor SoC systems. In this work we present the formulation and implementation of a method for analyzing the thermal (chip heating) behavior of a MPSoC task schedule, during the early stages of the design. We highlight the challenges in developing such a framework and propose solutions for tackling them. Due to nondeterminism in task execution times and decision branches, multiprocessor applications cannot be evaluated accurately by the current state-of-the-art thermal simulation and steady-state analysis methods. Hence an analysis covering nondeterministic execution behaviors is required for thermal analysis of MPSoC task schedules. To address this issue we propose a model checking-based approach for solving the thermal analysis problem and formulate it as a hybrid automata reachability verification problem. We present an algorithm for constructing this hybrid automata given the task schedule, a set of power profiles of tasks, and the Compact Thermal Model (CTM) of the chip. Information about task power consumption is inferred from Markov chains which are learned from power profiles of tasks, obtained from simulation or emulation runs. A numerical analysis-based algorithm which uses CounterExample-Guided Abstraction Refinement (CEGAR) is developed for reachability analysis of this hybrid automata. We propose a directed simulation methodology which uses results of a time-bounded analysis of the hybrid automata modeling thermal behavior of the application, to simulate the expected worst-case execution runs of the same. The algorithms presented in this work have been implemented in a prototype tool called HeatCheck . We present experimental results and analysis of thermal behavior of a set of task schedules executing on a MPSoC system.

Putting the processor into shutdown state when it is idling is one of the primary methodologies towards the reduction of energy consumption in today's systems where leakage power is emerging as a dominant concern. This paper presents ERfair Scheduler with Processor Shutdown (ESPS), a uniprocessor ERfair scheduler that attempts to minimize energy consumption in rate-based periodic real-time task systems by locally maximizing processor shut-down intervals while simultaneously maintaining proportional fairness among task executions. Evaluation results show that our proposed algorithm achieves good shut-down efficiency and provides upto 9 times higher effective shutdown lengths as compared to the Basic_ERfair scheduler.

This work presents a static timing-analysis method for verification of scenario-based real-time properties, on graphical task-level models of embedded applications. Scenario-based properties specify timing constraints which must be honored for specific control-flow behaviors and task execution orderings. Static checking of scenario-based properties currently requires computationally expensive model checking methods. Hence the proposed graph-based static timing-analysis algorithm improves upon the state-of-the-art. This is manifested in a significant performance advantage over timed model checking (up to 1000X in several cases), which suffers from state space explosion. The proposed algorithm also employs compositional reasoning and abstraction refinement for handling large problems. We also illustrate methods for using scenario-based timing analysis, which can act as alternatives to traditional timed model checking for verification of timed systems like FDDI and Fischer protocols. We implement this timing verification algorithm as a tool called SymTime and present experimental results for SymTime comparing it with SPIN, UPPAAL, and a TCTL model checker for Time Petri Nets, called Romeo.

Design intent coverage is a formal methodology for analyzing the gap between a formal architectural specification of a design and the formal functional specifications of the component RTL blocks of the design. In this article we extend the design intent coverage methodology to hybrid specifications containing both state-machines and formal properties. We demonstrate the benefits of this extension in two domains of considerable recent interest, namely (a) the use of auxiliary state-machines in formal specifications, and (b) the use of modest sized RTL blocks in the design intent coverage analysis.

Formal specifications of interface protocols between a design-under-test and its environment mostly consist of two types of correctness requirements, namely (a) a set of invariants that applies throughout the protocol execution and (b) a set of context-triggered properties that applies only when the protocol state belongs to a specific set of contexts. To model such requirements, an increasingly popular design choice in the assertion IP design community has been the use of abstract context state machines and state-oriented properties. In this paper, we formalize this modeling style and present algorithms for verifying such specifications. Specifically, we present a purely formal approach and a semi-formal approach for verifying such specifications. We demonstrate the use of this design style in modeling some of the industry standard protocol descriptions and present encouraging results.

We propose a specification logic called Temporally Attributed Boolean (TAB) Logic for Assertion Based Verification, which allows us to: (i) represent assertions succinctly, (ii) incorporate data-orientation and (iii) associate timing to design intentions. TAB Logic allows us to write specifications functionally linking system variables from different temporal contexts. We present examples to show the motivation for this logic especially in the context of high level modeling of complex real time systems. We formally define TAB Logic, formulate the problem of verification on a simulation trace and present efficient algorithms to check TAB assertions, both offline and online. We present results of application of TAB Logic for Instruction Semantics and Bus Transaction Verification of a bus integrated pipelined processor core implementation. We also employ TAB Logic to validate the Interrupt mode behavior of the processor core implementation. Further, we show the utility of TAB Logic in fault detection. Finally, we demonstrate the applicability of TAB Logic in the domain of simulation based verification of analog circuits like Operational Amplifiers and DC-DC Converters. We finally discuss the limitations of TAB logic and conclude.

This paper presents a hybrid scheduling methodology for task graphs to multiprocessor embedded systems. The proposed methodology is designed for task graphs that are dynamic in nature due to the presence of conditional tasks and tasks whose execution times are unpredictable but bounded. We have presented the methodology as a three-phase strategy, in which task nodes are mapped to the processors in the first (static mapping) phase. In the second (selective duplication) phase, some critical nodes are identified and duplicated for possible rescheduling at runtime, depending on the code memory constraints of the processors. The third (online) phase is a runtime scheduling algorithm that performs list scheduling based on the actual dynamics of the schedule up to the current time. We show that this technique provides better schedule length (up to 20 percent) compared to previous techniques, which are predominantly static in nature, with low overhead and a complexity comparable with existing online techniques. The effects of model parameters like the number of processors, memory, and various task graph parameters on performance are investigated in this paper.

A satisfiability-based technique for symbolic modeling of event propagation in a circuit is presented in this paper which captures the events in the internal nodes of the circuit with a high level of detail. The model is used to accurately measure the peak single cycle transition power consumption in combinational and sequential circuits, which is closely affected by the switching activity in the circuit. Our technique is scalable, and adapts easily to ever increasing sizes of the custom cells (building blocks) in today's industry, without compromising on accuracy and correctness.

We address the problem of optimizing the quality-time tradeoff of very large scale integration (VLSI) computer-aided design (CAD) algorithms working under various constrained environments. We present a unified meta-reasoning framework to automatically control the progress of iteratively improving CAD algorithms. The control framework uses profile knowledge about the quality-time relation of the algorithms used and generates a combined strategy for time allocation and parameter control that optimizes the expected tradeoff. We present specific formulations for handling single and multiple problems (both dependent and independent) under various constraints. We use the proposed strategies for adjusting the control parameters of standard simulated annealing and genetic algorithm based techniques used in VLSI optimization along with an appropriate time allocation suited for different constraint specifications. Application on several classical problems in the VLSI domain shows that significant improvement in quality-time tradeoff can be achieved.

Typical analog and radio frequency (RF) circuit sizing optimization problems are computationally hard and require the handling of several conflicting cost criteria. Many researchers have used sequential stochastic refinement methods to solve them, where the different cost criteria can either be combined into a single-objective function to find a unique solution, or they can be handled by multiobjective optimization methods to produce tradeoff solutions on the Pareto front. This paper presents a method for solving the problem by the former approach. We propose a systematic method for incorporating the tradeoff wisdom inspired by the circuit domain knowledge in the formulation of the composite cost function. Key issues have been identified and the problem has been divided into two parts: a) normalization of objective functions and b) assignment of weights to objectives in the cost function. A nonlinear, parameterized normalization strategy has been proposed and has been shown to be better than traditional linear normalization functions. Further, the designers' problem specific knowledge is assembled in the form of a partially ordered set, which is used to construct a hierarchical cost graph for the problem. The scalar cost function is calculated based on this graph. Adaptive mechanisms have been introduced to dynamically change the structure of the graph to improve the chances of reaching the near-optimal solution. A correlated double sampling offset-compensated switched capacitor analog integrator circuit and an RF low-noise amplifier in an industry-standard 0.18mum CMOS technology have been chosen for experimental study. Optimization results have been shown for both the traditional and the proposed methods. The results show significant improvement in both the chosen design problems

With the advent of multiprocessor embedded platforms, application partitioning and mapping have gained primacy as a design step. The output of this design step is a multithreaded partitioned application where each thread is mapped to a processing element (processor or ASIC) in the multiprocessor platform. This partitioned application must be verified to be consistent with the native unpartitioned application. This verification task is called application (or task) partitioning verification. This work proposes a code-block-level containment-checking -based methodology for application partitioning verification. We use a UML-based code-block-level modeling language which is rich enough to model most designs. We formulate the application partitioning verification problem as a special case of the containment checking problem, which we call the complete containment checking problem . We propose a state space reduction technique specific to the containment checking, reachability analysis, and deadlock detection problems. We propose novel data structures and token propagation methodologies which enhance the efficiency of containment checking. We present an efficient containment checking algorithm for the application partitioning verification problem. We develop a containment checking tool called TraceMatch and present experimental results. We present a comparison of the state space reduction achieved by TraceMatch with that achieved by formal analysis and verification tools like Spin, PEP, PROD, and LoLA.

We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for analog circuit verification) which is suitable for specifying properties specific to analog circuits. The application of Ana CTL for validation of transient behavior of arbitrarily nonlinear analog circuits is presented. The transient response of a circuit under all possible input waveforms is represented as a finite state machine (FSM), by bounding and discretizing the continuous state space of an analog circuit. We have developed algorithms to run Ana CTL queries on this discretized model using search-based methods which reduce the runtime considerably by avoiding creation of the whole FSM. The application of these methods on several real-life analog circuits is presented and we show that this system is a useful aid for detecting and debugging early design errors. We also present methods for checking the equivalence of transient response of two analog circuits. The behavior of two different analog circuits can rarely be exactly similar. Hence, we introduce a notion of approximate equivalence. A query language for checking different notions of user-definable approximate equivalence is presented which extends the syntax of the Ana CTL model checking language. In its extended form, Ana CTL can be used combining model checking with equivalence checking.

A SAT-based modeling for event propagation in gate-level digital circuits, which is used for accurate calculation of critical delay in combinational and sequential circuits, is presented in this article. The accuracy of the critical delay estimation process depends on the accuracy with which the circuit in operation is modeled. A high level of precision in the modeling of the internal events in a circuit for the sake of greater accuracy causes a combinatorial blowup in the size of the problem, resulting in a scalability bottleneck for which most existing techniques effect a trade-off by restricting themselves to less precise models. SAT based techniques have a good track record in efficiency and scalability when the problem sizes become too large for most other methods. This article proposes a SAT-based technique for symbolic event propagation within a circuit which facilitates the estimation of the critical delay of circuits with a greater degree of accuracy, while at the same time scaling efficiently to large circuits. We report very encouraging results on the ISCAS85 and ISCAS89 benchmark circuits using the proposed technique.

The UML activity diagram language is the de facto language for behavioral modeling capable of block level modeling of real time multiprocessor SoC applications where timing behavior is a critical aspect. Although there are several tools for timing verification of logics with branching time semantics, there are no known model checkers for timing verification of logics with linear time semantics as needed for many verification tasks. This work deals with timing verification of UML activity diagram models of applications. We propose a subset of TPTL (timed prepositional temporal logic) for specifying timing queries. We develop an automata based model checker for verifying such queries. We present a comparison of the proposed timing verification with the state of the art for random test-cases.

The design of a large chip is typically hierarchical - large modules are recursively expanded into a collection of sub-modules. Each expansion refines the design due to the addition of level specific details. We believe that a similar approach is necessary to scale the capacity of formal property verification technology - as the design gets refined from one level to another, the formal specification must also be refined to reflect the level specific design decisions. At the heart of this approach we propose a checker that identifies the input assumptions under which the refined specification "covers" the original specification. This enables the validation engineer to focus the verification effort on the remaining input scenarios thereby reducing the number of target coverage points for simulation.

Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that can be checked on the sub-modules of the parent module. To support this methodology, we have developed a formal methodology for verifying whether the decomposition is indeed sound and complete, that is, whether verifying the smaller properties on the submodules actually guarantees the original property on the parent module. In practice, however designers do not write properties for all modules and thereby our previous methodology was applicable to selected cases only. In this paper we present new formal methods that allow us to handle RTL blocks in the analysis. We believe that the new approach will significantly widen the scope of the methodology, thereby enabling the validation engineer to handle much larger designs than admitted by existing formal verification tools

This paper presents a multi-objective evolutionary algorithm based approach to yield-inclusive design space exploration of analog circuits. The yield objective function is included from the beginning in the optimization cycle, and is estimated economically by support vector regression models built from training data provided by the optimization process itself. We propose techniques to effectively handle the inaccurate nature of model-based yield estimates through various stages of the optimization process, and a two-level hybrid algorithm to keep the modeling cost reasonable. The experimental results presented for two real-world circuit examples look encouraging and show the effectiveness of the proposed method in providing designers with multiple trade-off choices

The main contributions of this paper are as follows: We revisit the concept of multiplayer coalition games in the context of a 3-party system. We analyze the coalition realizability problem for different degrees of observability of the module and the controller. We show that the realizability problem can be expressed as an instance of quantified Boolean formulas (QBF), by using appropriate quantifications on the variables of the environment, the module and the controller. We then use recent QBF solvers to verify

All known real-time proportional fair scheduling mechanisms either have high scheduling overheads (O(lg n) per time-slot) or do not efficiently handle dynamic task sets. This paper presents frame-based proportional round-robin (FBPRR), a real-time fair scheduler providing high and bounded proportional fairness accuracy and O(1) scheduling overhead with the ability to efficiently handle a set of dynamic tasks. FBPRR achieves this by applying the benefits of virtual-time round-robin (VTRR) scheduling mechanism within a frame-based scheduling approach. Simulation results show that the algorithm gains a speedup of 5 to 20 times (over O(lg n) complexity schedulers) with fairly high fairness

It is essential to formally ascertain whether the register-transfer level (RTL) validation effort effectively guarantees the correctness with respect to the design's architectural intent. The design's architectural intent can be expressed in formal properties. However, due to the capacity limitations of formal verification, these architectural properties cannot be directly verified on the RTL. As a result, a set of lower level RTL properties are developed and verified against the RTL modules. In a top-down design approach, the architect would ideally like to formally guarantee the coverage of the architectural intent at the time of creating the specifications for the component RTL modules (that is, before they are passed to the designers for implementation). In this paper, the authors present: 1) a method for checking whether the RTL properties are covering the architectural properties, that is, whether verifying the RTL properties guarantees the correctness of the design's architectural intent; 2) a method to identify which architectural properties are still uncovered, that is, not guaranteed by the RTL properties; and 3) a methodology for representing the gap between the specifications in a legible form

Present-day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching, and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures the complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths, as well as conditions for such situations. This information is then represented as an event-time graph. A temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A binary decision diagram-based implementation of this system has been made. Results on the International Symposium on Circuits and Systems (ISCAS)85 benchmarks are presented.

The knowledge of optimal design space boundaries of component circuits can be extremely useful in making good subsystem-level design decisions which are aware of the parasitics and other second-order circuit-level details. However, direct application of popular multi-objective genetic optimization algorithms were found to produce Pareto fronts with poor diversity for analog circuit problems. The paper proposes a novel approach to control the diversity of solutions by partitioning the solution space, using local competition to promote diversity and global competition for convergence, and by controlling the proportion of these two mechanisms by a simulated annealing based formulation. The algorithm was applied to extract numerical results on analog switched capacitor integrator circuits with a wide range of tight specifications. The results are found to be significantly better than traditional GA based uncontrolled optimization methods.

Formal property verification is increasingly being adopted by designers for module level validation. The behavior of a module is typically expressed in terms of the behavioral guarantee of the module under assumptions on its environment. Expressing such assume-guarantee properties correctly in a formal language is a nontrivial task and errors in the specification are not uncommon. In this paper we examine the main forms of specification errors for open systems, and present SAT based algorithms for verifying the specification against such errors.

We present a method for automated synthesis of analog circuits using evolutionary search and a set of circuit design rules based on topological reuse. The system requires only moderate expert knowledge on part of the user. It allows circuit size, circuit topology, and device values to evolve. The circuit representation scheme employs a topological reuse-based approach-it uses commonly used subcircuits for analog design as inputs and utilizes these to create the final circuit. The connectivity between these blocks is governed by a well-defined set of rules and the scheme is capable of representing most standard analog circuit topologies. The system operation consists of two phases-in the first phase, the circuit size and topology are evolved. A limited amount of device sizing also occurs in this phase. The second phase consists entirely of device value optimization. The design of the evaluation function-which evaluates each generated circuit using SPICE simulations-has also been automated to a great extent. The evaluation function is generated automatically depending on a behavioral description of the circuit. We present several experimental results obtained using this scheme, including two types of comparators, two types of oscillators, and an XOR logic gate. The generated circuits closely resemble hand designed circuits. The computational needs of the system are modest.

Microprocessor pipeline simulation at the system level is an extremely important activity in the architecture exploration process. In this article, we address the problem of validating and debugging a pipeline simulator from the specific perspective of instruction scheduling. We propose a general framework for a systematic validation process and show that the assumptions made are justified for most standard pipeline models. The framework does not need any formal specification of the pipeline logic and hence can be readily integrated into the simulation and iteration-based architectural design space exploration process. We propose a concept of semantic equivalence between two simulations called D* equivalence which effectively captures the dataflow between instructions through registers. We then proceed to propose an algorithm which decides this equivalence in time polynomial in the number of instructions executed and the number of registers. We implement the algorithm and demonstrate how the framework facilitates debugging.

It is essential to formally ascertain whether the RTL validation effort effectively guarantees the correctness with respect to the design's architectural intent. The design's architectural intent can be expressed in formal properties. However, due to the capacity limitation of formal verification, these architectural-properties cannot be directly verified on the RTL. As a result, a set of lower level RTL-properties are developed and verified against the RTL. In this paper we present: (1) a method for checking whether the RTL-properties are covering the architectural-properties, that is, whether verifying the RTL-properties guarantee the correctness of the design's architectural intent; and (2) a method to identify the coverage holes in terms of the architectural properties (or their sub-properties) that are not covered.

Present day designers require deep reasoning methods to analyze circuit timing. This includes analysis of effects of dynamic behavior (like glitches) on critical paths, simultaneous switching and identification of specific patterns and their timings. This paper proposes a novel approach that uses a combination of symbolic event propagation and temporal reasoning to extract timing properties of gate-level circuits. The formulation captures complex situations like triggering of traditional false paths and simultaneous switching in a unified symbolic representation in addition to identifying false paths, critical paths as well as conditions for such situations. This information is then represented as an event-time graph. A simple temporal logic on events is proposed that can be used to formulate a wide class of useful queries for various input scenarios. These include maximum/minimum delays, transition times, duration of patterns, etc. An algorithm is developed that retrieves answers to such queries from the event-time graph. A complete BDD based implementation of this system has been made. Results on the ISCAS85 benchmarks indicate very interesting properties of these circuits.

Existing methods for formal verification coverage compare a given specification with a given implementation, and evaluate the coverage gap in terms of quantitative metrics. We consider a new problem, namely to compare two formal temporal specifications and to find a set of additional temporal properties that close the coverage gap between the two specifications. In this paper we present: (1) the problem definition and motivation, (2) a methodology for computing the coverage gap between specifications, and (3) a methodology for representing the coverage gap as a collection of temporal properties that preserve the syntactic structure of the target specification.

A typical verification IP (VIP) of a bus protocol such as ARM AMBA or PCI consists of a set of assertions and associated verification aids like test-benches and coverage metrics. While, several languages have been formalized for specifying assertions (examples include OVA, Sugar, ForSpec, SVA, etc), the tasks of writing test-benches that produce protocol compliant stimuli and coverage monitors that reflect the coverage of the protocol functionality are also of significant importance. This paper presents a platform for high-level specification of a bus protocol and an automated methodology for generating a variety of verification aids that must supplement the set of assertions in a VIP.

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Presents a framework for efficiently solving logic formulations of combinatorial optimization problems using heuristic search techniques. In order to integrate cost, lower-bound and upper-bound specifications with conventional logic programming languages, we augment a constraint logic programming (CLP) language with embedded constructs for specifying the cost function and with a few higher-order predicates for specifying the lower and upper bound functions. We illustrate how this simple extension vastly enhances the ease with which optimization problems involving combinations of Min and Max can be specified in the extended language CLP* and we show that CSLDNF (Constraint SLD resolution with Negation as Failure) resolution schemes are not efficient for solving optimization problems specified in this language. Therefore, we describe how any problem specified using CLP* can be converted into an implicit AND/OR graph, and present an algorithm called GenSolve which can branch-and-bound using upper and lower bound estimates, thus exploiting the full pruning power of heuristic search techniques. A technical analysis of GenSolve is provided. We also provide experimental results comparing various control strategies for solving CLP* programs.

RTL descriptions for word-level arithmetic components typically specify the architecture at the bit-level of the registers. The problem studied in this paper is to abstract the word-level functionality of a component from its bit-level specification. This is particularly useful in simulation since word-level descriptions can be simulated much faster than bit-level descriptions. Word-level abstractions are also useful for reducing the complexity of component matching since the number of words is significantly smaller than the number of bits. This paper presents an algorithm for abstraction of word-level linear functions from bit-level component descriptions. We also present complexity results for component matching which justifies the advantage of performing abstraction prior to component matching.

We propose a new style of model checking of timed transition systems, where instead of reasoning about the timing of states with specific properties, we reason about the timings of events with specific properties. This shift in paradigm appears to be useful for verification of edge triggered control paths, where we are more interested in the timings of changes in signal values. We propose a temporal logic, event-triggered timed computation tree logic (ETCTL), which allows the specification of event properties such as posedge(signal) and negedge(signal) along with real time computation tree logic (RTCTL) properties. We show that all ETCTL properties are interval independent, that is, their truth can never change on states between successive events. By virtue of the interval independent property, reasoning about timings of events (using ETCTL) is more efficient computationally than reasoning about general timed properties. We present a labeling algorithm, and suggest extensions to automata theoretic and symbolic approaches.

We present here a technique for allocation and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach. This GA uses an unconventional crossover mechanism relying on a force directed data path binding completion algorithm. The data path is synthesized using some supplied design parameters. A bus-based interconnection scheme, use of multi-port memories, and provision for multicycling and pipelining are the main features of this system. The method presented here has been applied to standard benchmark examples and the results obtained are promising.

This paper presents a generalized formulation of precedence constrained scheduling where the number of dependent tasks which are to be scheduled before the task itself can be scheduled is a variable. This formulation is capable of modeling a number of scheduling and path-finding problems. An algorithm is presented to solve the problem of finding the minimum time schedule. Variants are discussed. One simple variant is shown to be NP-Complete.

In this paper, we examine the multicriteria optimization involved in scheduling for data-path synthesis (DPS). The criteria we examine are the area cost of the components and schedule time. Scheduling for DPS is a well-known NP-complete problem. We present a method to find nondominated schedules using a combination of restricted search and heuristic scheduling techniques. Our method supports design with architectural constraints such as the total number of functional units, buses, etc. The schedules produced have been taken to completion using GABIND as written by Mandal et al., and the results are promising.

We provide an overall framework for learning in search based systems that are used to find optimum solutions to problems. This framework assumes that prior knowledge is available in the form of one or more heuristic functions (or features) of the problem domain. An appropriate clustering strategy is used to partition the state space into a number of classes based on the available features. The number of classes formed will depend on the resource constraints of the system. In the training phase, example problems are run using a standard admissible search algorithm. In this phase, heuristic information corresponding to each class is learned. This new information can be used in the problem solving phase by appropriate search algorithms so that subsequent problem instances can be solved more efficiently. In this framework, we also show that heuristic information of forms other than the conventional single valued underestimate value can be used, since we maintain the heuristic of each class explicitly. We show some novel search algorithms that can work with some such forms. Experimental results have been provided for some domains.

We investigate the role of learning in search-based systems for solving optimization problems. We use a learning model, where the values of a set of features can be used to induce a clustering of the problem state space. The feasible set of h* values corresponding to each cluster is called h*set. If we relax the optimality guarantee, and tolerate a risk factor, the distribution of h*set can be used to expedite search and produce results within a given risk of suboptimality. The off-line learning method consists of solving a batch of problems by using A* to learn the distribution of the h*set in the learning phase. This distribution can be used to solve the rest of the problems effectively. We show how the knowledge acquisition phase can be integrated with the problem solving phase. We present a continuous online learning scheme that uses an "anytime" algorithm to learn continuously while solving problems.

Stuck-at and crosspoint faults in PLA's introduce combinational and sequential redundancies in PLA-based FSM's that affect the testability of these FSM's. We propose a new state assignment algorithm for PLA-based FSM's called EARTH that simultaneously considers area minimization and testability of the resultant PLA's. Our fault model is the single stuck-at and/or single crosspoint fault model. Experimental results show that, on an average, the number of undetectable faults which result due to state assignment by EARTH is about five times less than those generated due to state assignment by NOVA with area overhead 2% more than NOVA.

This paper describes a system which obtains a structural scene description of 3-D objects from range images. The system uses a hierarchical approach to obtain higher level primitives from lower level ones. Instead of a detailed mathematical approach, qualitative reasoning by rule based deduction is used to obtain the scene description. The rule bases are also hierarchical and several special control strategies like rule pruning, windowing (or zoning) and fact inhibition are used to considerably improve the speed of the system. Experimental results and performance of the system on actual range images are presented.