The increasing complexity of embedded and Cyber-Physical Systems (CPS) has accelerated the adoption of heterogeneous multi-core architectures, which combine performance and energy efficiency. However, scheduling dependent tasks on such platforms introduces significant challenges due to strict real-time constraints, high energy consumption, and the NP-hard nature of task mapping. This paper proposes a novel hybrid scheduling framework to jointly optimize energy efficiency and timeliness for Directed Acyclic Graph (DAG) applications. The framework operates in three tiers: first, a Genetic Algorithm (GA) performs a global search to determine near-optimal task-to-core mappings; second, a Dynamic Voltage and Frequency Scaling (DVFS) manager is integrated into the GA’s fitness function to accurately capture energy-performance trade-offs; and third, a Graph Neural Network (GNN) is trained to imitate the GA+DVFS policy, enabling fast and high-quality online scheduling decisions. Experimental results demonstrate that the proposed approach achieves a balanced trade-off between power consumption and deadline satisfaction, while the GNN significantly accelerates scheduling without compromising solution quality. Our GLEAM method reduced energy consumption on average by 49.08% and improved the makespan on average by 27.03% compared to baseline methods.

The rapid growth of Internet of Things (IoT) deployments and the increasing integration of multiple cores on a single chip have made managing power consumption and ensuring thermal safety critical challenges for multicore IoT devices. This paper proposes HAMLET, a heterogeneous adaptive mapping and low-energy task scheduling framework that jointly manages energy consumption, timing constraints, thermal safety, and reliability in multicore IoT platforms through a multi-objective genetic optimization approach. In the offline phase, task-to-core mapping and replication decisions are optimized to minimize peak power and energy consumption while preserving schedulability and reliability targets. Moreover, predictive temperature control is achieved in the runtime phase using a Long Short-Term Memory (LSTM) model, which anticipates core temperature evolution and enables proactive control actions. This approach ensures that tasks are allocated to processing cores to prevent thermal violations while maintaining system-level reliability. Furthermore, DVFS and DPM mechanisms are adaptively applied at runtime based on predicted thermal states to reduce energy consumption and avoid thermal emergencies. Experimental results demonstrate that the proposed method achieves up to 84.39% reduction in peak power and up to 81.98% reduction in energy consumption, while improving schedulability by up to 20.7% compared to state-of-the-art techniques, confirming its effectiveness for energy- and reliability-aware multicore IoT systems.

Fog-cloud task scheduling faces the dual challenge of maintaining critical IoT workloads despite node failures while adhering to strict energy budgets. We present SIREN, a game-theoretic framework that treats fog nodes as strategic players, embedding reliability benefits and DVFS-aware energy costs directly into their payoffs. By searching the joint strategy space with a Memory-Driven Grey Wolf Optimizer (MDGWO), SIREN adapts placements, selective replication, and frequency settings to workload dynamics. Extensive evaluations on the Alibaba 2018 and Google 2011 cluster traces and on a latency-critical healthcare application demonstrate that SIREN converges to near-Nash schedules that minimize energy while maximizing reliability. Results confirm that SIREN delivers (i) 100% task success rates in critical healthcare scenarios, (ii) 2.08×–4.24× lower worst-case energy consumption than leading baselines, and (iii) a 3.9×–5.8× reduction in network usage, establishing a new benchmark for resilient, energy-efficient fog computing.

With the advancement of technology size and the integration of multiple cores on a single chip, the probability of fault occurrence has increased. These faults can be transient or permanent, requiring techniques to manage both types. Hybrid fault tolerance techniques have emerged as effective solutions to handle both types. In this paper, we propose a power-aware hybrid fault tolerance (called Pilot). Our approach utilizes checkpointing with rollback-recovery and primary/backup techniques, tolerating two kinds of faults. Moreover, in real-time embedded systems, power consumption is a critical constraint that must be managed. To do this, we exploit the Thermal Safe Power (TSP) constraint for each processing core. Based on this constraint and the utilization of each core, tasks are mapped and scheduled, while guaranteeing the timing constraints. Our experimental results demonstrate that our proposed methods can meet the reliability target by tolerating the optimal number of fault occurrences in each task while reducing power consumption. Our proposed methods are compared to state-of-the-art techniques in terms of schedulability, power consumption, Quality of Service (QoS), energy consumption, and reliability. The peak power and energy consumption are reduced on average by 34.2% and 15.9%, respectively, the QoS is improved on average to 28.7%, and the schedulability is improved on average to 14.6% while satisfying the system reliability target.

In multicore Internet of Things (IoT) devices, high reliability, low power/energy design, and real-time computing are three important design requirements. The multiple cores in these systems enable us to exploit different fault-tolerance techniques for improving system reliability. However, these techniques impose power/energy and timing overheads on the system. This paper proposes DReaM, a power- and reliability-aware approach that utilizes Deep Reinforcement Learning (DRL) to minimize power consumption in multicore systems while maintaining the desired reliability level and meeting timing constraints. DReaM controls the power consumption by adjusting the voltage and frequency levels for each task and choosing the most suitable fault-tolerant techniques between Primary/Backup (P/B), Triple Modular Redundancy (TMR), and N-Modular Redundancy (NMR). Evaluations using an ARM-based processor and applications from the MiBench benchmark suite were conducted under different fault injection scenarios. The experimental results show that DReaM reduces power consumption on average by 19.86% (up to 64.1%), with improved Quality of Service (QoS) by an average of 11.02% (up to 77%) while maintaining the required system reliability.

Modern vehicles, as a cyber-physical system, consist of hundreds of sensors, and due to the safety-critical nature of vehicles, faults in these sensors can result in failures and potentially catastrophic consequences. The traditional approaches employ redundant components for tolerating faults, which incur costs and overheads. These costs and overheads present barriers to adopting fault-tolerant methods in the automotive industry. To address this issue, we propose a solution that replaces redundant sensors with virtual replicas of Digital Twin (DT) technology. We exploit data of these virtual replicas, available through the Internet of Things (IoT) infrastructure to devise cyber redundancies. We refer to these cyber redundancies as Cyber-Twin-based Redundancies (CTRs). Recognizing that CTRs utilize DT data, does not incur additional physical overhead. We applied our approach to throttle-by-wire technology as a case study and conducted fault injection experiments. Our experiments demonstrate that our proposed approach not only provides cost-effective fault tolerance capability but also enhances the number of nines of reliability on average from 4.33N to 4.35N for the 5G network and 4.74N for the 6G network in the first year when vehicles require more maintenance. For future networks with 7N, 8N, and 9N reliability, this metric improves to 5.38N, 5.88N, and 6.17N, respectively. Compared to traditional approaches, our proposed approach achieves these improvements without incurring additional costs and physical overheads.

This paper presents DIST, a novel distributed reinforcement learning-based (DRL) framework for energyefficient and reliable task scheduling and resource allocation in fog computing, low-latency computing solutions driven by the rapid deployment of IoT devices, and time-sensitive applications. DIST is built based on a novel distributed Q-learning to enable fog nodes to learn an optimal strategy to balance energy consumption, task execution time, and system reliability. The main novelty includes a cooperative Dynamic Voltage and Frequency Scaling-enabled task scheduling policy that dynamically adjusts node energy level to ensure power consumption reduction without sacrificing deadline adherence or reliability. The results demonstrate that DIST reduces energy consumption by up to 52.26%, realizes 38% higher success rates, and reduces task wait times by up to 46.77%, compared with state-of-the-art algorithms.

Fog computing enhances cyber-physical systems (CPS) by processing data closer to the network edge. However, the performance of fog nodes is critical for maintaining system responsiveness and quality of service (QoS). This paper introduces MoTiCPS, a novel task scheduling and resource allocation method built on the Osprey Optimization Algorithm (OOA). MoTiCPS improves task reliability and balances resource use across edge devices, optimizing fog node performance under real-time constraints. Simulation results show that MoTiCPS increases task success rates by 32% and reduces energy consumption by 39%, significantly outperforming benchmark methods. These improvements highlight MoTiCPS's potential to enhance the efficiency and scalability of CPSs in various application domains.

RPL is introduced to conduct path selection in Low-power and Lossy Networks (LLN), including IoT. A routing policy in RPL is governed by its objective function, which corresponds to the requirements of the IoT application, e.g., energy-efficiency, and reliability in terms of Packet Delivery Ratio (PDR). In many applications, it is not possible to connect the nodes to the power outlet. Also, since nodes may be geographically inaccessible, replacing the depleted batteries is infeasible. Hence, harvesters are an admirable replacement for traditional batteries to prevent energy hole problem, and consequently to enhance the lifetime and reliability of IoT networks. Nevertheless, the unstable level of energy absorption in harvesters necessitates developing a routing policy, which could consider harvesting aspects. Furthermore, since the rates of absorption, and consumption are incredibly dynamic in different parts of the network, learning-based techniques could be employed in the routing process to provide energy-efficiency. Accordingly, this paper introduces LANTERN; a learning-based routing policy for improving PDR in energy-harvesting IoT networks. In addition to the rate of energy absorption, and consumption, LANTERN utilizes the remaining energy in its routing policy. In this regard, LANTERN introduces a novel routing metric called Energy Exponential Moving Average (EEMA) to perform its path selection. Based on diversified simulations conducted in Cooja, with prolonging the lifetime of the network by$5.7\times $, and mitigating the probability of energy hole problem, LANTERN improves the PDR by up to 97%, compared to the state-of-the-art. Also, the consumed energy per successfully delivered packet is reduced by 76%.

A major requirement of safety-critical systems is high reliability at low power consumption. Dynamic voltage and frequency (v/f) scaling (DVFS) techniques are widely exploited to reduce power consumption. However, DVFS through downscaling v/f levels has a negative impact on the reliability of the tasks running on the cores, and through upscaling v/f levels has circuitlevel aging effects. To achieve high reliability in multicore safetycritical systems, task replication as a fault-tolerant technique is an established way to deal with the negative effect of downscaling v/f levels, but it may accelerate aging effects due to elevating the on-chip temperatures. In this paper, we propose an aging-aware task replication (called ATLAS) method that solves the problem of satisfying the desired reliability target for a set of periodic hard real-time tasks which are executed on a multicore system. The proposed method satisfies the reliability target of the tasks through updating the required number of replicas for each task at different years. We replicate the tasks through our proposed formulas such that the reliability target is satisfied. However, task replication increases the temperature of the system and accelerates aging. To decelerate aging, we attempt to reduce the temperature while mapping and scheduling the tasks. We have also developed a modified demand bound function (DBF) for our aging-aware task replication method to verify scheduling the realtime tasks. Compared to the existing state-of-the-art techniques, experimental results for safety-critical applications on different configurations of multicore systems demonstrate the efficiency and effectiveness of our proposed method. Experiments show that our proposed method improves schedulability on average by 16.1% and reduces the temperature on average by 7.4°C compared to state-of-the-art methods while meeting the system reliability target.

Due to the real-time requirements in several IoT applications, fog computing has emerged to overcome the long latency and other constraints of cloud computing. Due to the high probability of packet loss, energy limitation of IoT devices, and the external disturbances that may frequently occur on the fog infrastructure, the timing constraints of real-time tasks may be compromised. Therefore, the reliability of executing real-time tasks has always been a significant challenge in fog computing. In addition to the correct execution of the tasks, it is also important to execute them before their deadlines according to their real-time classification. State-of-the-art methods generally focus on the delay or functionality of tasks in fog computing systems. However, those methods do not widely focus on the reliability of tasks with real-time constraints in dynamic environments. In this article, a novel primary backup task assignment strategy based on machine learning (ReLIEF) is proposed to improve the reliability of fog-based IoT systems. To identify suitable nodes for the execution of the primary and backup tasks, ReLIEF employs a reinforcement learning (RL) approach, which has an outstanding performance in dynamic environments by establishing a balance between communication delay and workload on each fog device. Based on the simulations, our newly proposed technique has been able to reduce the amount of task dropping rate by up to 84% against the state of the art. Moreover, it is capable of balancing the workload distribution while increasing the reliability of the system by nearly 72% compared with its counterparts.

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic voltage and frequency scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

In addition to meeting the real-time constraint, power/energy efficiency and high reliability are two vital objectives for real-time embedded systems. Recently, heterogeneous multicore systems have been considered an appropriate solution for achieving joint power/energy efficiency and high reliability. However, power/energy and reliability are two conflict requirements due to the inherent redundancy of fault-tolerance techniques. Also, because of the heterogeneity of the system, the execution of the tasks, especially real-time tasks, in the heterogeneous system is more complicated than the homogeneous system. The proposed method in this paper employs a passive primary/backup technique to preserve the reliability requirement of the system at a satisfactory level and reduces power/energy consumption in heterogeneous multicore systems by considering real-time and peak power constraints. The proposed method attempts to map the primary and backup tasks in a mixed manner to benefit from the execution of the tasks in different core types and schedules the backup tasks after finishing the primary tasks to remove the overlap between the execution of the primary and backup tasks. Compared to the existing state-of-the-art methods, experimental results demonstrate our proposed method's power efficiency and effectiveness in terms of schedulability.

Mobile portable embedded devices are becoming an integral part of our daily activities in the vision of Internet of Things (IoT). Nevertheless, due to lack of mobility support in the IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized for multihop IoT infrastructures, providing reliable communications in terms of packet delivery ratio (PDR) in mobile IoT applications has become significantly challenging. While several studies tried to enhance the adaptability of RPL to network dynamics, their utilized routing metrics have prevented them from establishing long-lasting reliable paths. Furthermore, the stochastic parent replacement policy in the standard version of RPL has intensified this challenge. Aside from this, due to the existing tradeoff between reliability and power efficiency, most of the existing approaches have only concentrated on one of these concerns without paying attention to the other one. To address these issues, this article introduces ARMOR, a routing mechanism built upon RPL, which employs a novel mobility-aware routing metric, i.e., time to reside (TTR), and a corresponding parent replacement policy. According to the motion characteristics of the mobile objects, TTR provides an estimation of how long the nodes will be in the transmission range of each other. This enables ARMOR to select nodes, which provide longer connection period and consequently higher reliability. In comparison with the state of the art, while keeping the power consumption constant, ARMOR significantly improves the amount of PDR in the network by up to$2.5\times $, while it enhances the reliability against the original version of this protocol by up to$4.2\times $.

Mixed-criticality (MC) systems have recently been devised to address the requirements of real-time systems in industrial applications, where the system runs tasks with different criticality levels on a single platform. In some workloads, a high-critically task might overrun and overload the system, or a fault can occur during the execution. However, these systems must be fault tolerant and guarantee the correct execution of all high-criticality (HC) tasks by their deadlines to avoid catastrophic consequences, in any situation. Furthermore, in these MC systems, the peak-power consumption of the system may increase, especially in an overload situation and exceed the processor thermal design power (TDP) constraint. This may cause generating heat beyond the cooling capacity, resulting the system stop to avoid excessive heat and halting the processor. In this article, we propose a technique for dependent dual-criticality tasks in fault-tolerant multicore MC systems to manage peak-power consumption and temperature. The technique develops a tree of possible task mapping and scheduling at design-time to cover all possible scenarios and reduce the low-criticality task drop rate in the HC mode. At the runtime, the system exploits the tree to select a proper schedule according to fault occurrences and criticality mode changes. Experimental results show that the average task schedulability is 74.14% on average for the proposed method, while the peak-power consumption and maximum temperature are improved by 16.65% and 14.9 °C on average, respectively, compared to a recent work. In addition, for a real-life application, our method reduces the peak power and maximum temperature by up to 20.06% and 5 °C, respectively, compared to a state-of-the-art approach.

An increasing trend for reducing cost, space, and weight leads to modern embedded systems that execute multiple tasks with different criticality levels on a common hardware platform while guaranteeing a safe operation. In such mixed-criticality (MC) systems, multiple worst case execution times (WCETs) are defined for each task, corresponding to the system operation mode to improve the MC system’s timing behavior at runtime. Determining the appropriate WCETs for lower criticality (LC) modes is nontrivial. On the one hand, considering a very low WCET for tasks can improve the processor utilization by scheduling more tasks in that mode, on the other hand, using a larger WCET ensures that the mode switches (which causes by task overrunning) are minimized, thereby improving the quality of service for all tasks, albeit at the cost of processor utilization. Hitherto, no analytical solutions are proposed to determine WCETs in LC modes. In this regard, we propose a scheme to determine WCETs by the Chebyshev theorem, to make a tradeoff between the number of scheduled tasks at design-time and the number of dropped low-criticality tasks at runtime as a result of frequent mode switches. To have a tight bound of execution times and mode switching probability, we also propose a distribution analytics-based scheme, in which the mode switching probability is obtained based on the cumulative distribution function. Our experimental results show that our scheme improves the utilization of state-of-the-art MC systems by up to 72.27%, while maintaining 24.28% mode switching probability in the worst case scenario. Besides, the results of running embedded real-time benchmarks on a real platform show that the distribution-based scheme can improve the utilization by 7.30% while bounding the mode switching probability by 4.85% more, compared to the Chebyshev-based scheme.

Reliability of routing mechanisms in wireless networks is typically measured with Packet Delivery Ratio (PDR). Basically, PDR is reported with an optimistic assumption that the topology is fully constructed, and the nodes have started their packet transmission. This is despite the fact that prior to being able to transmit packets, nodes must first join the network, and then try to keep connected as much as possible. This is a key factor in the overall reliability provided by the routing protocols, especially in mobile IoT applications, where disconnections occur frequently. Nevertheless, there is a lack of appropriate metrics, which could evaluate the routing mechanisms from this perspective. Accordingly, this paper introduces attachability; a new metric for evaluating the capability of routing protocols in assisting the mobile or stationary nodes in joining, and maintaining their connections to the network. Our newly proposed metric is calculated via Markov chain analysis along with the sample frequency-based estimating technique. To evaluate attachability, we have simulated a mobile IoT infrastructure, and conducted a comprehensive set of experiments on different versions of the IPv6 Routing Protocol for Low-power and lossy networks (RPL). Based on our observations, attachability is significantly dependent on the employed metrics and path selection policies in the routing mechanisms. Among the three different versions of RPL, including the original version (ORPL), which is standardized for stationary IoT applications, and two mobility-aware versions, i.e., MARPL, and OMARPL, OMARPL showed up to 42%, and 10% of improvement in terms of attachability against ORPL, and MARPL, respectively.

Increasing the number of cores integrated on a single chip offers a great potential for the implementation of fault-tolerant techniques to achieve high reliability in real-time embedded systems. Checkpointing with rollback-recovery is a well-established technique to tolerate transient faults in multicore platforms. To consider the worst-case fault occurrence scenario, checkpointing technique requires to re-execute some parts of the tasks, and that might lead to simultaneous execution of task parts with high power consumptions, which eventually might result in a peak power increase beyond the thermal design power (TDP). Exceeding TDP can elevate on-chip temperatures beyond safe limits, and thereby triggering countermeasures that throttle down the voltage and frequency levels or power gate the cores. Such countermeasures might lead to violating task deadlines and degrading the system's reliability. To avoid such severe scenarios, it is inevitable to consider the impact of applying fault-tolerant techniques on the power consumption and prevent violating the power constraint of the chip, i.e., TDP. This paper presents for the first time, a peak-power-aware checkpointing (PPAC) technique that tolerates a given number of faults,k, while at the same time meets the power constraint in hard real-time embedded systems. To do this, our proposed technique (PPAC) adjusts the timing of the checkpoints, which have lower power consumption than the tasks to the execution time points that have power spikes beyond TDP. Moreover, PPAC exploits the available slack times on the cores to delay the execution of some tasks to avoid the remaining power spikes beyond TDP, which could not be mitigated by solely adjusting checkpoints. To evaluate our technique, we extend the state-of-the-art system-level simulator, gem5, with the state-of-the-art checkpointing module in Linux. Our experimental results show that our proposed technique is able to tolerate a given number of faults without exceeding the timing and power constraints in hard real-time embedded systems. The resulting peak power reduction achieved by our technique compared to state-of-the-art techniques is an average of 23%. Moreover, our technique employs the Dynamic Power Management (DPM) during the slack times resulting at runtime in the case of fault-free scenarios, which provides energy savings with an average of 17.28% and up to 61.1%.

Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Compared with SRAM, NVMs have lower leakage power and higher density, but the read and write latencies of the NVMs are higher than the SRAM. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to achieve further energy saving. This paper proposes MASTER, a task mapping, task scheduling, and dynamic SPM allocation scheme that efficiently utilizes the hybrid SPM space. To this end, we model the hybrid SPM allocation on a multi-core system with integer linear programming formulation to minimize the energy consumption of the memory subsystem. Experimental results show that MASTER improves the energy saving of the memory subsystem by up to 34 percent compared to EADA, which is a heuristic dynamic data allocation algorithm for multi-core systems with hybrid SPM.

In Mixed-Criticality (MC) systems, there are often multiple Worst-Case Execution Times (WCETs) for the same task, corresponding to system operation mode. Determining the appropriate WCETs for lower criticality modes is non-trivial; while on the one hand, a low WCET for a mode can improve the processor utilization in that mode, on the other hand, using a larger WCET ensures that the mode switches are minimized, thereby maximizing the quality-of-service for all tasks, albeit at the cost of processor utilization. Although there are many studies to determine WCET in the highest criticality mode, no analytical solutions are proposed to determine WCETs in other lower criticality modes. In this regard, we propose a scheme to determine WCETs by Chebyshev theorem to make a trade-off between the number of scheduled tasks at design-time and the number of dropped low-criticality tasks at runtime as a result of frequent mode switches. Our experimental results show that our scheme improves the utilization of state-of-the-art MC systems by up to 85.29%, while maintaining 9.11% mode switching probability in the worst-case scenario.

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) in the structure of the RPL routing protocol. Meanwhile, the majority of the existing OFs mainly perform the parent selection based on the gathered information from the routing layer. Nevertheless, based on our investigations, there exists a series of transmission operations in the medium access control (MAC) layer, which significantly affects the energy consumption in IoT devices. Therefore, in this article, we propose ELITE, an energy-efficient cross-layer OF, which introduces a novel routing metric, called strobe per packet ratio (SPR). SPR indicates the number of transmitted strobes per packet due to radio duty cycling (RDC) policies in the MAC layer. This newly defined metric, which has been designed to be coupled with asynchronous MAC protocols, could be differentiated node by node and based on the existing relative phase shift between the communicating nodes. In this regard, the ELITE tries to select a path, which imposes less number of strobe transmissions to its nodes. According to the evaluation results, while ELITE could reduce the average amount of required strobes per packet by up to 25%, it can significantly improve the average amount of consumed energy in an IoT node by up to 39% compared to its counterpart OFs.

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed correctly. In this article, we present a predictable fully non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. Since write buffers usually help with the performance problem but they make WCET estimation more complex, we also present a new low-overhead software-based optimization technique that makes the proposed system more predictable without imposing considerable overhead. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33 and 47 percent, respectively.

The energy efficiency of emerging nonvolatile processors equipped with FRAM-SRAM memory makes them a promising solution for energy harvesting systems. To enable correct functionality and forward progress with an unreliable power supply, the system must accumulate sufficient energy in the capacitor to execute tasks atomically, even in the worst case scenario. Due to the large gap between the average and worst case energy consumption of tasks, state-of-the-art approaches like eM-map require a large capacitor to execute tasks on the SRAM. However, the size, cost, and charging time of the capacitor are major concerns in the energy harvesting systems. In this article, we proposed CHANCE, a capacitor charging management scheme that improves the capacitor size and average response time of an energy harvesting system. CHANCE analyses the energy consumption of tasks to set an appropriate capacitor size to make a balance between capacitor charging time and failure rate for each task. The results show that CHANCE improves the response time of state-of-the-art approaches up to 68% with a five times smaller capacitor.

In modern multicore mixed-criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multicore MC systems. In this regard, we propose an online peak power and thermal management heuristic for multicore MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster dynamic voltage and frequency scaling (DVFS). Specifically, our approach examines multiple tasks ahead to determine the most appropriate one for slack assignment, that has the most impact on the system peak power and temperature. However, changing the frequency and selecting a proper task for slack assignment and a proper core for task remapping at runtime can be time-consuming and may cause deadline violation which is not admissible for high-criticality tasks. Therefore, we analyze and then optimize our runtime scheduler and evaluate it for various platforms. The proposed approach is experimentally validated on the ODROID-XU3 (DVFS-enabled heterogeneous multicore platform) with various embedded real-time benchmarks. Results show that our heuristic achieves up to 5.25% reduction in system peak power and 20.33% reduction in maximum temperature compared to an existing method while meeting deadline constraints in different criticality modes.

Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability- and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint (as a metric for temperature measurement) that is updated according to the number and position of the active cores on the chip. READY, first, attempts to meet the reliability target of the system by improving the reliability of each task. Then, it performs the mapping and scheduling of the tasks on cores of different islands, so that the peak power and timing constraints are met. The simulation results illustrate that while READY guarantees the timing constraints and meets reliability targets, it improves the peak-power-aware system schedulability (chip performance) by 23.77% (up to 40.69%).

Two main objectives in designing real-time embedded systems are high reliability and low power consumption. Hardware replication (e.g., standby-sparing) can provide high reliability while keeping the power consumption under control. In this paper, we consider a standby-sparing system where the main tasks on primary cores are scheduled by our proposed peak-power-aware earliest-deadline-first policy while the backup tasks on spare cores are scheduled by our proposed peak-power-aware earliest-deadline-late policy to meet the chip thermal design power (TDP) constraint. These policies provide the best opportunity to shift the task executions as much as possible to minimize execution overlaps between main and backup tasks that consume high power consumption. Since TDP is the maximum amount of power generated by a chip that the cooling component is designed to dissipate under any workload, the total power consumption should not be higher than the TDP constraint. When a task finishes successfully a larger portion of its corresponding copy task can be canceled, resulting in a significant amount of peak/average power reduction. To achieve further peak/average power reduction, we use dynamic voltage and frequency scaling and dynamic power management (DPM). The main reason of using DPM is that, once the first copy of each task has finished successfully, its corresponding copy task is terminated, and if there is no more task for execution, the core goes to a low-power mode. We evaluated our scheme under various system configurations. Experiments show that our scheme provides up to 47.6% (on average by 28.2%) peak power reduction compared to four state-of-the-art techniques.

Analysis of reliability, power, and performance at hardware and software levels due to heterogeneity is a crucial requirement for heterogeneous multicore embedded systems. Escalating power densities have led to thermal issues for heterogeneous multicore embedded systems. This paper proposes a peak-power-aware reliability management scheme to meet power constraints through distributing power density on the whole chip such that reliability targets are satisfied. In this paper, we consider peak power consumption as a system-level power constraint to prevent system failure. To balance the power consumption, we also employ a Dynamic Frequency Scaling (DFS) method to further reduce peak power consumption and satisfy thermal constraints on the chip. We illustrate the benefits of our scheme by comparing it with state-of-the-art schemes, resulting in average in 26.5 percent less peak power consumption (up to 54.3 percent).

In this work, we address peak power and maximum temperature in multi-core Mixed-Criticality (MC) systems. In these systems, a rise in peak power consumption may generate more heat beyond the cooling capacity. Additionally, the reliability and timeliness of MC systems may be affected due to excessive temperature. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines multiple tasks ahead to determine the most appropriate one for slack assignment instead of just one task as in the literature. The selection is based on the impact of the tasks on peak power and temperature of the system. The DVFS is then applied to that task to reduce the system peak power and maximum temperature. Further, a re-mapping technique is proposed to further improve the results. Our experimental results show that our heuristic achieves up to 18.2% reduction in system peak power consumption and 8.1% reduction in maximum temperature compared to an existing method. The inherent energy consumption is also reduced by up to 50%.

Multicore platforms provide a great opportunity for implementation of fault-tolerance techniques to achieve high reliability in real-time embedded systems. Passive redundancy is well-suited for multicore platforms and a well-established technique to tolerate transient and permanent faults. However, it incurs significant power overheads, which go wasted in fault-free execution scenarios. Meanwhile, due to the Thermal Design Power (TDP) constraint, in some cases, it is not feasible to simultaneously power on all cores on a multicore platform. Since TDP is the maximum sustainable power that a chip can consume, violating TDP makes some cores automatically restart or significantly reduce their performance to prevent a permanent damage. This may affect timeliness of the system, and hence, designers face a challenge in deciding how to use multicore platforms in real-time embedded systems. In this paper, at first, we study how the use of passive redundancy (especially for Triple Modular redundancy) can violate TDP on multicore platforms. Then, we propose a scheme for scheduling real-time tasks in multicore systems to conquer the peak power problem in NMR systems. This is because in multicore embedded systems an efficient solution for meeting the TDP constraint is reducing the peak power consumption. The proposed scheme tries to remove overlaps of the peak power of concurrently executing tasks to keep the maximum power consumption below the chip TDP. In the proposed scheme, we devised a policy called PPA-LTF to manage peak power consumption. This policy prevents tasks execution that consume higher power according to the tasks’ power traces. Our experimental results show that our scheme provides up to 50 percent (on average by 39 percent) peak power reduction compared to state-of-the-art schemes.

Existing memory approximation techniques focus on employing approximations at an individual level of the memory hierarchy (e.g., cache, scratchpad, or main memory). However, to exploit the full potential of approximations, there is a need to manage different approximation knobs across the complete memory hierarchy. Towards this, we model a system including STT-RAM scratchpad and PCM main memory with different approximation knobs (e.g., read/write pulse magnitude/duration) in order to synergistically trade data accuracy for both STT-RAM access delay and PCM lifetime by means of an integer linear programming (ILP) problem at design-time. Furthermore, a runtime algorithm is proposed to adaptively tune the approximation knobs of both STT-RAM and PCM to obtain high energy savings while keeping error-per-second within acceptable ranges across the complete memory hierarchy. We evaluated our proposed technique (i.e., AdAM) in a baseline system consisting of 1-2MB STT-RAM scratchpad and 0.5-1GB PCM main memory. The experimental results demonstrate that AdAM improves the execution time and the lifetime of memory by up to 38.7% and 1.6X, respectively.

Multi-level cell phase change memory (MLC-PCM), because of its very low leakage power and high density, is promising for embedded systems. Furthermore, for applications with inherent low sensitivity to errors, approximate write operations can be exploited in MLC-PCM to improve endurance and performance. However, data that reside in the approximate MLC-PCM for a rather long time without refreshing are prone to soft errors due to resistance drift phenomenon, while even for an application with inherent low sensitivity to errors, a high soft error rate can degrade its Quality of Result (QoR). The architecture-level approaches to decrease the drift effect incur considerable power overhead (about 100%), which is a prominent issue in embedded systems, and are dependent on the number of logic levels stored in the PCM cell (e.g., most of them are designed for 4LC-PCM). This article, taking a different approach, proposes a drift-aware frequency and voltage management to alleviate the drift-based soft-error rate. To this end, first we characterize the application data based on the degree of being exposed to the drift to identify the drift-prone application data. Then we assign the execution frequency and voltage to different regions of the application considering the drift. This frequency assignment speeds up the application regions wherein the drift-prone data are accessed to shorten the lifetime of the drift-prone data, thereby decreasing the soft error rate. An integer linear programming model implements our proposed Dynamic Voltage Frequency Scaling (DVFS). Also, the proposed approach is independent of the number of levels of PCM cells and can be applied to any MLC-PCM system. To evaluate the approach, the approximate MLC-PCM is simulated using empirical models and is integrated into a full-system simulator as data memory. The experimental results show that, by exploiting the approach, QoR is in the acceptable range, while its power overhead is about 84% (on average) less than that of the architecture-level approach.

Mixed-criticality systems are introduced due to industrial interest to integrate different types of functionalities with varying importance into a common and shared computing platform. Low-energy consumption is vital in mixed-criticality systems due to their ever-increasing computation requirements and the fact that they are mostly supplied with batteries. We propose a novel reliability-aware energy management approach and three techniques, Monotonous-DVFS, Stretch, and Combined Monotonous-DVFS/Stretch in which energy management targets non-safety-critical functionalities. The Monotonous-DVFS technique lowers energy consumption by monotonously distributing slack times between low-criticality tasks while the Stretch technique lowers the energy consumption of mixed-criticality systems with the cost of degraded service in low-criticality tasks. Our Stretch technique extends both execution time and period of tasks while preserving their utilization. This leads to degrading the tasks’ service level due to a period extension that is exploited by Stretch for energy management. Experiments show that Combined Monotonous-DVFS/Stretch provides around 25 percent energy savings with only 5 percent service level degradation in low-criticality tasks in a heavily utilized system. The energy savings can be increased to around 56 percent with the cost of degrading low-criticality tasks’ service level to the minimum level, while preserving the original reliability of the system.

Energy consumption is one of the prominent design constraints of multi-core embedded systems. Since the memory subsystem is responsible for a considerable portion of energy consumption of embedded systems, Non-Volatile Memories (NVMs) have been proposed as a candidate for replacing conventional memories such as SRAM and DRAM. The advantages of NVMs compared to conventional memories are that they consume less leakage power and provide higher density. However, these memories suffer from increased overhead of write operations and limited lifetime. In order to address these issues, researchers have proposed NVM-aware memory management techniques that consider the characteristics of the memories of the system when deciding on the placement of the application data. In systems equipped with memory management unit (MMU), the application data is partitioned into pages during the compile phase and the data is managed at page level during the runtime phase. In this paper we present an NVM-aware data partitioning and mapping technique for multi-core embedded systems equipped with MMU that specifies the placement of the application data based on access pattern of the data and characteristics of the memories. The experimental results show that the proposed technique improves the energy consumption of the system by 28.10 percent on average.

Compile-time optimizations play an important role in the efficient design of real-time embedded systems. Usually, compile-time optimizations are designed to reduce average-case execution time (ACET). While ACET is a main concern in high-performance computing systems, in real-time embedded systems, concerns are different and worst-case execution time (WCET) is much more important than ACET. Therefore, WCET reduction is more desirable than ACET reduction in many real-time embedded systems. In this article, we propose a compile-time optimization method aimed at reducing WCET in real-time embedded systems. In the proposed method, based on the predicated execution capability of embedded processors, program code blocks that are in the worst-case paths of the program are merged to increase instruction-level parallelism and opportunity for WCET reduction. The use of predicated execution enables merging code blocks from different worst-case paths that can be very effective in WCET reduction. The experimental results show that the proposed method can reduce WCET by up to 45% as compared to previous compile-time block formation methods. It is noteworthy that compared to previous works, while the proposed method usually achieves more WCET reduction, it has considerably less negative impact on ACET and code size.

This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multi-core systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered:i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving,ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energy-management technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29 percent energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work.

Checkpointing with rollback recovery is a well-established technique to tolerate transient faults. However, it incurs significant time and energy overheads, which go wasted in fault-free execution states and may not even be feasible in hard real-time systems. This paper presents a low-overhead two-state checkpointing (TsCp) scheme for fault-tolerant hard real-time systems. It differentiates between the fault-free and faulty execution states and leverages two types of checkpoint intervals for these two different states. The first type is nonuniform intervals that are used while no fault has occurred. These intervals are determined based on postponing checkpoint insertions in fault-free states, with the aim of decreasing the number of checkpoint insertions. The second type is uniform intervals that are used from the time when the first fault occurs. They are determined so as to minimize execution time for faulty states, leaving more time available for energy management in fault-free states. Experimental evaluation on an embedded processor (LEON3) and an emerging nonvolatile memory technology (ReRAM) illustrates that TsCp significantly reduces the number of checkpoints (62% on average) compared with previous works, while preserving fault tolerance. This results in 14% and 13% reduced execution time and energy consumption, respectively. Furthermore, we combine TsCp with dynamic voltage scaling (DVS) and achieve up to 26% (21% on average) energy saving compared with the state-of-the-art techniques.

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling (DRVS) considering process variations in hardware, and diversities in software vulnerability and execution time properties. Experiments show that DRVS system provides significant reliability improvements while providing up to 60% reduced power consumption compared to state-of-the-art techniques.

Allocating the scratchpad memory (SPM) space to tasks is a challenging problem in real-time multicore embedded systems that use shared SPM. Proper SPM space allocation is important, as it considerably influences the application worst-case execution time (WCET), which is of great importance in real-time applications. To address this problem, in this article we present a dynamic SPM reuse scheme, where SPM space can be reused by other tasks during runtime without requiring any static SPM partitioning. Although the proposed scheme is applied dynamically at runtime, the required decision making is fairly complex and hence cannot be performed at runtime. We have developed techniques to perform the decision making offline at design time in the form of optimization problems combined with task scheduling/mapping. The proposed work is unlike previous works that either exploit static schemes for SPM space allocation or perform task scheduling/mapping and SPM space allocation incoherently. The experimental results show that our dynamic SPM reuse scheme can reduce WCET by up to 55% as compared to recent previous works on SPM allocation in real-time multicore embedded systems.

In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection.

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this paper is an online energy-management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time-redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time-redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumption.

The interaction between fault tolerance and energy consumption is an interesting avenue in the realm of designing embedded systems. In this paper, a scheme for reducing energy consumption in conventional standby-sparing systems is introduced. In the proposed method, the primary unit exploits dynamic voltage scaling (DVS) and dynamic power management (DPM) is employed for the spare unit. The framework which is used in the primary unit is composed of a feedback system to follow up workload along with a three-layer yet light-weight energy manager which guarantees hard real-time constraints of the system. Moreover, an optimal approach (but not practical) as a margin for the minimum energy consumption of this system is presented and the capability of other methods in reducing energy consumption is compared. Simulation results show an improvement in energy saving as compared with previous works and also show that the proposed method is near optimal for task sets with different dynamic workloads.

Low energy consumption and fault tolerance are often key objectives in the design of real-time embedded systems. However, these objectives are at odds, and there is a trade-off between them. Real-time systems usually use system level energy reduction methods, i.e., dynamic voltage scaling (DVS) and dynamic power management (DPM). Also hard real-time systems often use replication to achieve fault tolerance. In this paper, we investigate the impact of system level energy reduction methods on both the reliability and energy consumption of hard real-time systems which use replication for fault tolerance. In this analysis, we have considered four various existing energy management methods: 1) Classic DPM, 2) Classic DVS, 3) Postponement method: a variation of DPM which is only applicable to replicated systems, and 4) Hybrid method: a combination of Postponement and DVS. Based on the comparative study, we have provided guidelines so that a designer can decide which energy management method is more suitable for a given application. For example, we have shown that when reliability is the main concern, the postponement method is the most preferable. However, when the energy consumption is the primary concern, the hybrid method may be more appropriate.

A distributed embedded system consists of different processing elements (PEs) communicating via communication links. PEs have various power characteristics and in turn, have different thermal profiles. With new technologies, processor power density is dramatically increased which results in high temperature. This alarming trend underscores the importance of temperature management methods in system design. The majority of proposed techniques to address thermal issues, impose severe penalties on performance and reliability. We present Schedule Swapping, a technique for reducing peak temperature in distributed embedded systems while satisfying real-time constraints. Contrary to many other approaches, our proposed technique does not use slack time for reducing power dissipation but leaves it to be used by recovery mechanisms (rollback re-execution). The more slack time, the more the number of possible recoveries and the more reliability. We also introduce a simple yet effective scheme to ensure that all the deadlines will be met if our technique is used. This scheme also determines the order in which tasks should transmit their data in Schedule Swapping. Our experimental results show up to 18.1°C reduction in peak temperature. On average, Schedule Swapping achieves the peak temperature reduction of 11.13°C.

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time embedded systems. Dynamic Voltage Scaling (DVS) is known as one of the most effective low energy techniques for real-time systems. It has been observed that the use of control-theoretic methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using feedback control theory. Our proposed feedback-based DVS method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy consumption while guaranteeing hard real-time requirements in the presence of unpredictable workload fluctuations and faults. In the proposed method, the available slack-time is exploited by a feedback-based DVS at runtime to reduce the energy consumption. Furthermore, some slack-time is reserved for re-execution in case of faults. Simulation results show that, as compared with traditional DVS methods without fault-tolerance, our proposed approach not only significantly reduces energy consumption, but also it satisfies hard real-time constraints in the presence of faults. The transition overhead (both time and energy), caused by changing the system supply voltage, are also taken into account in our simulation experiments.

Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the above-mentioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to side channel attacks) than the existing logic circuits are achieved. This paper also presents an analytical proof about how sub-threshold charge recovery circuits can meet these characterizations. we have also confirmed our analytical discussions by examining our technique for full adder, and 8 × 8 carry-save multiplier in different frequencies, supply voltages, and CMOS technologies. Detailed SPICE simulations show significant improvements as compared to its existing counterparts in all simulated frequencies and supply voltages.

High reliability against noise, high performance, and low energy consumption are key objectives in the design of on-chip networks. Recently some researchers have considered the impact of various error-control schemes on these objectives and on the tradeoff between them. In all these works performance and reliability are measured separately. However, we will argue in this paper that the use of error-control schemes in on-chip networks results indegradable systems, hence, performance and reliability must be measured jointly using a unified measure, i.e.,performability. Based on the traditional concept of performability, we provide a definition for the ¿Interconnect Performability¿. Analytical models are developed for interconnect performability and expected energy consumption. A detailed comparative analysis of the error-control schemes using the performability analytical models and SPICE simulations is provided taking into consideration voltage swing variations (used to reduce interconnect energy consumption) and variations in wire length. Furthermore, the impact of noise power and time constraint on the effectiveness of error-control schemes are analyzed.

This paper presents a fault tolerant and energy efficient write-back set-associative cache, which has a heterogeneous structure. The cache architecture is based on partitioning the ways of each set into two different parts. In each set, one cache way uses SEC-DED code and maintains dirty blocks while the other ways employ parity bit and keep clean blocks. To evaluate the set-associative cache, SIMPLESCALAR tool and CACTI analytical model are used. The experimental results show that as the feature size decreases and the associativity increases, the energy saving of the proposed cache increases. The experimental results express that for an 8-way set-associative cache in 32 nm, about 7% area and 2%-17% energy consumption are saved. These figures are achieved by keeping the reliability in the same level of the conventional SEC-DED protected cache.

In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively.

This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09-SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering tradeoff between reliability and power consumption, an optimum fault-tolerant technique is assigned to each part to design the micro-FT-UART. This UART corrects all single-bit errors and on average 24% of multiple-bit errors with about 81% power consumption overhead and 152% area overhead.

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques.

This paper presents a hardware control-flow checking scheme for RISC processor-based systems. This scheme combines two error detection mechanisms to provide high coverage. The first mechanism uses parity bits to detect faults occurring in the opcodes and in the target addresses of branch instructions which lead to erroneous branches. The second mechanism uses signature monitoring to detect errors occurring in the sequential instructions. The scheme is implemented using a watchdog processor for an VHDL model of the LEON2 processor. About 31800 simulation faults were injected into the LEON2 processor. The results show that the error detection coverage is about 99.5% with average detection latency of 7 cycles. The performance loss of presented scheme is about 8.4%.

Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we present a low power error detection mechanism for the division operation in FPUs. In this technique the FPU multiplier circuitry is modified so that it can be used to detect the errors that may happen in the divider circuitry. The experimental results show that while the proposed technique can detect almost all the errors in the division circuitry, its power-delay-product (PDP) is about 23% lower than that of the traditional error detection techniques.

The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles.

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch is also compared with other SEU-tolerant latches.

Improving performance, reducing energy consumption and enhancing reliability are three important objectives for embedded computing systems design. In this paper, we study the joint impact of cache size selection on these three objectives. For this purpose, we conduct extensive fault injection experiments on five benchmark examples using a cycle-accurate processor simulator. Performance and reliability are analyzed using the performability metric. Overall, our experiments demonstrate the importance of a careful cache size selection when designing energy-efficient and reliable systems. Furthermore, the experimental results show the existence of optimal or Pareto-optimal cache size selection to optimize the three design objectives

Recently, the tradeoff between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on-time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack-time to increase the fault-tolerance by performing recovery executions, DVS exploits slack-time to save energy. Therefore, we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the use of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance [tolerance to single event upsets (SEUs)] and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e., the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone.

Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techniques based on time-redundancy. In this paper we analyze the usage of information redundancy in DVS-enabled systems with the aim of improving both the system tolerance to transient faults as well as the energy consumption. We demonstrate through a case study that it is possible to achieve both higher fault-tolerance and less energy using a combination of information and time redundancy when compared with using time redundancy alone. This even holds despite the impact of the information redundancy hardware overhead and its associated switching activities

The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.

This paper presents a method for the fast emulation of switch-level circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. Unlike the abstraction methods, the method presented in this paper can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the rest of the circuit is emulated at the gate-level.

This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest parts of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Cooperation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject faults at different levels of abstraction. The experimental results show that this approach can significantly reduce the time needed for executing fault injection campaigns.

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstream file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits. The results show that between 33 to 45 percent of the SEUs injected to the FPGA device have propagated to the output terminals of the device.

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults on some important observation points have been presented. In this study, recovered errors are distinguished from those that affected the system behavior. The errors that lead to wrong results are separated from those that do not affect the correct results.