We present an end-to-end design of a built-in self-test (BIST) and BIST-based diagnosis infrastructure for 3-D-stacked integrated circuits (ICs) that facilitates the use of BIST at multiple stages of 3-D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both prebond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. A framework for fault diagnosis using the BIST infrastructure for 3-D-stacked ICs is also proposed. We present results on synthetic stacks created from ITC'99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. We also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

No Trouble Found (NTF) has been discussed for several years [1]. An NTF occurs when a device fails at the board/system level and that failure cannot be confirm by the component supplier. There are several explanations for why NTFs occur, including: device complexity; inability to create system level hardware/software transactions which uncover hard to find defects; different environments during testing (power, thermal, noise). More recently a new concept, No Fault Found (NFF), has emerged. A NFF represents a defect which cannot be detected by any known means so far. The premise is that at some point the defect will be exposed - most likely at a customer site when the device is in a system. Given that we looking for a defect that we know nothing about and are theoretically undetectable it will be interesting to see what the panel has to say about the nature of these defects and how we intend to find them.

Increased functional density with shrinking technology could result in escalating noise-induced failures in the field. Further, the low correlation between system level functional test and production test is making it difficult to better screen parts that would fail in the field due to noise. To address these issues, in this paper we present a light-weight fully digital on-chip distributed sensor network to continuously monitor the noise profile and generate a trace for diagnosis of any noise-induced failure at silicon validation, structural test, and system test phases of SoCs. The sensors capture noise at a fine granularity and store the SoC's critical status bits. The sensor network has been designed in 28/32nm standard cell library and its performance is demonstrated in the physical design of Open SPARCT1 multicore processor SoC

We present an end-to-end design of a built-in self-test (BIST) infrastructure for 3D-stacked ICs that facilitates the use of BIST at multiple stages of 3D integration. The proposed BIST design is distributed, reusable, and reconfigurable, hence it is attractive for both pre-bond and post-bond testing. We also provide support for translating a static BIST schedule into a set of BIST control instructions. The BIST design is validated using detailed simulations of the various operating modes. We present results on synthetic stacks created from ITC'99 and Open-Core benchmark circuits and assess the impact of inserting BIST in these designs in terms of area, timing, and power overhead. Results show that the overhead due to BIST is negligible. We also formulate a test-scheduling problem that aims at minimizing test time under BIST-resource and power constraints, and use two algorithms based on bin packing for solving the problem.

As technology and voltage scale, both intrinsic and extrinsic Vmin failures can occur at a significant rate. These failures can impact yield and reliability. We propose a novel guardband and advanced outlier limits (AOL) methodology to protect against intrinsic and extrinsic Vmin failures. This paper will demonstrate the impact of aging, RTN and HKMG process variation on Vmin. The data will be used to establish guardbands and AOL to minimize failures during testing and in the field.

2.5-D integration is emerging as the precursor to stacked 3-D ICs. Since the silicon interposer and micro-bumps in 2.5-D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 standard. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay defects in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. The proposed test technique is fully compatible with the IEEE 1149.1 architecture and can be controlled by the test-access port controller. We present HSPICE and ModelSim simulation results to demonstrate the effectiveness of fault detection. Simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach. We also present synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 standard. Synthesis results show that the cost of implementation of the architecture is negligible.

2.5D integration is emerging as a precursor to stacked 3D ICs. Since the silicon interposer and micro-bumps in 2.5D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 Std. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay fault in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. HSPICE simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach.

Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the “known good die” problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future.

3D-stacked ICs that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleaness of silicon dies, rendering prior TSV redundancy solutions less effective. To resolve this problem, we present a novel TSV repair framework, including a hardware architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, and the corresponding repair algorithm. By doing so, the manufacturing yield for 3D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems?

FALCON (FAst fauLt COverage estimatioN) is a scalable method for fault grading which uses local fault simulations to estimate the fault coverage of a large system. The generality of this method makes it applicable for any modular design. Our analysis shows that the run time of our algorithm is related to the number of gates and the number of IOs in a module, while fault simulation run time is related to the total number of gates in the system. We have measured fault coverage for OR1200 and IVM processors and compared the results with fault simulation performed by a commercial tool. We have also compared our results with fault sampling. Our results show that for large designs FALCON is an order of magnitude faster compared with fault simulation. It also has a smaller error rate compared with fault sampling when the size of design under test grows.

This series will discuss board and system level testing of high speed optical interfaces. Today these interfaces operate up to 10 Gbps over short, medium and long ranges. In the not too distant future, these interfaces will be operating in ranges up to 40 Gbps. There are several factors that can affect the performance of board/system level high speed, serial interfaces, including signal integrity issues in the optics and at the board level, power and other components such as clocks. The application series will provide background on high speed serial interfaces and techniques used to test these interfaces. This background will include a discussion about optical and electrical parameters that are tested and how they could impact the performance of these interfaces. The application series will continue with a discussion of the different test techniques. One aspect of this will include a discussion of the lack of standardization in the measurements that are taken by test equipment. The application series will conclude by talking about future interfaces and what it will take to effectively tests those interfaces.

In-circuit test (ICT) has been used for more that 30 years to test for correct assembly of components on to a printed circuit board (PCB). The premise behind the in-circuit test philosophy was based on gaining netlevel access to a circuit and driving and sensing signals through the components of that circuit to determine if the components were placed correctly and soldered correctly to the board. Given today's board density and speed requirements, it is becoming more and more challenging to gain access to all of the nets on a given printed circuit assemble (PCA). Even with 100% access, the tester may not be capable of testing all of the nets on a large, high density PCA (due to the sheer number of nets on the board). In addition, as more and more logic is integrated into devices and signal integrity begins to dominate interconnect as the primary board level concern; the "relevance" of in-circuit test seems to be diminishing. This paper will discuss the application of "advanced" in-circuit test techniques to help improve the effectiveness of the in-circuit test on large, fast, complex PCAs with limited (test point) access.

There is an industry-wide initiative called IJTAG (I for Internal) that has been prompted by the fact that many device and board test engineers are using the IEEE 1149.1 test access port and its supporting hardware and instruction features to access a variety of device-internal instrumentation. The IJTAG initiative was started at ITC 2004 and is now supported by over 50 device design and test professionals from all sectors of the electronics industry. IJTAG was formed to control the proliferation of unusual uses and, in some cases, non-compliant design of the TAP, which culminated in the 2005 submission of a project authorisation request to the IEEE to standardise the new technology emerging from the study. The IJTAG initiative is now known as the IEEE PI687 draft standard for the access and control of instrumentation embedded within a semiconductor device. In the words of the PAR, this standard will develop a methodology for access to embedded test and debug features (but not the features themselves) via the IEEE 1149.1 test access port (TAP) and additional signals that may be required. The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features. This embedded tutorial describes the work carried out so far by the P1687 working group. The two presenters are members of the P1687 core group and they will reflect the very latest thinking of the group

The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware interface scheme are all taking shape, but still have many details to complete. Since this is a snapshot taken during the standard development process, the final form of the draft standard may differ from what is described here; any feedback to the working group is welcome

The outsourcing of manufacturing to low cost regions has significantly changed product cost models. The impact of test may be much more difficult to determine in lower cost regions. This paper presents some background on product cost models and the effect that outsourcing has on these cost models. In light of these affect the concept of return on investment for "test enhancements" is discussed. The paper provides examples of how test enhancements can generate both positive and negative ROI. The paper concludes by presenting ideas on how test engineers can influence product costs, in both a positive and negative way. The reader should note that these examples use hypothetical data based on quotes received over the last several years from contract manufacturers. The intent of these examples is to illustrate the concepts presented

As chip, board and system technologies scale towards higher speeds and greater logic density, the effect of defects becomes more subtle, but more pervasive. As hardware designers push technologies to the limit, system DPM rates continue to increase, yet it becomes increasingly difficult to determine the nature of the failures. More and more often, components/ASICs which fail at board and system test are sent to suppliers, only to have them returned "NTF" (no trouble found). This paper presents some of the issues that Cisco Systems has experienced with respect to NTFs, and how some of those issues were resolved. These issues span from chip to system and from process to test to debug. The paper discusses the importance of a process to deal with NTFs and the importance of accurate data to determine and fix unwanted trends. Ultimately, most problems were resolved once the trend data and the offending logic were completely understood. Not all NTFs resulted from test escapes. It was clear, however, that some sort of "correlation" between the ASIC test and the system test needed to be in place to resolve/prevent NTF issues. In its conclusion, this paper advocates for much better correlation between the ASIC test on the component tester and the functional test in the system chassis.

This paper looks at IEEE 1149.6, two years after being approved as an IEEE standard. The paper was written based on: interviews with companies that have implemented IEEE 1149.6 (either in hardware or software tools), emails from the 1149.6 distribution list, working group meetings and previous papers. The paper begins with a review of the 1149.6 standard, including objectives of the standard and what the standard was not meant to do. It will then present some initial findings and concerns, prior to release of the standard. The paper also discusses the adoption of the standard and issues that have been discovered by companies trying to implement the standard

The "back-end" costs associated with debug of functional test failures can be one of the highest cost adders in the manufacturing process. As boards become more dense and more complex, debug of functional failures will become more and more difficult. Test strategies try to detect and diagnose failures early on in the test process (component and structural tests), but inevitably some defects are not detected until functional testing is done on the board. Finding these defects usually requires an "expert", with engineering level skills in both hardware and software. Depending on the complexity of the product, it could take several months (even years) to develop this level of expertise. During the initial product ramp, this expertise is usually most needed and often unavailable. Debug time is usually very long and scrap rates are generally high. This paper will provide an overview of reasoning-based diagnosis techniques and how they can significantly decrease debug time, especially during new product introduction. Because these engines are "model-based", there is no guarantee how they will perform in real life. In almost all cases, the reasoning engine will have to be modified based on instances where the reasoning engine could not correctly identify the failing component. Making these adjustments to the reasoning is a very complex and sometimes risky endeavor. While the new model may correctly identify the previously missed failure, the reasoning may have been altered to a point where several other diagnoses have now been unknowingly compromised. This paper will propose enhancements to the reasoning engine that will allow a simpler approach to adapting to diagnostic escapes without risking compromises to the original diagnostic engine.

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

Testing of processors and mixed signal IP require large number of functional vectors to assure high coverage. Built-in-test features helps to reduce the vector count and increase coverage. Building bit error rate test capability and jitter test capability into the SerDes logic reduce the requirement for very expensive equipment to test these parameters. Power requirements for testing is larger than power requirements for functional operation. Testing in an SoC environment requires careful planning on the part of the IP integrator and careful attention to DFT on the part of the IP provider.

Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.

Board level testing account for the functionality and performance of all the device placed on the board, and also account for how the devices are assembled on to the board and how the device interact with one another. Three areas of board and system level testing are structural testing, functional testing and parametric testing. Structural testing focuses on the assembly process given above. Parametric tests have well defined metrics like bit error rate and jitter. Functional testing are targeted very less in order to target the defects.

This work presents a simulation-based, fault insertion environment, which allows faults to be "injected" into a Verilog model of the hardware. A co-verification platform is used to allow real, system level software to be executed in the simulation environment. A fault manager is used to keep track of the faults that are inserted on to the hardware and to monitor diagnostic messages to determine whether the software is able to detect, diagnose and/or cope with the injected fault. Examples be provided to demonstrate the capabilities of this approach as well as the resource requirements (time, system, human). Other benefits and issues of this approach also be discussed.

Growing ASIC design sizes and advanced deep sub-micron technologies require new fault models and more test vectors to meet high test quality goals. To realize these goals within given test resources and cost constraints, new DFT techniques must be used. This paper reports test quality metrics and the test cost of industrial designs for different fault models using three DFT techniques: ATPG for deterministic patterns, Logic BIST for pseudo-random patterns, and EDT for compressed deterministic patterns. It is shown how these techniques can be used to achieve the high quality goals within the test resources currently available for stuck-at tests.

This work presents an approach for system testing of networking equipment. This approach utilizes network traffic generators to simulate a "real life" environment for the unit under test. The traffic which is generated by the test equipment can be used to test both the hardware and software in the unit under test as well as the interaction between the hardware and software. Another important aspect of this level of system testing is conformance testing which ensures that networking equipment from different vendors can interact reliably. A general overview of networking systems be presented, discussing the key elements of the networking system. A "real life" system test methodology which utilizes the traffic generator then be presented along with the benefits of this approach.

From the viewpoint of a casual observer, it appears that less than 10% of the paper and panel presentations at ITC in the last 10 years have been related to board test. Of those, the majority have focused on boundary scan testing. Note that both IEEE 1149.1 and IEEE 1149.4 are standards for IC’s. Board testing continues to be a significant challenge for producers of both high volume and high complexity PWA’s. The impact of a poor board/system test strategy is felt even more by contract manufacturers. So why is it, then, the board and system test are not receiving more attention at ITC?

Very high-speed, digital technology is imposing new requirements on test logic that will limit the effectiveness of current IEEE 1149.1 based testing. IEEE P1149.6 is an extension to IEEE 1149.1 that attempts to standardize the boundary-scan structures and methods required to ensure simple, robust and minimally intrusive boundary-scan testing of advanced digital networks which are not adequately addressed by existing standards. This includes AC-coupled networks, differential networks or both. This paper will describe the work that has been done thus far by the P1149.6 working group including: defects to be targeted by the proposed standard, physical layer implementation for both the driver and receiver, verification of proposed solutions through SPICE modeling, BSDL and tools implications. The paper will also discuss some of the challenges faced by the working group and will discuss new approaches taken on by the working group in the development of the proposed standard.

Unsafe board states are created when boundary-scan vectors adversely affect non-boundary-scan logic or boundary-scan devices in functional mode. Case studies are provided based on work performed over the last two years, consequences are discussed and solutions are provided.

This paper proposes a framework to help designers understand how to integrate customized design for test features under the guidelines of the 1149.1 standard. The paper begins by discussing the reasoning behind some of the essential features of the IEEE 1149.1 boundary scan standard. Following that, arguments are made for allowing greater flexibility within the standard in order to accommodate design features, that may follow the intent of the standard but not necessarily the letter of its specification. An example of such a feature is to allow I/O cells in which test logic is "shared" with functional logic. The proposed framework for compatibility with the IEEE 1149.1 standard may result in some changes to the current standard. The framework is intended to provide a guideline for additional tools and recommendations to be developed by the IEEE 1149.1 working group and EDA companies in order to help produce testable designs. The framework also helps to explain and understand the ramifications of implementing testability features, which are not compliant with the boundary-scan standard.

Boundary scan provides test engineers with a powerful tool for detecting both board-level and chip-level faults. The benefits of boundary scan can be diminished, however, when commonly used design and test generation tools are tied to a specific implementation (standard) of boundary scan. By requiring a specific implementation, test tools may limit a designer's ability to design an optimal product. A "higher" level standard is required which abstracts the concept of accessibility to device I/O from specific implementation details. Abstracting information required for tool developers from implementation details should allow tools to become more flexible, enabling designers to optimize their specific boundary scan implementation without losing the benefit of the tools themselves.