Abstract Graphics processing units (GPUs) have become integral to embedded systems and supercomputing centres due to their large memory, cutting-edge technology and high performance per watt. However, their susceptibility to transient errors requires a comprehensive analysis of error sensitivity, as well as the development of error mitigation techniques and fault-tolerant algorithms. This study focuses on evaluating the soft-error sensitivity of two distinct versions of LU decomposition algorithms implemented on two very different GPUs—a low-power SoC embedded GPU and a high-performance massively parallel GPU. Through extensive fault injection campaigns on both GPUs, we examine the vulnerability of the algorithms, identify error causes, and determine critical code components requiring enhanced protection. The experiments reveal that most single bit flip fault injections in the instruction results lead to erroneous outcomes or unrecoverable errors. Notably, efficient GPU resource utilisation can increase the number of masked errors, thereby enhancing error resilience. Additionally, while different parts of the code exhibit similar error occurrence types and rates, the propagation of errors to elements within the result matrix differs significantly.

Studying the radiation effects on electronic devices is essential for avionics and space systems. The shrinking technology nodes and increasing density of devices enhance the sensitivity of electronic systems to ionizing radiation. Due to their crucial role, memories and processors are the highest contributors to soft errors in systems, making them the best candidates for studying these effects. This work introduces the radiation environment in space and atmosphere and the main effects that the different types of ionizing particles that are present in these environments may produce on electronic devices. Furthermore, mainly focusing on Single-Event Effects (SEEs), it presents approaches and tools for modeling SEEs and their impact on memories and microprocessors. Additionally, experimental results targeting a Commercial-Off-The-Shelf self-refresh Dynamic RAM are presented. These experiments are based on radiation test campaigns in particle accelerators with neutrons and protons. Finally, an overview of issues and mitigation techniques for microprocessors is exposed.

Hardware Trojans have become in the last decade a major threat in the Integrated Circuit industry. Many techniques have been proposed in the literature aiming at detecting such malicious modifications in fabricated ICs. For the most critical circuits, prevention methods are also of interest. The goal of such methods is to prevent the insertion of a Hardware Trojan thanks to ad-hoc design rules. In this paper, we present a novel prevention technique based on approximation. An approximate logic circuit is a circuit that performs a possibly different but closely related logic function, so that it can be used for error detection or error masking where it overlaps with the original circuit. We will show how this technique can successfully detect the presence of Hardware Trojans, with a solution that has a smaller impact than triplication.

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.

Integrity assurance of configuration data has a significant impact on microcontroller-based systems reliability. This is especially true when running applications driven by events which behavior is tightly coupled to this kind of data. This work proposes a new hybrid technique that combines hardware and software resources for detecting and recovering soft-errors in system configuration data. Our approach is based on the utilization of a common built-in microcontroller resource (timer) that works jointly with a software-based technique, which is responsible to periodically refresh the configuration data. The experiments demonstrate that non-destructive single event effects can be effectively mitigated with reduced overheads. Results show an important increase in fault coverage for SEUs and SETs, about one order of magnitude.

Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.

Transient faults can affect the behavior of electronic systems, and represent a major issue in many safety-critical applications. This paper focuses on Control Flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers. The new method achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost: moreover, the proposed technique does not involve any change either in the processor hardware or in the application software, and works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

Approximate logic circuits can be used in hardware redundancy approaches to reduce the overheads at the expense of slightly sacrificing robustness. However, a major drawback of existing logic approximation methods lies in the difficulty of estimating the effect of approximations in the total error probability and therefore to identify and select optimal approximation transformations. In this work, we propose an approach to build approximate logic circuits for a given acceptable error target. Using signal probabilities, we can dynamically estimate the probability of error that can be expected when an approximation is taken, use it to iteratively select optimal transformations and keep an estimation of the total error probability in order to stick to a given target. Experimental results show how this approach can be used to generate optimal approximate logic circuits for any particular tradeoff between robustness and area overhead.

Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

Robust communications protocols are widely used in safety critical applications, such as aerospace or automotive systems. On-board complex systems, working in harsh environments, are composed of distributed modules with a high degree of interaction and critical tasks replication. Single Event Upsets (SEUs) are very probable to affect these modules and their communications. Robust protocols are usually designed to correct communication data errors, usually due to problems in the physical medium (e.g. noise). They provide robustness in data transmission but fault tolerance is not ensured in the interface control logic. In this work, a study of the SEU sensitivity of a typical robust communication protocol, the CAN bus, is performed. Authors have applied an extensive fault injection campaign in the internal modules of the circuit that implements this standard in order to perform a depth analysis. Experimental results prove robustness is not complete in the control part of this protocol. Selective hardening will enhance this robustness with low extra cost in terms of area or performance.

Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic circuits driven by testability estimations. Using the concept of unate functions, approximations are performed in lines with low testability in order to minimize the impact on error coverage. The proposed approach is scalable and can provide a variety of solutions for different trade-offs between error coverage and overheads.

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

In order to obtain more secure and reliable systems, the vast majority of RFID protocols include a Pseudorandom Number Generator (PRNG) in its design. However, the authors often do not specify the PRNG to use and standard solutions exceed the capabilities of low-cost RFID tags. In this paper, we propose two lightweight PRNGs (AKARI-1 and AKARI-2) that meet the requirements of these systems while improving their reliability and security. They may be supported on commercial tags of low price.

The process of designing robust digital systems is getting heavier and longer due to the increase of functional complexity and circuit sensitiveness [1][2]. Furthermore, aerospace and automotive electronics are including more digital systems with critical tasks distribution among several single and cheaper modules. Although collaborative hardening is providing very interesting results in terms of cost and reliability, the design process becomes more difficult. Redundant tasks, hardware and software, must be evaluated together with the global and local error mitigation techniques. Also, network links affect error propagation and mitigation. Finally, the error accumulation must be considered in these systems working in harsh conditions. In this paper we present a general method for evaluating the Single Bit Upsets (SBU) sensitivity of complex digital systems with critical tasks distribution and collaborative hardening. This method performs a detailed analysis of signal integrity along system operation thanks to hardware emulation in the early steps of the design cycle.

Pseudorandom number generators (PRNGs) are used frequently in secure data processing algorithms. Randomness measuring is an essential test, performed on these generators, that help to range the security of the designed algorithm with respect to assure strong messing-up of the processed data. This paper describes a solution for accelerating statistical tests of Diehard Battery based on reconfigurable hardware, benefiting from task parallelization and high frequencies. With this proposal, users can obtain a fast, cheap and reliable measure of the randomness properties that can enable a complete exploration of the design space to produce better devices in shorter times.

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

An increasing number of applications require being able to detect possible faults arising during the normal activity of the electronic system: for this reason, on-line fault detection is a hot topic today. This paper proposes a new technique which is suitable for microprocessor-based systems (no matter whether they are implemented in a single device or with discrete COTS) that exploit hardware duplication and combines it with the On-Chip Debug features existing in many processors. The new technique increases the observability of faults (thus increasing detection probability and reducing latency) and is characterized by a very reduced intrusiveness in terms of changes required in the application code.

A new solution is presented for fast measuring of randomness properties of cryptographic algorithms. Statistical Tests from NIST are hardware implemented in order to enable an on-line detection of intentional attacks in cryptographic ciphers. The small area overhead and the short processing times provide a good solution for hardening this type of circuits.

SEU effects are a main concern in an increasing number of applications. Selective hardening in early design stages is intended to design a robust circuit in a fast and cost-efficient way. In this paper, a method to performing selective hardening in digital circuits against SEUs is described. This method is based on the autonomous emulation fault injection technique. It allows the designer to identify the critical parts of the circuit and use different hardening techniques to reach a trade-off between the obtained robustness and area and performance penalties. A PIC microcontroller has been analysed in detailed against SEU effects as case study, injecting millions of faults. Results points out that hardening just 17% of the circuit flip-flops reduces the failure rate induced by SEUs in 99%.

Latest mitigation techniques proposed at register-transfer level for dependable cryptosystems deal with time redundancy in an active on-line error-detection scheme. Round-based block ciphers are very likely to be hardened with these techniques. Although good results are achieved in terms of area or time overhead, intentional attacks are still able to obtain crucial information by means of intensive fault injection campaigns. In this paper, a new solution is presented and analyzed, dealing with pseudo-random number generators (PRNG) with the goal of misleading attackers and, therefore, making cryptosystem more robust. With this approach, attackers must face two difficulties: dealing with on-line error detection and ignoring the fault location in the round sequence. PRNG will produce different repetition sequences for the rounds of the cryptosystem, making very difficult to correlate output data with injected faults.

We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.

This paper presents an important improvement in the current capabilities of existing Redundancy Addition and Removal (RAR) techniques for digital circuits logic optimization. In this work we present a new efficient way of finding all the possible logic addition transformations that allow the removal of a given selected wire in the circuit. All the possible points in the circuit where the addition can be performed and all the possible transformations, involving multiple wires, in each of those points are identified. We prove the necessary and sufficient conditions for the existence of such transformations. RAR algorithms use these possible sets of transformations for different optimizations, like area or timing, which have been shown to be very effective in previous works. Improving the core of these algorithms is the key to improve the RAR optimization methods themselves.

In this paper a coarse-grain dynamically reconfigurable coprocessor for image processing is presented. This coprocessor is the main component of a System on a Programmable Chip (SoPC). The coprocessor can accelerate a wide range of image processing tasks and can be configured in a few clock cycles. The coprocessor performance and reconfiguration functionality has been tested with algorithms that involve several reconfiguration steps and microprocessor interaction. Experimental results demonstrate that the SoPC based on a 100 MHz soft microprocessor core can reach much better performance than a 3.2 GHz PC.

Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness together with a small penalty in the algorithm throughput when dealing with specific intentional attacks. Experimental results on Advanced Encryption Standard are presented and discussed.

Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). It can be widely applicable to different processors since JTAG standard is an extended interface and OCDs are usually available in current processors. The hardware implementation avoids the communication between the target system and the software debugging tool. The method has been applied to a complex processor, the ARM7TDMI. Results illustrate the approach is a fast, efficient and cost-effective solution.

Systems-on-programmable-chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a Web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack

FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed autonomous emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the autonomous emulation techniques to circuits with embedded memories is presented. The LEON2 processor benchmark is used to demonstrate as an application for the proposed techniques

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitivity to radiation. So errors are currently appearing in ICs working at the Earth's surface. Hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the FT evaluation. In this work, a new emulation system for FT evaluation with respect to SEU effects is proposed, providing shorter evaluation times by performing all the evaluation process in the FPGA and avoiding emulator-host communication bottlenecks.

Platform FPGAs provide a high degree of reconfigurability and a high density of integration. These features make these devices very suitable for hardware emulation and in particular for fault tolerance evaluation. There are several FPGA-based approaches that enhance notably the fault tolerance evaluation process achieving an important speed up. However, such methods are limited by the communication between the FPGA and the host computer, which manages the emulation process. In order to minimize this communication and therefore accelerate the overall process, an autonomous emulation system is proposed in this paper. This solution profits from additional hardware resources available in current platform FPGAs such as embedded RAM. In the proposed system, a complete emulation campaign and its management is embedded in the FPGA, accelerating emulation process up to two orders of magnitude without losing flexibility with respect to other hardware solutions.

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Therefore, hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of CAD tools, for the generation and the validation of fault tolerant circuits, will allow designers to obtain hardened devices in a cost-effective way with short development times and with high reliability results. While automatic insertion of fault tolerant structures in designs is already possible, automatic evaluation with an optimum time-cost relation is still needed. In this sense, the use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the fault tolerance evaluation. In this work, a new emulation system for the evaluation of FT with respect to SEU effects is proposed. This solution gets profit of hardware resources for accelerating the FT evaluation. It is analysed and compared with respect to other emulation techniques. The proposed solution provides not only short times but also low cost in area for FT validation, giving better results than pure software or hardware solutions.

Fault-tolerant circuits are currently required in several major application sectors, and a new generation of CAD tools is required to automate the insertion and validation of fault-tolerant mechanisms. This paper outlines the characteristics of a new fault-injection platform and its evaluation in a real industrial environment. The fault-injection platform is mainly used for assessing the correctness and effectiveness of the fault tolerance mechanisms implemented within ASIC and FPGA designs. The platform works on register transfer-level VHDL descriptions which are then synthesized, and is based on commercial tools for VHDL parsing and simulation. It also details techniques devised and implemented within the platform to speed-up fault-injection campaigns. Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.

When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising a sample safety-critical device. Designers were permitted to assess the effects of transient faults, automatically add fault-tolerant structures, and validate the results working on the same circuit descriptions and acting in a coherent framework. The evaluation showed the effectiveness of the proposed environment.

This work provides a generalization of structural logic optimization methods to general boolean networks. With this generalization, the nodes of the network are no longer restricted to simple gates and can be functions of any size. Within this framework, we present necessary and sufficient conditions to identify all the possible functional expansions of a node that allow to eliminate a wire elsewhere in the network. These conditions are also given for the case of multiple variable expansion, providing an incremental mechanism to perform functional transformations involving any number of variables that can be applied in a very efficient manner. On the other hand, we will show in this paper that relevant simplifications can be obtained when this framework is applied to the particular case of AND-OR-NOT networks, resulting in important savings in the computational effort. When compared to previous approaches, the experimental results show an important reduction in the number of computations required.

In this work a generalization of the structural Redundancy Addition and Removal (RAR) logic optimization method is presented. New concepts based on the functional description of the nodes in the network are introduced to support this generalization. Necessary and sufficient conditions to identify all the possible structural expansions are given for the general case of multiple variable expansion. Basic nodes are no longer restricted to simple gates and can be any function of any size. With this generalization, an incremental mechanism to perform structural transformations involving any number of variables can be applied in a very efficient manner. Experimental results are presented that illustrate the efficiency of our scheme.

The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.

This paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case, the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then, we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal techniques over the retiming and resynthesis techniques.

This paper presents a new integrated approach to logic optimization for sequential circuits. The approach is based on the redundancy addition and removal algorithm, which is based on automatic test pattern generation (ATPG) techniques, and improves it using symbolic techniques based on BDDs. The advantage of the integrated approach lies in the ability of Symbolic Techniques to provide exact and extensive information about the sequential behavior of the portion of the circuit that is of interest to the logic optimization algorithm. Experimental results are provided that show the superiority of the approach to the original ATPG-based optimization approach.

Prototyping has been used to develop electronic systems for a long time. In this work a new prototyping approach, that we named VHDL Virtual Prototyping, is introduced. The new approach introduces VHDL models as the hardware part of the system prototype. The software components of the system are then executed and debugged on top of the hardware models of the system. A platform for developing electronic systems using VHDL Virtual Prototyping is presented. The enhancement of this approach for mechatronics is also introduced.

This paper presents a method for multilevel logic optimization for combinational and synchronous sequential circuits. The circuits are optimized through iterative addition and removal of redundancies. Adding redundant wires to a circuit may cause one or many existing irredundant wires and/or gates to become redundant. If the amount of added redundancies is less than the amount of created redundancies, the transformation of adding followed by removing redundancies will result in a smaller circuit. Based upon the Automatic Test Pattern Generation (ATPG) techniques, the proposed method can efficiently identify those wires for addition that would create more redundancies elsewhere in the network. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal.>

This paper presents a method of multi-level logic optimization for combinational and synchronous sequential logic. The circuits are optimized through iterative addition and removal of redundancies. Among the large number of possible connections that can be added, the proposed method can efficiently identify those connections that would create more redundancies and, thus, would result in a smaller network. This is done with the use of combinational and sequential ATPG techniques based up the concept of mandatory assignments. Experiments on ISCAS-85 combinational benchmark circuits show that best results are obtained for most of them. For sequential circuits, experimental results on MCNC FSM benchmarks and ISCAS-89 sequential benchmark circuits show that a significant amount of area reduction can be achieved beyond combinational optimization and sequential redundancy removal.