Developing large-scale integrated circuits starts with specifying the desired system behavior. While specifications must be precise and dependable for both design and verification purposes, traditional specifications rely on natural language documents and their human interpretation. This introduces two critical weaknesses: First, interpretation can be challenging due to vagueness and inherent ambiguity. Second, validating that a natural language specification expresses the intended behavior is hardly possible with deterministic methods. To tackle these challenges, we use a formal specification format, called the Universal Specification Format (USF), with unambiguous syntax and semantics. USF applies to the specification of general digital hardware and automatically generates formal properties for design verification. Still, it must be ensured that the formal specification—and thus the generated properties—correctly express the desired system behavior. In this paper, we present a novel code generator for behavioral simulation models to execute USF specifications and validate them against use cases. Moreover, we introduce and integrate runtime checks into the simulations that automatically detect inconsistencies and gaps in the specification. This methodology has been applied to industrial-strength hardware components and their formal specifications, demonstrating the effectiveness and industry-readiness of our behavioral simulation models and the automated runtime checks. We finally show that USF enables reusable code generators for both simulation-based specification validation and formal design verification.

The TRISTAN project aims to expand and industrialize the European RISC-V ecosystem to compete effectively with existing commercial alternatives. This initiative specifically targets the critical challenges in the development of Electronic Design Automation (EDA) tools, essential for RISC-V-based solutions, by leveraging the synergy between the open-source community and industrial solutions. This paper presents an overview of the current landscape of TRISTAN's EDA flow, highlighting specific tools and methodologies that streamline the early design phases of RISC-V-based systems. We explore the unique features of these tools, emphasizing how they complement each other to strengthen the overall design process.

Digital division is a pivotal operation in a number of domains, such as scientific computation, cryptography, digital signal processing, and machine learning, and has been broadly researched in the past decades. However, the increasing demand for efficient digital systems has emphasized the design of digital dividers with more stringent area and power costs without excessively compromising their performance. One option to achieve this is to implement Single Instruction Multiple Data (SIMD) dividers capable of exploiting the abundance of data-level parallelism, which is naturally present in common tasks such as stream processing, matrix normalization, and vector scaling. In this paper, we propose the designs of four configurable integer dividers capable of sustaining both Single Instruction Single Data (SISD) and SIMD computations, targeting different levels of performance and efficiency. Compared to one of the state-of-the-art integer dividers, our most efficient SIMD divider shows a 54% smaller area and 30% lower power consumption. Furthermore, we propose a novel technique which can reduce n-bit divisions to smaller (n−m)-bit ones, yielding a peek speedup of 15% when implemented in one of our proposed dividers.

A key challenge for Deep Neural Network (DNN) inference on resource-constrained edge devices is the high energy consumption caused by frequent memory accesses for parameters. While our previous research has demonstrated the efficacy of data compression for weights, this paper extends our approach to include on-the-fly compression and decompression of activations. We propose a comprehensive hardware solution comprising two main components: a Golomb-Rice (GR) compression system and an Output Activation Processing Module (OAPM). The GR system provides an efficient activation compression mechanism, while the OAPM enables dynamic data-format capabilities for handling activations. Additionally, we present an enhanced Input Activation Extract Module (IAEM) with an integrated decompression unit and dynamic activation processing capabilities. When integrated with an industry-strength Neural Network accelerator and evaluated using the Anomaly Detection (AD) TinyML benchmark, our lossless compression system achieved a 2.3× compression ratio, reduced memory bandwidth usage by 49.28%, and improved inference speed by 10%.

The push to support artificial intelligence in embedded systems introduces new challenges regarding software support of specialized hardware. The RISC-V instruction set architecture offers a promising platform for accelerators for said AI applications through custom instructions. Integrating these instructions into existing software codebases poses significant challenges, including manual adaptations and limited compiler support. This paper introduces a novel approach that generates hardware-optimized code utilizing custom instructions defined by a platform model. This method enhances the reusability of code and leverages design artifacts from the hardware design process to optimize the generated software in both C and Rust by generating intrinsic support for custom instructions through inline assembly. If the underlying platform does not allow the utilization of the specified custom instruction, an alternative implementation with optional global side effects is generated instead of the intrinsic. Thus, it expedites development by minimizing manual coding efforts and facilitates the seamless integration of hardware accelerators. An exemplary implementation of a matrix multiplication utilizing a custom multiply-accumulate instruction presented in this paper highlights the efficiency provided by this approach. Measurements based on this implementation show a reduction of the executed instructions by up to 75% while also achieving a 5-fold theoretical reduction in manual effort.

This paper presents a demonstrator chip for an industrial audio event detection application developed as part of the Scale4Edge project. The project aims at enabling a comprehensive RISC-V based ecosystem to efficiently assemble well-tailored edge devices. The chip is manufactured in Globalfoundries' 22FDX technology and contains a RISC-V CPU with custom Instruction-Set-Architecture Extensions (ISAX) for fast AI and DSP processing, a low power neural network accelerator, and a scalable PLL to fulfill real-time processing requirements. By automated integration of these specialized hardware components, we achieve a speedup of ×2.15 while reducing the power by 27% compared to the unp[ntimized solution.

Deep Neural Networks (DNNs) have created opportunities to address real-world issues and expand the application of Artificial Intelligence (AI). Despite significant accuracy enhancements, DNNs pose a challenge when deployed on resource-limited edge devices commonly used in Internet of Things (IoT) applications. Inference execution of the DNNs requires accessing millions of parameters responsible for most energy consumption. Compression of weights is one possible solution, but most of the existing hardware decompression units could be more efficient in terms of power, area, and energy. This paper presents a scalable version of a hardware-efficient Parallel Golomb-Rice decoder (PaGoRi). The decoder has been integrated with an industry-strength Neural Network (NN) accelerator and evaluated with three TinyML benchmarks. The PaGoRi decoder achieves optimal trade-offs between power consumption and throughput, supporting decoding capacities of four and eight weights, consuming 0.43 mW and 0.79 mW of power, respectively, while achieving a throughput of 888 MBps and 1.3 GBps, respectively.

Deep Neural Networks (DNNs) offer possibilities for tackling practical challenges and broadening the scope of Artificial Intelligence (AI) applications. The demanding memory requirements of present-day neural networks can be attributed to the rising intricacy of network architectures. These designs encompass multiple layers with an extensive number of parameters, leading to heightened demands on memory storage. The energy consumption during the inference execution of DNNs is predominantly attributed to the access and processing of these parameters. To tackle the significant size of models integrated into Internet of Things (IoT) devices, a promising strategy involves diminishing the bit width of weights. This paper introduces an improved version of Golomb-Rice (GR) encoder and an optimized Parallel Golomb-Rice decoder that can support sparse and non-sparse DNNs. To evaluate the encoder's and decoder's efficiency, we conducted two sets of experiments using three TinyML benchmarks, one without pruning and the other incorporating pruning. The results highlight that the encoder demonstrates a Compression-Ratio (CR) superior to that of Huffman encoding, and the decoder exhibits an energy efficiency of up to 2.6 TBps/W and 2.7 TBps/W for four- and eight-weight decoding, respectively.

Hardware accelerators (HAs) underpin high-performance and energy-efficient digital systems. Correctness of these systems thus depends on the correctness of constituent HAs. Self-consistency-based pre-silicon verification techniques, like A-QED (Accelerator Quick Error Detection), provide a quick and provably thorough HA verification framework that does not require extensive design-specific properties or a full functional specification. However, A-QED is limited to verifying HAs which are non-interfering – i.e., they produce the same result for a given input independent of its context within a sequence of inputs. We present a new technique called G-QED (Generalized QED) which goes beyond non-interfering HAs while retaining A-QED’s benefits. Our extensive results as well as a detailed industrial case study show that: G-QED is highly thorough in detecting critical bugs in well-verified designs that otherwise escape traditional verification flows while simultaneously improving verification productivity 18-fold (from 370 person days to 21 person days). These results are backed by theoretical guarantees of soundness and completeness.

Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. This paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges.We present several state-of-the-art safety and reliability verification techniques in the design phase. These include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications.By combining these techniques with the inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. The insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.

Due to the recent advances in AI, the requirement for Artificial Intelligence (AI) has increased exponentially in the domain of Internet of Things (IoT). Running Deep Neural Networks (DNNs) on edge devices gives the advantage of privacy, security, and lower latency. It is challenging to deploy them on embedded devices with constrained hardware resources since a lot of compute and memory resources are required. Memory access contributes to the majority of the energy requirements on edge devices. Although data compression plays a critical role in reducing storage and memory bandwidth requirements, most of the hardware decoders are inefficient in terms of power, area, and throughput. In this work, a hardware Parallel Golomb-Rice decoder is presented that can decode 8-bits of unary encoded data every cycle. The design has been integrated with a Neural Network (NN) accelerator and experimented with state-of-the-art benchmark models. Lossless compression is performed with an offline Golomb-Rice encoder. It encodes the weights of each layer with an optimum Golomb-Rice parameter. Applied to the benchmarks Anomaly Detection, Image Classification and Visual Wake Words the memory access during inference is reduced by 26.8%, 6.62% and 5.54% respectively. The decoder dissipates 0.4216 mW of power and delivers an average throughput of 860 MBps. The design has been synthesised with 40 nm technology and compared with state-of-the-art works.

We present FPGA-implementation techniques to efficiently validate application readiness of a product for analog/mixed-signal (AMS) applications that lead to a reduction of overall runtime by two orders of magnitude on the example of a power conversion application compared to state-of-the-art simulation based approaches. Further, we use this example to analyze area utilization, timing impact and scalability at increased application complexity. The open source synthesizable model generator for mixed-signal blocks msdsl is extended to support reconfigurable variables within a model description. Further, the control API of the open source FPGA prototyping automation anasymod is enhanced to allow updating these variable values on FPGA at runtime. The end-result is a unique framework for application scenario driven product validation that to our knowledge for the first time allows reconfiguration of analog dynamics on FPGA at runtime and leverages benchmark AMS system simulation throughput on FPGA to enables fast system property sweeping at different modeling abstractions.

Driven by Moore’s law, the chip design complexity is steadily increasing. Electronic Design Automation (EDA) has been able to cope with the challenging very large-scale integration process, assuring scalability, reliability, and proper time-to-market. However, EDA approaches are time and resource demanding, and they often do not guarantee optimal solutions. To alleviate these, Machine Learning (ML) has been incorporated into many stages of the design flow, such as in placement and routing. Many solutions employ Euclidean data and ML techniques without considering that many EDA objects are represented naturally as graphs. The trending Graph Neural Networks (GNNs) are an opportunity to solve EDA problems directly using graph structures for circuits, intermediate Register Transfer Levels, and netlists. In this article, we present a comprehensive review of the existing works linking the EDA flow for chip design and GNNs. We map those works to a design pipeline by defining graphs, tasks, and model types. Furthermore, we analyze their practical implications and outcomes. We conclude by summarizing challenges faced when applying GNNs within the EDA design flow.

This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned demonstrators, which will be used in their evaluation.

In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would increase the quality of the results and lower the flow iterations. Machine learning has been used to estimate the timing behavior of chip components. However, existing solutions map EDA objects to Euclidean data without considering that EDA objects are represented naturally as graphs. Recent advances in Graph Neural Networks (GNNs) motivate the mapping from EDA objects to graphs for design metric prediction tasks at different stages. This paper maps RTL designs to directed, featured graphs with multidimensional node and edge features. These are the input to GNNs for estimating component delays and slews. An in-house hardware generation framework and open-source EDA tools for ASIC synthesis are employed for collecting training data. Experiments over unseen circuits show that GNN-based models are promising for timing estimation, even when the features come from early RTL implementations. Based on estimated delays, critical areas of the design can be detected, and proper RTL micro-architectures can be chosen without running long design iterations.

We present a framework that enables systematic analysis of mixed-signal application on FPGA and show its application during architecture validation of a power controller. The open source synthesizable model generator for mixed-signal blocks (msdsl) is used to create a synthesizable prototype of the analog power control application. A library of instrumentation elements enables control from a host computer, time control, analog event capture, analog stimulus and noise generation, as well as trace, read and write of arbitrary signals. This keeps the effort of building the FPGA application prototype low and provides good debugging and analysis capabilities. The end-result is a unique analysis framework for mixed-signal applications that offers almost real time analog simulation speed - thus considering software as well as analog and digital hardware - no risk of damaging equipment and simulator alike analysis and debugging capabilities at a low overhead through an instrumentation library.

While semiconductors are becoming more efficient generation after generation, the continuous technology scaling leads to numerous reliability issues due, amongst others, to variations in transistors characteristics, manufacturing defects, component wear-out, or interference from external and internal sources. Induced bit flips and stuck-at-faults can lead to a system failure. Security-critical systems often use Physical Memory Protection (PMP) modules to enforce memory isolation. The standard loosely-coupled approach eases the implementation but creates overhead in area and performance, limiting the number of protected areas and their size. While delivering great support against malicious software and induced faults, better performance would benefit safety tasks by preventing the program from jumping into an undesired region and giving wrong outputs.We propose a novel model-driven approach to resolve these limitations by generating a tightly-coupled RISC-V PMP, which reduces the impact of run-time reconfiguration. We also discuss guidelines on configuring a PMP to minimize the overhead on performance and memory, and provide an area estimation for each possible PMP design instance. We formally verified a RISC-V Core with a PMP and evaluated its performance with the Dhrystone Benchmark. The presented architecture shows a performance gain of about 3 times against the standard implementation. Furthermore, we observed that adding the PMP feature to a RISC-V SoC led to a negligible performance loss of less than 0.1% per thousand PMP reconfigurations.

Safety-critical designs need to ensure reliable operations even under a hostile working environment with a certain degree of confidence. Continuous technology scaling has resulted in designs being more susceptible to the risk of failure. As a result, the safety requirements are constantly evolving and becoming more stringent. For validating and measuring the robustness of safety-critical designs, fault injection methods are employed within the design flows. To ensure safety requirements’ compliance, and at the same time to cope with the ever-increasing complexity of modern SoCs, the existing design flows become inadequate as the process is repetitive, time-tedious, and requires high manual efforts. In this paper, a fully automated, fast and accurate, fault emulation framework based on the FPGA platform is proposed that enables a high level of controllability and observability for fault injection. The approach uses model-driven engineering concepts and automates various fault injection campaigns, namely, statistical fault injection (SFI), direct fault injection (DFI), and exhaustive fault injection (EFI). A novel design architecture tailored for the FPGA platform is also proposed to improve the overall productivity of performing fault emulation. The proposed approach scales to a wide variety of RISC-V based CPU subsystems with varying complexity in size and features. The experimental results demonstrate a significant gain in the fault emulation performance by a factor of 2.75x to 47.57x when compared to the standard simulation-based fault injection methods.

Malware applications are one of the major threats that computing systems face today. While security researchers develop new defense mechanisms to detect malware, attackers continue to release new malware families that evade detection. New defense mechanisms must therefore be developed to effectively counter malware. Hardware performance counters (HPCs) have been recently proposed as a means to detect malware. However, recent work has also shown that malware detection is not effective when performance counters are sampled in realistic scenarios. We show how proper data preprocessing and the use of the XGBoost classifier can be used to improve the performance of malware detection using HPCs by at least 15%. We also show that the proposed method can detect malware early (shortly after its launch) by classifying HPC datastreams at short time intervals. In addition, we propose a multitemporal classification model that ensures the early detection of a high percentage of malware while maintaining overall low false positive rates. Finally, we show that through robust training, the XGBoost classifier shows up to 50x less vulnerability to adversarial attacks that are intended to undermine its malware detection performance.

This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-point and floating-point synthesizable SystemVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework’s generality by discussing three applications: 1) a high-speed link receiver (DragonPHY); 2) a firmware-controlled flyback converter; and 3) an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2–3 orders of magnitude faster than CPU simulations with real-number functional models.

The scalable and extendable RISC-V ISA introduced a new level of flexibility in designing highly customizable processors. This flexibility in processor designs adds to the complexity of already complex functional verification process. Although formal methods are increasingly used to exhaustively verify the processors, the required manual effort and verification expertise become the major hurdles in industrial flows. Furthermore, efficient ISA modeling techniques are required that are scalable to multiple ISA extensions and to different architectural variants of a processor. This paper proposes a trace notation for ISA definition to capture the implicit execution behavior of a processor and specific characteristics. The proposed trace notation can be annotated with timing and hierarchy information to adapt the trace to any kind of processor architecture. From this trace notation, a complete set of properties are generated to detect all functional bugs in a processor implementation. The approach requires significantly less manual effort compared to the contemporary techniques. Its industry strength has been demonstrated by formally verifying a wide variety of RISC-V processor implementations with one or more ISA extensions (RV32I, C, Zicsr, M and custom extensions supporting AI acceleration and safety features).

Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging design requirements such as on-chip debug and functional safety. These code modifications lead to escalated development, verification efforts and deteriorate the code reuse. This paper proposes a highly efficient aspect-oriented design automation approach that leverages graph-grammar-based model transformations. With the proposed approach, main design functionalities and aspect-oriented instrumentation are separately developed, automatically integrated and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Experimental results confirm the efficiency of the approach. Further, reduced code is needed with the proposed automation approach, which also replaces the error-prone manual RTL coding. Finally, the transformation scripts are applicable to different SoCs, which promotes the overall code reuse.

The required manual effort and verification expertise are among the main hurdles for adopting formal verification in processor design flows. Developing a set of properties that fully covers all instruction behaviors is a laborious and challenging task. This paper proposes a highly automated and "complete" processor verification approach which requires considerably less manual effort and expertise compared to the state of the art.The proposed approach extends the S2QED approach to cover both single and multiple instruction bugs and ensures that a design is completely verified according to a well-defined criterion. This makes the approach robust against human errors. The properties are simple and can be automatically generated from an ISA model with small manual effort. Furthermore, unlike in conventional property checking, the verification engineer does not need to explicitly specify the processor's behavior in different special scenarios, such as stalling, exception, or speculation, since these scenarios are taken care of implicitly by the proposed computational model. The great promise of the approach is shown by an industrial case study with a 5-stage RISC-V processor.

Automatic code generation is used to implement Intellectual Property (IP) blocks for System-on-Chip (SoC), but the challenge is how to describe the IP as a model and what is a feasible meta-model. IEEE 1685 IP-XACT standard and many domain-specific meta-models are not compatible and tool flows are too specific for general use. We present Kamel that is a new intermediate IP meta-model. It is used to generate behavioral code to complete IP-XACT structural models. The key idea is light modeling overhead while automating the majority of the RTL IP development tasks. Kamel uses Model Driven Architecture (MDA) to integrate IP-XACT and Kamel modeling together. Python Mako template-based code generation framework is used to generated different views from the models. The compatibility with IP-XACT is demonstrated with the Kactus2 tool. Our case study is modeling and code generation for Kvazaar HEVC video intra encoder IP block on FPGA. The results confirm that the Kamel and introduced tool flow can provide 5×-10× productivity gain when measured on time spent on model entry and Lines of Code used for model entry.

The HW/SW interface is a common and crucial component in System-on-Chips, enabling the interaction between software and hardware. Generating architecture and firmware code of the interface from extended IP-XACT, SystemRDL, or proprietary formalism is an established technology. This paper describes a new area and performance optimization step in the HW/SW interface generation process that reduces the silicon area and hardware access time through firmware. Three improvements of the underlying formalism are applied to achieve the optimization: First, a decoupling of bit fields from registers, which allows the rearrangement of the memory layout easily. Second, the specification of hardware accesses, which constraints the bit field arrangement. Third, different implementations of bit field accesses, such as memory-mapped or via CPU special registers. The used generation framework follows the approach of model-driven architecture, which includes optimization. Initially, abstract models specify the requirements of the IP or the HW/SW interface. Transformations turn these models into platform-independent models of hardware and firmware. These models are further transformed into implementation-specific models of a target language, such as hardware description languages or C. The proposed optimization has been successfully applied to peripheral variants of a CPU subsystem used in an industrial demonstrator. An area reduction of 19% and a performance gain of 11% has been achieved by optimizing the interfaces.

The complexity of today's System on Chips (SoCs) forces designers to use higher levels of abstractions. Here, early design decisions are conducted on abstract models while different configurations describe how to actually realize the desired SoC. Since those decisions severely affect the final costs of the resulting SoC (in terms of utilized area, power consumption, etc.), a fast and accurate cost estimation is essential at this design stage. Additionally, the resulting costs heavily depend on the adopted logic synthesis algorithms, which optimize the design towards one or more cost objectives. But how to structure a cost estimation method that supports multiple configurations of an SoC, implemented by use of different synthesis strategies, remains an open question. In this work, we address this problem by providing a cost estimation method for a configurable SoC using Machine Learning (ML). A key element of the proposed method is a data representation which describes SoC configurations in a way that is suited for advanced ML algorithms. Experimental evaluations conducted within an industrial environment confirm the accuracy as well as the efficiency of the proposed method.

Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to provide a variety of options on how to realize a system. This allows for design exploration which relies on knowing the costs of different design configurations (with respect to hardware usage and firmware metrics). To this end, methods for cost estimation are frequently applied in industrial practice. However, currently used methods oversimplify the problem and ignore important features, leading to estimates which are far off from real values. In this article, we address this problem for memory systems. To this end, we borrow and re-adapt solutions based on Machine Learning (ML) which have been found suitable for problems from the domain of Computer Vision (CV). Based on that, an approach is proposed which outperforms existing methods for cost estimation. Experimental evaluations within an industrial context show that, while the accuracy of the state-of-the-art approach is frequently off by more than 20 percent for area estimation and more than 15 percent for firmware estimation, the method proposed in this article comes rather close to the actual values (just 5-7 percent off for both area and firmware). Furthermore, our approach outperforms existing methods for scalability, generalization, and decrease in manual effort.

Developing software in a slightly different way can have a dramatic impact on soft error resilience. This observation can be transferred in a process of improving existing code by transformations. These transformations are of systematic nature and can be automated. In this paper, we present a framework for low level embedded software generation - commonly referred to as firmware -- and the inclusion of safety measures in the generated code. The generation approach follows a three stage process starting with formalized firmware specification using both platform dependent and independent firmware models. Finally, C-code is generated from the view model in a straight forward way. Safety measures are included either as part of the translation step between the models or as transformations of single models.

This paper presents an automated process for end-to-end embedded system design following OMG's model driven architecture (MDA) vision. It tackles a major challenge in automation: bridging the large semantic gap between the specification and the target code. The shown MDA adaption proposes an uniform and systematic way by splitting the translation process into multiple layers and introducing design platform independent and implementation independent views.In our adaption of MDA, we start with a formalized specification and we end with code (view) generation. The code is then compiled (software) or synthesized (hardware) and finally assembled to the embedded system design. We split the translation process in Model-of-Thing (MoT), Model-of-Design (MoD) and Model-of-View (MoV) layers. MoTs represent the formalized specification, MoDs contain the implementation architecture in a view independent way, and MoVs are implementation dependent and view dependent, i.e., specific details in target language.MoT is translated to MoD, MoD is translated to MoV and MoV is finally used to generate views. The translation between the Models is based on templates, that reflect design and coding blueprints. The final step of the view generation is itself part of generation. The Model MoV and the unparse method are generated from a view language description.The approach has been successfully adapted for generating digital hardware (RTL), properties for verification (SVA), and snippets of firmware that have been successfully synthesized to an FPGA.

Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to allow plenty of options how to eventually realize a system. This allows for design exploration which in turn heavily relies on knowing the costs of different design configurations (with respect to hardware usage as well as firmware metrics). To this end, methods for cost estimation are frequently applied in industrial practice. However, currently used methods for cost estimation oversimplify the problem and ignore important features - leading to estimates which are far off from the real values. In this work, we address this problem for memory systems. To this end, we borrow and re-adapt solutions based on Machine Learning (ML) which have been found suitable for problems from the domain of Computer Vision (CV) - in particular age determination of persons depicted in images. We show that, for an ML approach, age determination from the CV domain is actually very similar to cost estimation of a memory system.

We present an industrial case study that demonstrates the practicality and effectiveness of Symbolic Quick Error Detection (Symbolic QED) in detecting logic design flaws (logic bugs) during pre-silicon verification. Our study focuses on several microcontroller core designs (~1,800 flip-flops, ~70,000 logic gates) that have been extensively verified using an industrial verification flow and used for various commercial automotive products. The results of our study are as follows: 1. Symbolic QED detected all logic bugs in the designs that were detected by the industrial verification flow (which includes various flavors of simulation-based verification and formal verification). 2. Symbolic QED detected additional logic bugs that were not recorded as detected by the industrial verification flow. (These additional bugs were also perhaps detected by the industrial verification flow.)3.Symbolic QED enables significant design productivity improvements: (a) 8X improved (i.e., reduced) verification effort for a new design (8 person-weeks for Symbolic QED vs. 17 person-months using the industrial verification flow). (b) 60X improved verification effort for subsequent designs (2 person-days for Symbolic QED vs. 4-7 person-months using the industrial verification flow). (c) Quick bug detection (runtime of 20 seconds or less), together with short counterexamples (10 or fewer instructions) for quick debug, using Symbolic QED.

This paper presents a practical methodology for applying formal verification on industrial designs. The methodology is developed considering the quality, efficiency and productivity required in an industrial verification setup. The flow proposes a systematic approach addressing various aspects of the formal verification. First, the design implementation (RTL) is analyzed for its formal friendliness based on several predefined criteria. Next, a property automation flow is adapted for an efficient property development. Later, a series of verification tasks, grouped into formal test plan and formal execution plan are carried out to reach the formal sign-off stage. To demonstrate the applicability and effectiveness of the methodology, the proposed flow has been successfully applied on several industrial designs. In this paper, we consider the formal verification of Error Correction Codes, generally implemented in program and data flash memory interfaces to benchmark the proposed flow. Automatic property generation flow is used to generate an optimal property set with varying abstraction levels. The property proof runtimes are drastically reduced and better coverage compared to the previous hand-written properties has been achieved. New RTL bugs and specification errors have been found that were previously missed during the simulation.

Advancements of Machine Learning (ML) in the field of computer vision have paved the way for its potential application in many other fields. Researchers and hardware domain experts are exploring possible applications of Machine Learning in optimizing many aspects of hardware development process. In this paper, we propose a novel approach for predicting the area of hardware components from specifications. The flow uses an existing RTL generation framework, for generating valid data samples that enable ML algorithms to train the learning models. The approach has been successfully employed to predict the area of real-life hardware components such as Control and Status Register (CSR) interfaces that are ubiquitous in embedded systems. With this approach we are able to predict the area with more than 98% accuracy and 600x faster than the existing methods. In addition, we are able to rank the features according to their importance in final area estimations.

In the last decade, several hardware generation languages (HGLs: chisel, metartl, spinalhdl, coreir and more) that focus on generation of RTL code have been proposed. These languages rise the level of abstraction from RTL description to RTL generation and utilize high-level languages such as Python or Scala for describing the generation intent. As a result, they are guiding the overall productivity and chip complexity on the rising trend. On the other front, pre -silicon verification is an equally important aspect of the design process and consumes more than 50% of the overall development time. As a consequence of increased chip complexity, the existing verification gap becomes wider. Therefore it neutralizes the productivity gain achieved from RTL generation or other productivity improvement techniques. In this paper, we describe a Python based generation language and framework for hardware properties in order to increase formal verification productivity. The described approach follows the model driven architecture (MDA) vision of OMG. The MDA approach includes transformations, that make the approach platform independent: Different property languages as well as different simulation and formal verification tools are supported. Applied to formal hardware verification, the approach empowers comparable productivity increase as HGLs in RTL designs. In addition, it is an ideal partner for HGLs, since it enables to generate a property set for each HGL generated RTL. The applicability of our approach for real -life industrial designs is demonstrated by generating properties for a RiscV CPU core and also for peripheral devices of a CPU system. The correctness of the generated properties are validated by verifying these designs with a formal verification tool.

Although Moore's law is slowing down, design productivity is still a big issue in semiconductor industry. Drivers are the trend to 3D integration, the addition of design goals such as ultra-low power and safety, and an increasing number of designs in IoT and automotive areas. EDA tools such as high-level synthesis cover a small design area only. Also, the impact of IP reuse is overestimated since IP integration often requires complex configuration and additional software to be developed. To continuously increase design productivity, Infineon heavily relies on an in-house automation framework that utilizes Python as language for automation and synthesis. It supports (and makes use of) classical HDSLs to describe specific design aspects. Mostly structured specification formalisms such as tables, requirements or diagrams (e.g. SysML subsets) are used. These formalisms can be seen as HDSLs with the additional benefit that they exist as a result of a specification process, i.e. need not be coded explicitly. To be able to deal with several formalisms, Infineon's automation framework follows OMG's MDA vision and utilizes meta-models e.g. for generation of infrastructure code. This work focuses on the aspect of combining DSLs, defining a formal semantic for HDSLs and using this definition to validate the correctness of the mapping of HDSLs to HDLs, an essential pillar to connect HDSLs to today's design flows.

This paper describes the Extendable Translating Instruction Set Simulator (ETISS). In addition to binary translation, ETISS features a plugin mechanism that allows to quickly include new functionality into the translation stage, the simulation loop, during accesses to the memory or whenever an interrupt is received. ETISS targets to become an advanced industrial-strength ISS with special focus on virtual prototypes (VPs) written in SystemC/TLM. In this paper, we will show examples of ETISS Plugins which include tracing tools, SystemC interfaces, closey-coupled peripherals or triggers for fault injection. A major drawback of developing a new binary translator such as ETISS is its lack of support for a variety of instruction set architectures (ISAs). At the moment ETISS supports the open-source OpenRISC orlk and partly RISC-V ISAs. Yet, in order to overcome this problem, we developed a toolchain to generate the binary translation stage for different ISAs following the MDA concept based on meta-modeling and code generation. It is planned to make ETISS available as an open-source tool to the research community.

The verification complexity of safety-critical systems on chip increased manifold after the introduction of ISO 26262, the safety standard for automotive applications. As a result, checkpoint-restore techniques have been implemented to speed-up fault-injection simulations of register-transfer level and gate-level models. However, these techniques are not suitable for safety verification, since they have high hard-disk space requirements, long generation time, and are mainly generated manually. To address these limitations, in this paper, we present a compiled-code-based snapshotting mechanism, which automatically generates an arbitrary amount of checkpoints post-simulation from a model's simulation traces. Our approach uses three to four orders of magnitude less hard-disk space than commercial tools and generates checkpoints 5x to 12x faster. Finally, fault-injection simulations with our approach run 6.75x to 27x faster than with commercial tools.

Safety-critical systems-on-chip currently undergo extensive fault-effect analyses. To meet the safety requirements of ISO 26262, most frequently fault-injection campaigns are per- formed. Due to the exponentially growing fault-verification space, faster simulation possibilities than enabled by register transfer (RT) and gate-level (GL) models are under investigation. Fault injection on virtual prototypes (VPs) is one measure to speed up simulation. However, VPs require the injection of complex abstract faults to observe the same effects of, for example, single- bit fault injection into GL models. As a consequence, VPs often suffer from injection of incorrect faults (i.e., faults whose effects cannot be reproduced on the RT or gate levels). Therefore, we developed an efficient approach to verify or falsify failures detected with VP fault simulation. As a result, incorrect faults are discovered early in the development phase helping to improve the design of accurate safety mechanisms. Moreover, the exclusion of incorrect faults from fault-effect analyses further improves the accuracy and efficiency of fault-injection campaigns. The benefit of the presented method has been validated using a medium-size controller design.

Formal techniques seem to be a way to cope with the exploding complexity of functional safety analysis. Here, the overall fault propagation probability to a certain safety-point in the design must be analyzed. As a consequence, the careful verification of the design is no longer sufficient. In addition, the propagation of all possible faults potentially showing up at all of the design's internal nodes must be validated. But this is not only a complexity challenge. Safety standards have a probabilistic view on functional safety analysis results and aspects such as different fault and pattern probability must be considered and related to requirements such as confidence level and maximum FIT rate. Following an overview on verification challenges around functional safety analysis, we introduce our innovative concept on how formal formal techniques can substantially simplify industrial functional safety analysis ows.

Circuit robustness can be increased with selective Flip-Flop hardening. Finding candidate sets of Flip-Flops for optimal selective hardening requires costly fault simulations, in particular if we consider safety properties stating that a bad state should never be reached in future. We present a fully symbolic formal method that gives a rigorous robustness measure without the need of extensive fault simulation and that can be applied in early design stages for selective hardening. Using Formal Verification, we define, compute and measure a set of “critical transitions”. The Markov Property is not required for the proposed method.

Several leading research groups name hardware generation as the next disruptive productivity improvement after IP-reuse. Metamodeling and code generation have already demonstrated a speedup by a factor 3× for the complete implementation phase of a chip. Furthermore, code size reduction by a factor of 3× was achieved with the hardware generation language (HGL) Chisel.

Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover's Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.

The need for safer and more robust hardware systems increased considerably in the automotive industry after the introduction of the safety standard ISO 26262. As a result, fault injection became a major verification milestone for safety-critical applications. However, safety-verification methods for gate level (GL) and RTL models suffer from long simulation time and large fault-injection campaigns due to the high complexity of large-scale SoCs. Virtual prototypes (VP) were employed to address the shortcomings of GL and RTL simulation, however fault injection into VPs usually leads to the observation of different failures than into GL and RTL models. In this paper, we present an approach which ensures 100% correlation of faults injected across VPs and GL models. Using a compiled-code approach, we transform GL net-lists into C++ code, which we then integrate into SystemC/TLM-based VPs. Thus, the new VPs have the same accuracy as the GL net-lists and are executed at near VP speed. Furthermore, since the new models share all fault-injection properties with the original GL net-lists, only realistic failures can be observed after fault injection.

Certifying an electrical/electronic system as functionally safe requires a range of analysis and assessment procedures, which must be performed during the different design and manufacturing phases. In the automotive context, the ISO 26262 standard prescribes a set of methods, including FMEDA (Failure Modes, Effects, and Diagnostic Analysis), to evaluate the safety integrity level of the product. FMEDA is a well-established technique in the industry, however, it still demands cumbersome and error-prone manual tasks.

The Universal Verification Methodology (UVM) has become a de facto standard in today's functional verification of digital designs. However, it is rarely used for the verification of Designs Under Test containing Real Number Models. This paper presents a new technique using UVM that can be used in order to compare models of analog circuitry on different levels of abstraction. It makes use of statistic metrics. The presented technique enables us to ensure that Real Number Models used in chip projects match the transistor level circuitry during the whole life cycle of the project.

Designing Automotive SoCs requires product specific support of one or more different design targets as different degrees of safety, reliability, very low power, or high current support as well as different design features as multi-core, sensor-on-chip, or system-in-package. Considering that wide design space, it's clear that EDA industry that is focusing on generic applicable tools leaves a wide field for automation unsupported.

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.

This paper presents an industry proven Metamodeling based approach to System-Level-Synthesis which is seen as generic design automation strategy above today's implementation levels RTL (for digital) and Schematic Entry (for analog). The approach follows a new synthesis paradigm: The designer develops a simple domain and/or design specific language and a smart tool synthesizing implementation level models according to its needs. The overhead of making both a tool and a model pays off since the tool building is automated by code generation and reuse, both based on Metamodeling techniques. Also the focus on owns demand keeps development costs low. Finally, specification data is utilized. I.e. the domain specific language simplifies to a document structure as a table. This keeps also modeling effort low since specification content is used and no model need to be built. Furthermore, increases design consistency and thus decreases debug time. Using these concepts, single design steps have been speed up to a factor of 20x and implementations of chips (specification-to-tapeout) have been speed up to a factor of 3x.

Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in today's SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures full system simulations (HW+SW) become a bottleneck reducing this benefit. Hence, it is necessary to develop modeling styles which allow for further abstraction beyond the currently applied TLM methodology. This paper introduces such a modeling style, referred to as TLM+. It enables a higher modeling abstraction through merging hardware dependent driver software at the lowest level with the HW interface. Thus, sequences of HW transactions can be merged to single HW/SW transactions while preserving both the HW architecture and the low-level to high-level SW interfaces. In order to maintain the ability to validate timing-critical paths, a new resource model concept is introduced which compensates the loss of timing information, induced by merging HW transactions. Experimental results show a speed-up of up to 1000x at a timing error of approximately 10%.

The complexity of hardware-dependent software (HdS) continuously grows faster than chip complexity since more and more tasks are moved to software. Clearly, the pressure on the development of new methodologies for early validation of HdS increases as well. Existing methods must be continuously improved and new methods must be developed. This is exemplified with an state-of-the-art transaction level (TL) model used for firmware development of a productive wireless communication chip. By discussing the strengths and shortcomings of TL modeling we derive a set of requirements for a future modeling paradigm, which led to the new data flow abstraction approach presented in this paper. Experiments showed that we gain up to 10 x performance improvement.

Effective integration of advanced systems-on-chip (SoC) requires extensive reuse of IP modules as well as automation of the IP integration process, including verification. Key enablers for this are standards to describe and package IP modules. We focus on the IP-XACT standards and demonstrate how these standards are deployed in three industrial IP integration flows. Further, we report on two future extensions to IP-XACT that are currently being explored in the SPRINT project, i.e. IP-XACT based verification software generation and IP-XACT based configuration of debug environments. We conclude that IP-XACT is enabling powerful IP integration methodologies and that future extensions can further increase the effectiveness of IP-XACT standards.

In recent years other verification features than simulation performance such as robustness and debugging gained increasing impact on simulation language and tool selection. However, fastest model execution speed is still priority number one for many design and verification engineers. This can be seen in the continuously growing interest in virtual prototypes and transaction level modeling (TLM). As part of the ongoing re-work modeling language strategies and the world wide introduction of TLM, a detailed analysis of the impact of description languages, abstraction layers and data types on simulation performance is of high importance. For the presented analysis, we considered five designs that have been modeled in VHDL, Verilog, SystemVerilog, and SystemC, using different value representations and coding styles, covering the abstraction levels from functional to behavioral to RTL. This paper presents our evaluation environment and several interesting findings of our analysis. The most important results are as follows: We found that HDL tool/language/abstraction selection of RTL models impacts on the execution speed with a factor of 4.4. We found that Verilog is on average 2times faster than VHDL for RTL models. We found that SystemC results in 10times slower RTL models than HDLs and surprisingly results in 2.6times slower TLM PV models than SystemVerilog. And we found finally that on average over all analyzed aspects SystemVerilog models are executed fastest

The latest development of hardware design and verification methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models are used for early prototyping and as reference models for the verification of their RTL representation. Hence, ensuring their quality is vital for the design process. Assertion based verification (ABV) has already given a good return of investment for RTL designs. We expect the same benefit from leveraging ABV on transaction level; however mapping RTL ABV methodology directly to TL poses severe problems due to the abstraction of time and different model of computation. In this paper we present requirements for TL ABV and introduce a conceptual language for specifying TL properties. We use a simple application example for illustrating the concepts and outline a possible SystemC execution model of the conceptual language.

Electronic system level (ESL) reflects the current trend in hardware design and verification towards abstraction levels higher than RTL referred to as transaction level (TL). Raising the abstraction level leads to reduced complexity compared to classical RTL modeling; however, due to this lack of detail, verification of higher level models produces new problems. Assertion based verification (ABV) - a well established RTL methodology - is a good example of this. Temporal relations in RTL properties are specified in terms of clocks that trigger the design. It is not obvious how to specify properties for more abstract, non-clocked models where the notion of lime is annotated as estimated delay values or omitted completely. Since ABV has already shown to be a strong methodology for functional RTL verification, we expect the same benefit for TL by lifting current ABV approaches to a higher level. In this paper we present a prototypic formal framework for specifying TL properties. We focus our work on three TL model views, as defined in the OSCI TLM standard. For each view we describe the model of computation and derive the required operators. Furthermore, we explain the required execution semantics and give some application examples.

The formal verification of assembler code using hardware verification tools requires memory components, which e.g. hold the code itself and the processed data. Since the count of variables to be proven usually rises with both data-size and address-space, complexity boundaries of formal tools can be reached quickly. Since bounded model checking (BMC) always involves a certain time window and therefore the count of memory accesses is limited, it is possible to optimize the applied memory as far as the address-space and the size in the count of gates is concerned. In this paper we introduce various memory models, which decrease the complexity of formal proofs by applying such optimizations. We provide examples of models with limitations either of the address-space or the amount of storable data. Our analysis shows that these models remarkably enhance the performance, while verifying the instruction-set of a given processor-unit with our in-house BMC-Tool

The tester-related simulation environment (TRSE) and applied methodology close the gap between physical test and simulation. Simulation checks the correctness of the implementation with respect to the specification, and test checks the correctness of the fabricated product with respect to the implementation. Unfortunately, simulation and test are still not connected in a smooth verification flow. Test cases and stimuli from simulation cannot be directly used for test. They may be used only in a restricted way, and after some adaptation. The approach presented here allows a better reuse of simulation stimuli for test issues. The main idea consists of inserting a special simulation element (SE) called a "transforming SE". This transforming SE is responsible for the adaptation and single cycle relation of the pattern. It also traces the interface pattern for direct use on a tester. These patterns are finally used for deriving test programs from functional patterns and for providing patterns for an e-beam analysis of the manufactured chip. The second main feature of the TRSE is the connection of each SE with an appropriate reference clock. This enables the SE to provide both synchronous and asynchronous communication with the unit under verification (UUV). Both the modeling of a test case and general methodology issues have a big influence in how easily a pattern can be adapted for the tester. Some practical modeling and methodology hints are given.

This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without loosing compatibility towith the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead.The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.

Novel test bench techniques are required to cope with afunctional test complexity which is predicted to grow muchmore strongly than design complexity. Our test benchapproach attacks this complexity by using a stronghierarchical architecture, application domain-independentsynchronization, reusable modules, and easy incrementalextendability based on table-driven techniques. In addition,the integration of VHDL/C co-simulation under the controlof the test bench makes it possible to use the hardware modelfor software testing and vice versa and thus enables extremereductions in test bench coding. The efficiency of our testbench has already been demonstrated in several industrialprojects, among them a four-ASIC ATM board with oneembedded core and one external micro controller.

In the area of hardware design, automata is often realized synchronously by a clocked state register, a next state logic block representing the state transition function, and an output logic block representing the output function. Assuming that combinatorial blocks of automata are already optimized, a further potential for timing optimization occurs, if two Moore automata interact sequentially, where the output of the first automata is the input of the second one. Processing of an event that occurs as input of the first automaton by both automata needs up to two clock cycles: at most one clock for producing an output of the first one, and one clock cycle to compute the final output by the second one. In this paper an algorithm is presented that allows to avoid one clock cycle in certain well defined situations.