In this article, we present a novel approach that seamlessly integrates machine learning (ML) algorithms into wearable technology through the use of weightless neural networks (WNNs) and flexible integrated circuits (FlexICs). Our methodology employs combinational intelligent networks (COIN) for edge inference on resource-constrained devices, highlighting the advantages of WNNs in terms of power efficiency and minimal hardware requirements. We propose an automated design flow for implementing COIN as FlexICs aimed at developing scalable, cost-effective, and environmentally sustainable wearable monitoring solutions. As a proof-of-concept demonstrator, an arrhythmia detection FlexIC was fabricated using COIN to meet the stringent requirements of medium-complexity wearable applications, offering a promising path toward personalized and accessible healthcare solutions.

Deploying fast, accurate, and efficient machine learning on edge devices remains a key research challenge. While deep neural networks (DNNs) excel in vision tasks, their computational and storage demands hinder deployment on resourceconstrained hardware. Optimization strategies such as quantization, sparsity induction, and multiplication-free architectures have been explored to address these challenges. Weightless Neural Networks (WNNs), based on look-up tables, offer high energy efficiency and low-latency inference, making them attractive for edge applications. However, WNNs struggle with complex vision tasks due to their lack of support for positional invariance. To enable machine learning models that are both lightweight and accurate for edge inference, we propose a hybrid weightless neural network model (H-WNN) that integrates the efficiency of WNNs with the spatial feature extraction capabilities of quantized convolution. FPGAs serve as an ideal platform for exploring the hybrid approach, as they facilitate efficient design space exploration for quantized convolution, allow direct mapping of look-up tables in WNNs, and enable seamless integration of both models. We additionally present a workflow to explore hardwareaccuracy tradeoffs for H-WNN models on hardware platforms. We evaluate H-WNN on multiple classification datasets relevant to edge applications and compare them against similar existing studies, such as FINN-R and DWN. Across the benchmarks, our results consistently demonstrate that H-WNN achieves lower resource usage and latency while maintaining competitive accuracy and throughput. For example, on CIFAR-10, H-WNN achieves 87.72 % accuracy while being$2 \times$smaller than competing approaches at the same throughput, resulting in improved energy efficiency.

We introduce the Differentiable Weightless Neural Network (DWN), a model based on interconnected lookup tables. Training of DWNs is enabled by a novel Extended Finite Difference technique for approximate differentiation of binary values. We propose Learnable Mapping, Learnable Reduction, and Spectral Regularization to further improve the accuracy and efficiency of these models. We evaluate DWNs in three edge computing contexts: (1) an FPGA-based hardware accelerator, where they demonstrate superior latency, throughput, energy efficiency, and model area compared to state-of-the-art solutions, (2) a low-power microcontroller, where they achieve preferable accuracy to XGBoost while subject to stringent memory constraints, and (3) ultra-low-cost chips, where they consistently outperform small models in both accuracy and projected hardware area. DWNs also compare favorably against leading approaches for tabular datasets, with higher average rank. Overall, our work positions DWNs as a pioneering solution for edge-compatible high-throughput neural networks.

As Deep Neural Networks become more complex and computationally demanding, efficient models for inference at the edge, particularly multiplication-free ones, have gained significant attention. The Ultra Low-Energy Edge Neural Network (ULEEN) is a notable architecture optimized for high throughput edge designs. ULEEN uniquely employs Bloom Filters with binary values to compute neuron activation, boasting better efficiency metrics than Binary Neural Networks (BNNs). This work uncovers a gradient back-propagation bottleneck within ULEEN’s Bloom filters and introduces a simplified version of it as a solution: the "Soon Filter". Both theoretically and empirically, we demonstrate that our approach improves gradient back-propagation efficiency. Tests on MLPerf Tiny, MNIST and various UCI datasets reveal that our method surpasses ULEEN, BNN, and DeepShift. Notably, with MLPerf KWS (Key Word Spotting) dataset, we achieve 69.6% accuracy with only 101KiB, while ULEEN, BNN and DeepShift achieve only 67.4%, 55.9%, and 24.9% respectively. Remarkably, we also achieve 67.7% accuracy with only 50KiB, resulting in a 2x model size reduction compared to ULEEN while maintaining similar accuracy (+0.3%). This results underscores the promising potential of our solution for efficient inference at the edge in applications that rely on high throughput architectures.

We introduce Combinational Intelligent Networks (COIN), a machine learning technique that targets edge inference using low-resourced FPGAs or ASICs. COIN is an improvement on LogicWiSARD, a recent weightless neural network that achieves low power, small area, and high throughput. We convert the LogicWiSARD model into a binary neural network, train it using backpropagation, and then convert it to a COIN model. As a result, COIN can achieve higher accuracy than LogicWiSARD or it can require significantly fewer hardware resources when comparing models with similar accuracies. In comparison to a BNN implementation, FINN, small and large COIN models are more energy efficient demonstrating up to 11.5x higher inferences/Joule at similar accuracy. Our tool executes the complete flow, from training to RTL. and is publicly available.

Weightless neural networks are recognized for their online learning capacity and competitive performance with the state-of-the-art in different scenarios.Despite this, the literature has not adequately explored the potential of classification ensembles based on these models and their unique characteristics.This study introduces three types of ensembles based on the WiSARD weightless model and evaluates their effectiveness.The results show that these ensembles significantly improve accuracy compared to the WiSARD model and its ClusWiSARD extension, with a reasonable increase in computational cost.Furthermore, using ensembles eliminates the need for time-consuming tie-break policies of traditional WiSARD models.

Photovoltaic(PV) systems are one of the leading technologies to address climate change.Tracking systems improve energy generation by moving the surface to follow the sun's position however, these methods do not ensure optimal results in cloudy environments.This article proposes a closed-loop control algorithm for tracking based on reinforcement learning and weightless neural networks, compared to an astrological model.The method was applied in a single PV array on a single-axis tracking system, simulated with PVLib.Results showed that the architecture could improve results in cloudy environments but not in a clear-sky situation, as expected for a first approach.

Algorithms for mobile networking are increasingly being moved from centralized servers towards the edge in order to decrease latency and improve the user experience. While much of this work is traditionally done using ASICs, 6G emphasizes the adaptability of algorithms for specific user scenarios, which motivates broader adoption of FPGAs. In this paper, we propose the FPGA-based Weightless Intrusion Warden (FWIW), a novel solution for detecting anomalous network traffic on edge devices. While prior work in this domain is based on conventional deep neural networks (DNNs), FWIW incorporates a weightless neural network (WNN), a table lookup-based model which learns sophisticated nonlinear behaviors. This allows FWIW to achieve accuracy far superior to prior FPGA-based work at a very small fraction of the model footprint, enabling deployment on small, low-cost devices. FWIW achieves a prediction accuracy of 98.5% on the UNSW-NB15 dataset with a total model parameter size of just 192 bytes, reducing error by 7.9x and model size by 262x vs. LogicNets, the best prior edge-optimized implementation. Implemented on a Xilinx Virtex UltraScale+ FPGA, FWIW demonstrates a 59x reduction in LUT usage with a 1.6x increase in throughput. The accuracy of FWIW comes within 0.6% of the best-reported result in literature (Edge-Detect), a model several orders of magnitude larger. Our results make it clear that WNNs are worth exploring in the emerging domain of edge networking, and suggest that FPGAs are capable of providing the extreme throughput needed.

‘‘Extreme edge” 1 devices, such as smart sensors, are a uniquely challenging environment for the deployment of machine learning. The tiny energy budgets of these devices lie beyond what is feasible for conventional deep neural networks, particularly in high-throughput scenarios, requiring us to rethink how we approach edge inference. In this work, we propose ULEEN, a model and FPGA-based accelerator architecture based on weightless neural networks (WNNs). WNNs eliminate energy-intensive arithmetic operations, instead using table lookups to perform computation, which makes them theoretically well-suited for edge inference. However, WNNs have historically suffered from poor accuracy and excessive memory usage. ULEEN incorporates algorithmic improvements and a novel training strategy inspired by binary neural networks (BNNs) to make significant strides in addressing these issues. We compare ULEEN against BNNs in software and hardware using the four MLPerf Tiny datasets and MNIST. Our FPGA implementations of ULEEN accomplish classification at 4.0–14.3 million inferences per second, improving area-normalized throughput by an average of 3.6× and steady-state energy efficiency by an average of 7.1× compared to the FPGA-based Xilinx FINN BNN inference platform. While ULEEN is not a universally applicable machine learning model, we demonstrate that it can be an excellent choice for certain applications in energy- and latency-critical edge environments.

Weightless neural networks (WNNs) are a class of machine learning model which use table lookups to perform inference, rather than the multiply-accumulate operations typical of deep neural networks (DNNs). Individual weightless neurons are capable of learning non-linear functions of their inputs, a theoretical advantage over the linear neurons in DNNs, yet state-of-the-art WNN architectures still lag behind DNNs in accuracy on common classification tasks. Additionally, many existing WNN architectures suffer from high memory requirements, hindering implementation. In this paper, we propose a novel WNN architecture, BTHOWeN, with key algorithmic and architectural improvements over prior work, namely counting Bloom filters, hardware-friendly hashing, and Gaussian-based nonlinear thermometer encodings. These enhancements improve model accuracy while reducing size and energy per inference. BTHOWeN targets the large and growing edge computing sector by providing superior latency and energy efficiency to both prior WNNs and comparable quantized DNNs. Compared to state-of-the-art WNNs across nine classification datasets, BTHOWeN on average reduces error by more than 40% and model size by more than 50%. We demonstrate the viability of a hardware implementation of BTHOWeN by presenting an FPGA-based inference accelerator, and compare its latency and resource usage against similarly accurate quantized DNN inference accelerators, including multi-layer perceptron (MLP) and convolutional models. The proposed BTHOWeN models consume almost 80% less energy than the MLP models, with nearly 85% reduction in latency. In our quest for efficient ML on the edge, WNNs are clearly deserving of additional attention.

Weightless neural networks (WNNs) are an alternative pattern recognition technique where RAM nodes function as neurons. As both training and inference require mostly table lookups, few additions, and no multiplications, WNNs are suitable for high-performance and low-power embedded applications. This work introduces a novel approach to implement WiSARD, the leading WNN state-of-the-art architecture, completely eliminating memories and arithmetic circuits and utilizing only logic functions. The approach creates compressed minimized implementations by converting trained WNN nodes from lookup tables to logic functions. The proposed LogicWiSARD is implemented in FPGA and ASIC technologies to illustrate its suitability for edge inference. Experimental results show more than 80% reduction in energy consumption when the proposed LogicWiSARD model is compared with a multilayer perceptron network (MLP) of equivalent accuracy. Compared to previous work on FPGA implementations for WNNs, convolutional neural networks, and binary neural networks, the energy savings of LogicWiSARD range between 32.2% and 99.6%.

The binary encoding of real valued inputs is a crucial part of Weightless Neural Networks.The Linear Thermometer and its variations are the most prominent methods to determine binary encoding for input data but, as they make assumptions about the input distribution, the resulting encoding is sub-optimal and possibly wasteful when the assumption is incorrect.We propose a new thermometer approach that doesn't require such assumptions.Our results show that it achieves similar or better accuracy when compared to a thermometer that correctly assumes the distribution, and accuracy gains up to 26.3% when other thermometer representations assume an unsound distribution.

Weightless neural networks (WNNs) are a type of machine learning model which perform prediction using lookup tables (LUTs) instead of arithmetic operations.Recent advancements in WNNs have reduced model sizes and improved accuracies, reducing the gap in accuracy with deep neural networks (DNNs).Modern DNNs leverage "pruning" techniques to reduce model size, but this has not previously been explored for WNNs.We propose a WNN pruning strategy based on identifying and culling the LUTs which contribute least to overall model accuracy.We demonstrate an average 40% reduction in model size with at most 1% reduction in accuracy.

Conditional branch prediction is a technique used to speculatively execute instructions before knowing the direction of conditional branch statements. Perceptron-based predictors have been extensively studied, however, they need large input sizes for the data to be linearly separable. To learn nonlinear functions from the inputs, we propose a conditional branch predictor based on the WiSARD model and compare it with two state-of-the-art predictors, the TAGE-SC-L and the Multiperspective Perceptron. We show that the WiSARD-based predictor with a smaller input size outperforms the perceptron-based predictor by about 0.09% and achieves similar accuracy to that of TAGE-SC-L.

Next-generation networks will provide intelligent infrastructure and management using machine learning. In real-world applications, demand for resources and performance within a service class may vary over time. Infrastructure providers choose which requests to accept with the goal of long-term profit maximization – a process known as slice admission control. In this paper, we envision a dynamic system with varying service requests attributes in urgency, duration, and amount of resources (i.e., computing, network, and storage). Further, we develop a dynamic pricing model that is responsive to demand and supply resulting in demand and supply reserve shaping. Then, we propose a solution to the slice admission control problem by using a reinforcement learning approach with Deep-Q Networks, where the state of the system is modeled using an array of parameters, similar to the input matrix in computer vision. Results show that our computer vision-inspired approach is capable of learning how the better policy to navigate this complex environment by selecting service requests that maximize the provider’s long-term profit.

This paper proposes a weightless architecture for graph classification scenarios.This architecture is a three-headed arrangement composed of graph hand-picked features, a quantization method and a final classifier.Although multiple new strategies for graph classification have been proposed in recent years, it is still necessary to settle comparable studies with respect to weightless neural networks.The proposed architecture is evaluated along with other baseline classifiers and independent strategies, showing that weightless architectures are able to compete with other well-established methods such as graph kernels.* This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior -Brasil (CAPES) -Finance Code 001, CNPq, FAPERJ and DIPPG -CE-FET/RJ.

n-tuple neural networks have been in the past applied to a wide range of learning domains.However, for the particular area of regression, existing systems have displayed two shortcomings: little flexibility in the objective function being optimized and an inability to handle nonstationarity in an online learning setting.A novel n-tuple system is proposed to address these issues.The new architecture leverages the idea of functional gradient descent, drawing inspiration from its use in kernel methods.Furthermore, its capabilities are showcased in two reinforcement learning tasks, which involves both nonstationary online learning and task-specific objective functions.

This special issue of Concurrency and Computation: Practice and Experience comprises four papers extending the original workshop publications accepted and presented at MPP 2019 (8th Workshop on Parallel Programming Models – Special Issue on IoT and Machine Learning), held in Rio de Janeiro in conjunction with IPDPS 2019. The papers represent interesting research ideas of parallel programming models, tools, and optimizations suited for being applied to IoT-based applications. The paper titled “Enabling Heterogeneous Ray-Tracing Acceleration in Edge/Cloud Architectures” represents a very interesting research on reconfigurable accelerators for Ray-Tracing, specialized in computing ray-triangle intersections at the network edge of a heterogeneous cloud computing environment. The authors validated their approach on the Xilinx Zynq FPGA platform. The paper titled “An Incremental Reinforcement Learning Scheduling Strategy for Data-Intensive Scientific Workflows in the Cloud” is a research work proposing a new scheduling algorithm based on Reinforcement Learning for scientific workflows on HPC distributed resources and Clouds. The paper titled “Latency-aware Adaptive Micro-Batching Techniques for Streamed Data Compression on GPUs” proposes a set of Autonomic Computing strategies for configuring the optimal parallelism degree and batch size on streaming data compression parallel applications on GPU architectures. Finally, the paper titled “Gamma – General Abstract Model for Multiset mAnipulation and Dynamic Dataflow Model: an Equivalence Study” is an interesting research study on new applications of the Gamma Model (General Abstract Model for Multiset mAnipulation) and its joint utilization with the Dataflow programming model. As Guest Editors, we would like to express our gratitude for the valuable contributions made by all authors. We would like to thank all the reviewers who helped us during the thorough review process based on several review rounds. Finally, we would like to thank all the editorial board members and all staff of Concurrency and Computation: Practice and Experience for allowing us to publish our Special Issue and for their invaluable support during the whole publication process.

Abstract With the increase of the search for computational models where the expression of parallelism occurs naturally, some paradigms arise as options for the current generation of computers. In this context, dynamic dataflow and Gamma—GeneralAbstractModel forMultiset mAnipulation—emerge as interesting computational model choices. In dynamic dataflow model, operations are performed as soon as their associated operands are available, without rely on a Program Counter to dictate the execution order of instructions. The Gamma paradigm is based on a parallel multiset rewriting scheme. It provides a nondeterministic execution model inspired by anabstract chemical machinemetaphor, where operations are formulated as reactions that occur freely among matching elements belonging to the multiset. In this work, equivalence relations between the dynamic dataflow and Gamma paradigms are exposed and explored, while methods to convert from dataflow to Gamma paradigm and vice versa are provided. It is shown that vertices and edges of a dynamic dataflow graph can correspond, respectively, to reactions and multiset elements in the Gamma paradigm. This work provides the scientific community with the possibility of taking profit of both parallel programming models, contributing with a versatility component to researchers and developers.

Abstract Scheduling by Edge Reversal provides an order of operation for nodes in a graph, but maximizing or minimizing the resulting concurrency is hard. In this paper, we discuss a series of real‐world applications for this technique and propose algorithms for both problems. For maximum concurrency, we prove its general inapproximability and introduce approximation algorithms for classes of graphs. For minimum concurrency, we use hardness and inapproximability results to establish its relation to longest cycles, while also introducing a novel application for assembling musical phrases.

Dynamic Information Flow Tracking has been successfully used to prevent a wide range of attacks and detect illegal access to sensitive information. Most proposed solutions only track the explicit information flow where the taint is propagated through data dependencies. However, recent evasion attacks exploit implicit flows, that use control flow in the application, to manipulate the data thus making the malicious activity undetectable. We propose NIFT - a nested implicit flow tracking mechanism that extends explicit propagation to instructions affected by a control dependency. Our technique generates taint instructions at compile time which are executed by specialized hardware to propagate taint implicitly even in cases of deeply-nested branches. In addition, we propose a restricted taint propagation for data executed in conditional branches that affects only immediate instructions instead of all instructions inside the branch scope. Our technique efficiently locates implicit flows and resolves them with negligible performance overhead. Moreover, it mitigates the over-tainting problem.

Among the existing computational parallel models, Gamma and Dynamic Dataflow are equivalent models where parallel programs can be developed in a natural way. However, the implementation of Gamma paradigm poses several communication and architectural challenges. On the other hand, interest-based protocols have emerged as possible solutions of communication routing enabling an efficient communication in IoT environments. An interesting property of Gamma is the possibility of locality exploration in a non-complex way that sounds quite suitable for IoT applications. This work proposes a novel execution model for Gamma programs integrating the Radnet --- an interest-based protocol --- as communication protocol. Since the interest processing using Gamma paradigm is not a trivial task, a dynamic dataflow graph is used to express the interest as edges between vertices. We explore the equivalence results between Gamma and dataflow and, also, provide experiments showing the potential of Gamma when used to implement approximate computing techniques.

This work takes into account the benefits of machine learning in order to estimate the valence of emotions on the OMG Empathy dataset, considering the information obtained from face expressions and dialogue of interlocutors. RegressionWiSARD and ClusRegressionWiSARD n-tuple regressors and its ensembles were employed to this end. The best performance achieved among all the combinations of weightless neural models considered (evaluated using the CCC metric) was 0.25 in validation set of the Personalized Track.

The growing volume of data produced continuously in the Cloud and at the Edge poses significant challenges for large-scale AI applications to extract and learn useful information from the data in a timely and efficient way. The goal of this article is to explore the use of computational storage to address such challenges by distributed near-data processing. We describe Newport, a high-performance and energy-efficient computational storage developed for realizing the full potential of in-storage processing. To the best of our knowledge, Newport is the first commodity SSD that can be configured to run a server-like operating system, greatly minimizing the effort for creating and maintaining applications running inside the storage. We analyze the benefits of using Newport by running complex AI applications such as image similarity search and object tracking on a large visual dataset. The results demonstrate that data-intensive AI workloads can be efficiently parallelized and offloaded, even to a small set of Newport drives with significant performance gains and energy savings. In addition, we introduce a comprehensive taxonomy of existing computational storage solutions together with a realistic cost analysis for high-volume production, giving a good big picture of the economic feasibility of the computational storage technology.

Physically unclonable functions (PUFs) have emerged as lightweight hardware security primitives for implementing secure authentication. Strong PUFs rely on random manufacturing process variation to create unique Boolean mappings from input (challenge) to output (output). For secure authentication, challenge to response mappings are required to be unique for each device. However, uniqueness is not guaranteed by design or manufacturing. Testing for uniqueness and weeding out non-unique parts are the only way to ensure uniqueness of devices. Uniqueness testing can be expensive in time as the challenge-responses of the N th device under-test, must be proven to be different from previously tested N - 1 devices, or the device must be discarded. To reduce the time complexity of uniqueness testing, Multi-Index hashing (MIH) was proposed for online testing in high volume manufacturing. Database search using MIH was shown to be fast, but it suffers from high memory cost. In this paper, we address the memory problem of MIH based uniqueness testing by proposing alternative MIH strategies. Our results indicate that the proposed search strategies can significantly reduce the memory cost without sacrificing performance, requiring ≈ 3.35× less memory with just a 17% performance overhead when testing the uniqueness of 1 million PUFs.

As services based on Machine Learning (ML) applications find increasing use, there is a growing risk of attack against such systems. Recently, adversarial machine learning has received a lot of attention, where an adversary is able to craft an input or manipulate an input to cause an ML system to misclassify. Another attack of concern is when an adversary with access to a ML model can reverse engineer attributes of a target class, creating a privacy concern, which is the subject of this paper. Such attacks use non-sensitive data obtainable by the adversary and the confidence levels returned by the ML model to infer sensitive attributes of the target user. Model Inversion attacks may be classified as white-box, where the ML model is known to the attacker, or black-box, where the adversary does not know the internals of the model. If the attacker has access to non-sensitive data of a target user, they can infer sensitive data by applying gradient ascent on the confidence returned by the model. Therefore, a black-box attack can be mounted by numerical approximations of the gradient to perform the gradient ascent. In this work, we present MLPrivacyGuard, a countermeasure against black-box model inversion attack is presented. This countermeasure consists of adding controlled noise to the output of the confidence function. It is important to preserve the accuracy of prediction/classification for the real users of the model while preventing attackers to infer sensitive data. This involves a trade-off between misclassification error and the effectiveness of defense. Based on experimental results, we demonstrate that when noise is injected with a long-tailed distribution, the objectives of low misclassification error with a strong defense can be attained as model inversion attacks are neutralized because numerical approximation of gradient ascent is unable to converge.

AI applications have recently driven the computer architecture industry towards novel and more efficient dedicated hardware accelerators and tools. Weightless Neural Networks (WNNs) is a class of Artificial Neural Networks (ANNs) often applied to pattern recognition problems. It uses a set of Random Access Memories (RAMs) as the main mechanism for training and classifying information regarding a given input pattern. Due to its memory-based architecture, it can be easily mapped onto hardware and also greatly accelerated by means of a dedicated Register Transfer-Level (RTL) architecture designed to enable multiple memory accesses in parallel. On the other hand, a straightforward WNN hardware implementation requires too much memory resources for both ASIC and FPGA variants. This work aims at designing and evaluating a Weightless Neural accelerator designed in High-Level Synthesis (HLS). Our WNN accelerator implements Hash Tables, instead of regular RAMs, to substantially reduce its memory requirements, so that it can be implemented in a fairly small-sized Xilinx FPGA. Performance, circuit-area and power consumption results show that our accelerator can efficiently learn and classify the MNIST dataset in about 8 times faster than the system's embedded ARM processor.

Summary In a program, there is usually a significant amount of instructions that are repeatedly executed with the same inputs during the execution. This redundancy allows the reuse of previous computations, potentially reducing the program execution time. The Dynamic Trace Memoization technique (DTM) was proposed to exploit the reuse of a dynamic sequence of redundant instructions for superscalar CPUs. This paper proposes the application of the DTM technique on a GPU architecture. We propose the DTM@GPU model that adapts the original DTM technique to the NVIDIA GPU architecture by introducing architectural modifications and the identification of different trace reuse styles in multithreaded environments. We investigate reuse opportunities in real‐world GPU applications and the potential performance gains. We also perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%.

Summary Instruction Reuse is a technique adopted in Von Neumann architectures that improves performance by avoiding redundant execution of instructions when the result to be produced can be obtained by searching an input/output memoization table for such instruction. Trace reuse can be applied to traces of instructions in a similar fashion. However, those techniques are yet to be studied in the context of the Dataflow model, which has been gaining traction in the high performance computing community due to its inherent parallelism. Dataflow programs are represented by directed graphs where nodes are instructions or tasks and edges denote data dependencies between tasks. This work presents Dataflow Dynamic Task Memoization (DF‐DTM), a technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF‐DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. Moreover, this paper evaluates how reuse rates can be affected by limiting subgraph size, memoization table size, task granularity, and problem size, showing that DF‐DTM can yield good reuse rates in more realistic environments.

The Wilkie, Stonham, and Aleksander recognition device (WiSARD) [Formula: see text]-tuple classifier is a multiclass weightless neural network capable of learning a given pattern in a single step. Its architecture is determined by the number of classes it should discriminate. A target class is represented by a structure called a discriminator, which is composed of [Formula: see text] RAM nodes, each of them addressed by an [Formula: see text]-tuple. Previous studies were carried out in order to mitigate an important problem of the WiSARD [Formula: see text]-tuple classifier: having its RAM nodes saturated when trained by a large data set. Finding the VC dimension of the WiSARD [Formula: see text]-tuple classifier was one of those studies. Although no exact value was found, tight bounds were discovered. Later, the bleaching technique was proposed as a means to avoid saturation. Recent empirical results with the bleaching extension showed that the WiSARD [Formula: see text]-tuple classifier can achieve high accuracies with low variance in a great range of tasks. Theoretical studies had not been conducted with that extension previously. This work presents the exact VC dimension of the basic two-class WiSARD [Formula: see text]-tuple classifier, which is linearly proportional to the number of RAM nodes belonging to a discriminator, and exponentially to their addressing tuple length, precisely [Formula: see text]. The exact VC dimension of the bleaching extension to the WiSARD [Formula: see text]-tuple classifier, whose value is the same as that of the basic model, is also produced. Such a result confirms that the bleaching technique is indeed an enhancement to the basic WiSARD [Formula: see text]-tuple classifier as it does no harm to the generalization capability of the original paradigm.

Open set recognition is a classification-like task. It is accomplished not only by the identification of observations which belong to targeted classes (i.e., the classes among those represented in the training sample which should be later recognized) but also by the rejection of inputs from other classes in the problem domain. The need for proper handling of elements of classes beyond those of interest is frequently ignored, even in works found in the literature. This leads to the improper development of learning systems, which may obtain misleading results when evaluated in their test beds, consequently failing to keep the performance level while facing some real challenge. The adaptation of a classifier for open set recognition is not always possible: the probabilistic premises most of them are built upon are not valid in a open-set setting. Still, this paper details how this was realized for WiSARD a weightless artificial neural network model. Such achievement was based on an elaborate distance-like computation this model provides and the definition of rejection thresholds during training. The proposed methodology was tested through a collection of experiments, with distinct backgrounds and goals. The results obtained confirm the usefulness of this tool for open set recognition.

Code execution in modern superscalar processors is inherently redundant. Many instructions execute repeatedly with the same inputs, producing the same outputs, thus wasting resources in the process. Value reuse techniques memorize previous executions of instructions, blocks or traces which may be reused if they appear again with the same input contexts. Although trace reuse techniques show great potential for both performance and energy consumption improvement, they have not been studied yet in one of the most widely available computer architectures - the ARM architecture. In this paper, the main issues with reusing traces in instruction sets with conditional execution are revisited. Afterwards, the reuse potential in the benchmark suite MiBench is analyzed varying (i) how traces are generated, and (ii) the size of reuse tables. Our results show that a memoization table of 32 KiB allows to reuse 18.36% of the total instructions on average.

In this study, we propose a variation of the RAdNet for vehicular environments (RAdNet-VE). The proposed scheme extends the message header, mechanism for registering interest, and message forwarding mechanism of RAdNet. Based on results obtained from simulation experiments, we compare the performance of RAdNet-VE against that of RAdNet, a basic content-centric network (CCN) using reactive data routing, (CCNr), and a basic CCN using proactive data routing, CCNP. These CCNs provide non-cacheable data services. Moreover, the communication radio standards adopted in the scenarios 1 and 2 were respectively IEEE 802.11n and IEEE 802.11p. The results shown that the performance of the RAdNet-VE was superior to than those of RAdNet, CCNRand CCNP. In this sense, RAdNet-VE protocol (RVEP) presented low communication latencies among nodes of just 20.4ms (scenario 1) and 2.87 ms (scenario 2). Our protocol also presented high data delivery rates, i.e, 83.05% (scenario 1) and 88.05% (scenario 2). Based on these and other results presented in this study, we argue that RAdNet-VE is a feasible alternative to CCNs as information-centric network (ICN) model for VANET, because the RVEP satisfies all of the necessary communication requirements.

Music tracking is a useful technique for many music related tasks. Some applications include evaluating musicians performance, automatic score page turning and syncing music lyrics. In this work, we describe a WiSARD-based system for real-time music tracking and evaluate the performance of the corresponding implementation. Given any audio example, the system is capable of recognizing which point of the original signal is currently playing and of dynamically tracking it. In other words, if the music restarts or jumps to another position, the system is capable of following it. This is accomplished thanks to the low complexity training and classifying of the models used, which continually keep track of all possible points of the music, and not only of the current neighboring region. Experiments are provided in order to analyze the performance of the system in three test scenarios: tracking continuous playing, tracking multiple jumps and self predicting errors. The final results demonstrate that the system is efficient even when applied to musics with some level of repetitions and short periods of silence.

Open set recognition is, more than an interesting research subject, a component of various machine learning applications which is sometimes neglected: it is not unusual the existence of learning systems developed on the top of closed-set assumptions, ignoring the error risk involved in a prediction. This risk is strictly related to the location in feature space where the prediction has to be made, compared to the location of the training data: the more distant the training observations are, less is known, higher is the risk. Proper handling of this risk can be necessary in various situation where classification and its variants are employed. This paper presents an approach to open set recognition based on an elaborate distance-like computation provided by a weightless neural network model. The results obtained in the proposed test scenarios are quite interesting, placing the proposed method among the current best ones.

In this work, a generalized central pattern generator (CPG) model is formulated to generate a full range of gait patterns for a hexapod insect. To this end, a recurrent neural network module, as the building block for rhythmic patterns, is proposed to extend the concept of oscillatory building blocks (OBB) for constructing a CPG model. The model is able to make transitions between different gait patterns by simply adjusting one model parameter. Simulation results are further presented to show the effectiveness and performance of the CPG network.

Custom Instruction Identification is an important part in the design of efficient Application-Specific Processors (ASIPs). It consists of profiling of a given application to find patterns of basic operations that are frequently executed. Operations of such patterns can be implemented together as a single custom instruction to speedup the execution of the application. Because of the problem's high complexity, several methods have been proposed for specific single-issue (RISC) processors and architectures, limiting the shape and size of custom instructions that can actually be identified and, possibly, implemented. In this paper, we propose and discuss an efficient custom instruction set identification method and corresponding automatic tool for multi-issue VLIW ASIPs, which search for the common operation patterns of the most frequently executed basic blocks of a given application, with different sizes and shapes. The speedup results for the custom instructions identified by our tool are provided for a set of benchmark applications. The speedup is up to 68%, with only a few custom instructions used.

The processor industry is well on its way towards manycore processors that comprise of large number of simple cores. The shift towards multi and manycores calls for new programming paradigms suitable for exploiting the inherent parallelism in applications. Dataflow execution was shown to be a good option for programming in such environments. It is well-known that as CMOS technology continues to scale, it becomes more prone to transient and permanent hardware faults. In this paper we present a novel mechanism for error detection and recovery that focuses on transient errors in dataflow execution. Due to the inherently parallel nature of dataflow, our solution is completely distributed and synchronizes only cores that have data dependencies between them, as opposed to prior work on error recovery that in general rely on global synchronization of the system. We evaluate the proposed solution via a software implementation on top of a dataflow runtime. Experimental results show that error detection overhead is highly related to the pressure on the memory bus. In memory bound applications, performance is found to deteriorate, while for other benchmarks, the observed overhead is less than 23%. We find no comparable previous work to contrast these results.

SUMMARY: Protein identification by mass spectrometry is commonly accomplished using a peptide sequence matching search algorithm, whose sensitivity varies inversely with the size of the sequence database and the number of post-translational modifications considered. We present the Spectrum Identification Machine, a peptide sequence matching tool that capitalizes on the high-intensity b1-fragment ion of tandem mass spectra of peptides coupled in solution with phenylisotiocyanate to confidently sequence the first amino acid and ultimately reduce the search space. We demonstrate that in complex search spaces, a gain of some 120% in sensitivity can be achieved. AVAILABILITY: All data generated and the software are freely available for academic use at http://proteomics.fiocruz.br/software/sim. CONTACT: [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

The reproduction of the movements of a ship by automated platforms, without the use of sensors providing exact data related to the numeric variables involved, is a non-trivial matter. The creation of an artificial vision system that can follow the cadence of said ship, in six axes of freedom, is the goal of this research. Considering that a real time response is a requisite in this case, it was decided to adopt a Boolean artificial neural network system that could identify and follow arbitrary interest points that could define, as a group, a model of the movement of an observed vessel. This paper describes the development of a prototype based on the Boolean perceptron model WiSARD (Wilkie, Stonham and Aleksander's Recognition Device), that is being implemented in the C programming language on a desktop computer using a regular webcam as input.

In this paper, we propose an architecture, which we call GridRT, capable of dealing with the main features, such as shadows and reflections effects, of Ray Tracing used for rendering three-dimensional scenes. This architecture achieves an efficient overall performance yet using a simple and compact massively parallel design. The design exploits the usage of Xilinx®Floating Point Operator IP Core and the spatial data structure of Regular Grids.

The WaveScalar is the first dataflow architecture that can efficiently provide the sequential memory semantics required by imperative languages. This work presents a speculative memory disambiguation mechanism for this architecture, the transaction WaveCache. Our mechanism maintains the execution order of memory operations within blocks of code, called waves, but adds the ability to speculatively execute, out-of-order, operations from different waves. This mechanism is inspired by progress in supporting transactional memories. Waves are considered as atomic regions and executed as nested transactions. Wave that have finished the execution of all their memory operations are committed, as soon as the previous waves are also committed. If a hazard is detected in a speculative wave, all the following waves (children) are aborted and re-executed. We evaluated the transactional WaveCache on a set of benchmarks from Spec 2000, Mediabench and Mibench (telecomm). Speedups ranging from 1.31 to 2.24 (related to the original WaveScalar) where observed when the benchmark doesn't perform lots of emulated function calls or access memory very often. Low speedups of 1.1 to slowdowns of 0.96 were observed when the opposite happens or when the memory concurrency was high.

This paper presents the implementation of ARQ-PROP II, a limited-depth propositional neural reasoner based on the Resolution Principle. The SATyrus platform was used in the synthesis of Energy functions from a set of pseudo-Boolean constraints specifying ARQ-PROP II architectures for different inferencing depths. Global minima of the Energy functions produced by SATyrus are associated to SATisfiability of a formula and, in the case of ARQ-PROP II, are associated to Resolution-based refutations. This allows for simplified abduction, prediction and planning to be unified with deduction in a goal-driven style, i.e. there is no need for presetting a reasoning style upon a target set of clauses. Experimental results on deduction with ARQ-PROP II using different propositional depth settings are presented together with a correction of Gadi Pinkas' mapping of SATisfiability into Energy minima.

Service-oriented computing (SOC) is the computational paradigm that utilizes services as fundamental elements to develop applications/solutions. To build a service model, SOC relies on the service-oriented architecture (SOA), which is a way of reorganizing software applications and infrastructures in a set of interacting services. This paper proposes a layered architectural model of the abstraction levels needed in the construction of mobile services platforms. Each one of theses layers has been defined based on SOC requirements and delivers the functionality needed to the creation of autonomous reconfiguring distributed systems.

Notwithstanding all the technology being invested in education, students still have to cope with a massive input of instructional information. However, many insulated initiatives from education community have been put forward. Each initiative by itself may not suffice to change the education landscape. To achieve any noticeable effect, several applications should be brought together into a single application. We propose an enabling technology to involve students in the construction of their own pedagogic content. The idea consists of a game where students participate both as players and constructors of the game. Furthermore, the game provides integration with technologies that allow the insertion of scientific tools and informations in its context. Students using the system, not only can learn the educational content, but meet a laboratory where they can develop a sort of reasoning and social abilities.

Speedup in distributed executions of Constraint Logic Programming (CLP) applications are directed related to a good constraint partitioning algorithm. In this work we study different mechanisms to distribute constraints to processors based on straightforward mechanisms such as Round-Robin and Block distribution, and on a more sophisticated automatic distribution method, Grouping-Sink, that takes into account the connectivity of the constraint network graph. This aims at reducing the communication overhead in distributed environments. Our results show that Grouping-Sink is, in general, the best alternative for partitioning constraints as it produces results as good or better than Round-Robin or Blocks with low communication rate.

Trace reuse is an effective way of improving the performance of superscalar processors by skipping the execution of a sequence of instructions with known input and output values. However, the extra hardware complexity is of special concern when implementing such mechanisms. In this paper, we describe ways to reduce these requirements for Reuse through Speculation on Traces (RST). RST combines instruction and trace reuse with value prediction in an integrated mechanism to provide missing trace inputs when execution reaches the beginning of a trace. Speculatively reused traces do not consume resources in the execution pipeline, as they are not executed. In this paper, we study the effects of constraining reuse tables to effectively reduce the number of reuse candidates and comparisons. We compare our approach to instruction reuse, trace reuse and value prediction. We show that RST reuses more instructions and has better performance than traditional trace reuse, with an average speedup over a baseline without reuse of 1.21.

This paper introduces SATyrus, a neuro-symbolic architecture oriented to optimization problem solving via mapping problems specification into sets of pseudo-Boolean constraints. SATyrus provides a logical declarative language used to specify and compile a target problem into a particular energy function representing its space state of solutions. The resulting energy function is then mapped into a higher-order Hopfield network of stochastic neurons in order to find its global minima. The application of SATyrus over three illustrative problems are given: (i) graph coloring, (ii) traveling salesperson problem (TSP), and (iii) calculus of the difference between observed and hypothesized distances of two atoms, a sub-problem of the determination of a molecular structure.

In this article, we propose a fully distributed algorithm for finding all primes in a given interval [2..n] (or (L, R), more generally), based on the SMER - scheduling by multiple edge reversal - multigraph dynamics. Given a multigraph M of arbitrary topology, having N nodes, an SMER-driven system is defined by the number of directed edges (arcs) between any two nodes of M and by the global period length of all "arc reversals" in M. In the domain of prime numbers generation, such a graph method shows quite elegant, and it also yields a totally new kind of distributed prime sieving algorithms of an entirely original design. The maximum number of steps required by the algorithm is at most n + radicn. Although far beyond the O(n/log log n) steps required by the improved sequential "wheel sieve" algorithms, our SMER-based algorithm is fully distributed and of linear (step) complexity. The message complexity of the algorithm is at most nDeltaN+ radicnDeltaN, where DeltaNdenotes the maximum "multidegree" of the arbitrary multigraph M, and the space required per process is linear

Reusing dynamic sequences of instructions - i.e., traces - improves performance for many benchmarks. However, many traces are not reused because of unavailable inputs in the reuse test. Reuse through speculation on traces (RST) aims to increase the number of reused traces by predicting those inputs when necessary, with minimal additional hardware when compared to nonspeculative trace reuse. In this paper, we compare last n-value and stride-aware prediction for trace inputs. Last n-value prediction uses the last recorded values as predictions, while stride-aware prediction identifies and uses strides to compute new predictions. Stride-aware RST has a higher hardware cost than last n-value RST and has also the shortcoming of not allowing branches inside predicted traces. This paper aims to determine which scheme is the most beneficial for RST. We show that stride values are important for reuse in RST and that last n-value prediction works as well as the more sophisticated stride-aware approach with simpler hardware.

Scheduling by edge reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. This work uses SER to perform constraint partitioning of constraint satisfaction problems (CSP). In order to apply the SER mechanism, the graph representing the constraints must receive an acyclic orientation. Since obtaining an optimal acyclic orientation is an NP-hard problem, we study three nondeterministic strategies known in the literature: Alg-Neigh, Alg-Edges, and Alg-Colour. We implemented the three algorithms and the SER scheduling mechanism, applying them to the CSP constraint networks generated from 3 applications. Our results show that SER has a great potential to perform a good partitioning of the constraint graphs.

Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ready by the time the reuse test is done. For these cases, we developed a new technique called reuse through speculation on traces (RST), where trace inputs may be predicted. We study the limits of RST for modern processors with deep pipelines, as well as the effects of constraining resources on performance. We show that our approach reuses more traces than the nonspeculative trace reuse technique, with speedups of 43% over a nonspeculative trace reuse and 57% when memory accesses are reused.

Presents a distributed implementation of the Structured Gamma programming language, a language based on the Gamma multi-set rewriting paradigm. Structured Gamma offers, in addition to the advantages introduced by Gamma, implicit concurrent behavior and a type system where not only types themselves are defined but also the automatic verification of user-defined types at compilation time. The problems and mechanisms involved in an MPI-based implementation of Structured Gamma using a type-checking engine based on the most general unifier (MGU) are investigated.

Implementation of overlapped block filtering using Scheduling by Edge Reversal (SER) is proposed in this paper. SER is a very simple and powerful synchronizer. It allows more efficient implementation of parallel structures. This technique is applied for the first time to FIR filters using the overlapped block digital filtering, and implemented on a parallel computer platform. The results confirm the expected reduction in computation time.

Filtered Back-Projection (FBP) is a well-known algorithm for reconstruction of tomographic images from projections. Some of FBP's highlights are: (i) it allows agile software implementations, and; (ii) it produces images of good quality, i.e., relatively free of artifacts. Our goal is to reconstruct images from fan beam projections collected by detectors set in a linear array.

No abstract available.

This work introduces a methodology to ease the implementation of BIST in asynchronous circuits. Scheduling by edge reversal (SER), a simple but powerful distributed synchronizer is used to implement a sequencer that allows testing the circuit at full speed. The methodology, which allows the detection of topological faults, is proved correct. Low hardware overhead and the absence of deadlocks are the main characteristics of the proposed methodology.

We investigate whether arithmetic operations based on Residue Number Systems (RNS) are cost-effective solutions to implement DSP applications into reconfigurable hardware. We simulated several RNS addition and multiplication implementations by varying the RNS parameters. For RNS addition, our results show that it can be implemented into a 3-stage 80.6-92.5 MHz pipeline using about 22 to 33 FPGAs' logic cells. For RNS multiplication, the attainable speed range was between 78.1 and 87.7 MHz, for operand lengths varying between 5 and 8 bits. Overall, a hybrid solution that combines logical elements and blocks of RAM is the best option, producing better average performance across the whole range of operand lengths.