It is a well-documented challenge to keep students engaged and motivated in out-of-class activities. More students now have part- or full-time jobs and less time to study. Supporting their academic growth and success requires acknowledging the higher commitments to the jobs while providing appropriate mechanisms to make the best use of their available times. This paper presents a mobile educational platform, Dysgu, that aims to engage students in out-of-class activities. An initial study completed on this platform investigates the role of peer influence to increase student engagement in an early college class. Data indicates students prefer Dysgu for out-of-class activities compared to traditional pen- and paper-based activities. Students noted that peer influence, in the form of scores compared to the rest of the class, was highly motivating. We also observed more on-time submissions when using Dysgu.

OpenCL is a High-Level Synthesis (HLS) based framework that relaxes the programmers considering design time and design complexity. A single OpenCL kernel can be designed in numerous ways by tuning the design knobs. For a given setting of design knobs, logic synthesis of each OpenCL- based design can take several hours. Therefore, the Design Space Exploration (DSE) to search for an optimized design is prohibitive. This paper presents an automated CODE tool to implement an OpenCL-based Matrix-Vector Multiplication (MVM) kernel optimized for throughput and area.

In this paper, we present AutoRARE, a Java-based automated design tool for generating Field Programmable Gate Array (FPGA)-based hardware accelerators. AutoRARE automatically generates all VHDL models needed to build/synthesize a processor specifically tailored for each application. The user needs only provide the VHDL description of a special-purpose floating point Arithmetic Logic Unit (ALU) or function core. The tool generates the VHDL description for the memory interface, memory controller, host processor interface, and the application specific processor. We also present details of the FPGA-based multi-memory hardware accelerator for accelerating computationally intensive applications, generated using AutoRARE. The multi-memory hardware accelerator is highly pipelined and able to simultaneously read and write multiple floating point values from multiple memories. The multi-memory architecture is the key to providing hardware accelerators that execute 10X-100X faster than typical multi-core processors. The Taylor Series expansion of the sine/cosine function is used as an application to demonstrate the merits of the multi-memory hardware accelerator. In our experiments, we executed the Taylor Series in software and compared execution times with an FPGA-based hardware implementation. Our experiments show that the FPGA-based multi-memory Taylor Series hardware accelerator is 481X faster than software executing the Taylor Series on a typical server.

Classroom formative assessment augmented with timely and frequent feedback has become one of the most prominent teaching practices in education research. On the context of Computer Science (CS) courses that expose students to the functionality and dynamic aspects of various algorithms, traditionally, students are evaluated by exploring in-class paper-based exercises. In these exercises, they simulate the steps of an algorithm by drawing several instances of a diagram. This traditional approach is time consuming, is inherently difficult for students to express the dynamics of an algorithm, does not allow timely feedback, and restricts the number of exercises that students can practice and receive feedback on. Mobile Response System (MRS) is a software environment that facilitates in-class exercises and their real-time assessment using mobile devices and therefore focuses on addressing many of the above-mentioned problems. In this paper, we present results of eight semester-long studies using MRS in two of the required CS courses at Winston-Salem State University (WSSU). Our experimental evaluation shows the educational benefits of the proposed approach in terms of enhanced student retention of covered concepts, reduced failing rate, and increased student engagement and satisfaction.

Significant barriers to real time face detection have been the complexity of computation kernels, minimal cost and superior accuracy requirements for both software and hardware implementation based on traditional high performance computing. It is desirable to develop variable precision face detection block for high dynamic range applications including night vision and infrared face detection applications. This paper developed an Arctan function for face detection which supports input ranges upto 360 degrees for Histogram of Oriented Graph. Our implementation takes advantage of mathematical identities for the pedestrian HOG computation. We compare our HOG block design to fixed point implementations and found that using floating point HOG is not be computationally expensive and can accelerate face detection process.

To improve student's class experience, the use of mobile devices has been steadily increasing. However, such use of mobile learning environments in the class is mostly static in nature through content delivery or multiple choice and true/false quiz taking. In CS courses, we need learning environments where students can interact with the problem in a hands-on-approach and instructor can assess their learning skills in real-time with problems having different degree of difficulty. To facilitate such interactive problem solving and real-time assessment using mobile devices, a comprehensive backend system is necessary. This paper presents one such system, named Mobile Response System (MRS) software, associated interactive problem-solving activities, and lessons learned by using it in the CS classrooms. MRS provides instructor with the opportunity of evidence-based teaching by allowing students to perform interactive exercises in their mobile devices with different learning outcomes and by getting an instant feedback on their performance and mental models. MRS is easy-to-use, extensible and can render interactive exercises developed by third-party developers. The student performance data shows its effectiveness in increasing student understanding of difficult concepts and the overall perception of using the software was very positive.

This paper presents a reconfigurable computing environment while addressing the problem of porting High Performance Computing (HPC) applications directly to Field Programmable Gate Arrays (FPGAs)-based architectures. The objectives of this research are developing a comprehensive floating point library of essential functions for scientific applications; demonstrate order of magnitude speedup of reconfigurable computing applications, demonstrating the effectiveness of automated design framework for both development and test of scientific algorithms. The developed framework can be reused in various scientific applications which shares kernel functions. The study of this research has identified an exponential function as a kernel for cellular ophthalmoscopy camera processing, traffic monitoring and light wave simulation. The paper demonstrates 30x speedup of these kernels in three algorithms using its novel architecture and its automated toolset. Exponential kernel generation case study and its flexible hardware implementation on an FPGA has been validated onto a Xilinx LX-100 device and the Nallatech H101-PCIXM FPGA board.

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to house hardware-based custom implementations of these kernels to speed up these applications. In this paper, we demonstrate a methodology for algorithm acceleration. We used SAR as a case study to illustrate the tremendous potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show an average speed-up of 188 when using the FPGA-based hardware accelerator as opposed to using a software implementation running on a typical general purpose processor.

Motivation: Contact map is a key factor to represent a specific protein structure. As previous work reported, even a corrupted contact map can be used to reconstruct its corresponding protein structure. Thus we can predict the structure of a protein partially through the contact map prediction. To simplify the protein contact map prediction, we predict the inter-residue contact clusters centered at the groups of their neighboring contacts instead.Results: In this paper, we adopt a SVM predictor based approach to predict the inter-residue contact cluster centers. The input information of the SVM predictor includes sequence profile, evolutionary rate, and predicted secondary structure. The SVM predictor is based on hydrophobic cores that may be considered as locations of the groups of their neighboring inter-residue contacts. As a result, about 35% clustering centers of inter-residue contacts can accurately be predicted.

In this paper we present a configurable digital signal processor synthesis (CPS) System that produces a library of high-performance processors wherein each processor executes a specific digital signal processing (DSP) algorithm. Each processor contains a small instruction set and implements a particular application. These algorithm specific DSPs (ASDSPs) are used to alleviate bottlenecks in software by replacing computationally intense portions of a high level DSP algorithm with custom hardware. Each ASDSP generated by the CPS system is individually loaded into a commercially available configurable system. A library of algorithm specific DSPs for a sample application set of fundamental complex arithmetic modules is generated using the CPS system. The resulting library of floating point processors is implemented on a Firebird FPGA board containing a Virtex XCV2000E FPGA part. The results are compared with a comparable software algorithm implemented on a 2.79 GHz Pentium IV general purpose processor. This comparison shows that, despite having a clock speed that is an order of magnitude slower than the microprocessor (54 MHZ versus 2.79 GHZ), the proposed ASDSP ran an order of magnitude (13X) faster than the microprocessor implementation in the best case.

Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm is to reduce interprocessor communication and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.

The authors address scan-based built-in self-test (BIST) of digital circuits that are highly resistant to testing with uniform random patterns. Introducing a procedure, the precompute test patterns for random-pattern resistant faults and generate optimized distributions of weights that guarantee pattern coverage in a given number of random trials. The software implementation offers a tradeoff in the number of distributions (hardware memory) and the length of the total test time. The hardware implementation is based on a canonic weighting circuit that interfaces to a circulating memory and a pseudo-random source.>

The authors introduce WARP, a weighted test generation system that includes a canonical circuit for resolving weights to any desired precision. Either cellular automata registers (CARs) or linear feedback shift registers (LFSRs) are used as a source of random patterns, and optionally, it is possible to permute and linearly combine random bits from the source to control inputs to the weighting circuit. The authors analyze pattern coverage and conclude with benchmark results on fault coverage differences between CARs and LFSRs.>

Boundary scan merging with built-in self-test is discussed. The proposed implementation of boundary scan represents a snapshot of the Joint Test Advisory Group Recommendation 1.0, while the built-in self-test implements the features of cellular automata. Test patterns generated from two distinct sources are examined, one with registers using cellular automata and the other, based on the conventional LFSR (linear-feedback shift register) configuration. Distinctive effects of these patterns on fault coverage of specific designs are analyzed and illustrated.>