A procedure to remotely control hardware reconfiguration at runtime is introduced in this paper. Low-level interactions are abstracted by a middleware service that can be called by requests issued by the user or by the underlying operating system. The dynamic loading of hardware modules is managed by a kernel reacting to user-defined events with a customizable scheduling strategy. The system has been designed in a flexible and portable way to support most common runtime reconfiguration approaches and operating systems. Interactions with the middleware are based on commands allowing custom composition and scheduling of hardware modules after deployment. The operation of the middleware is illustrated with the example of a remotely reconfigurable sensor node in a high-performance wireless sensor network.

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

This paper presents adaptive routing selection strategies suitable for network-on-chip (NoC). The main prototype presented in this paper uses contention information and bandwidth space occupancy to make routing decision at runtime during application execution time. The performance of the NoC router is compared to other NoC routers with queue-length-oriented adaptive routing selection strategies. The evaluation results show that the contention- and bandwidth-aware adaptive routing selection strategies are better than the queue-length-oriented adaptive selection strategies. Messages in the NoC are switched with a wormhole cut-through switching method, where different messages can be interleaved at flit-level in the same communication link without using virtual channels. Hence, the head-of-line blocking problem can be solved effectively and efficiently. The routing control concept and the VLSI microarchitecture of the NoC routers are also presented in this paper.

This paper presents an historical review of the establishment of an academic programme introducing teaching and research on FPGA-based system design in the Mongolian High Education. The main strategy was to found a Microelectronics research group within several departments of the Mongolian University of Science and Technology (MUST) and promote the education of microelectronics design not only at the MUST, but also throughout Mongolia. The education process adopted at the Computer Science and Management School (CSMS) of MUST will be presented. Under the Microelectronics group initiative, a set of events (Electronics Olympiad, seminaries and workshops) was set up in MUSTcollaboration with other Mongolian Universities as an important action for the dissemination of FPGA-based system design. The presence of students and faculty members in international activities had also an important effect. Results of research and teaching practices will also be presented.

An intuitive tool for the elaboration of configuration data for a Coarse-Grained Dynamically Reconfigurable Architecture (CGDRA) is presented in this paper. A Graphical User Interface (GUI) allows developers who are not familiar with the design or with dynamic reconfiguration, a quick elaboration of an algorithm implementation with the help of function blocksets. The generated configuration data is then uploadable in the core at runtime and can be remotely activated in order to execute the desired functionality. The interface also allows a rapid selection and arrangement of the elements composing the smart sensor interface and an adaptation of the design to a large range of applications. The system architecture is particularly suitable for resource-constrained embedded systems like Wireless Sensor Networks (WSNs) where it can be used for energy and time-efficient data processing or on-demand hardware acceleration.

A dynamically reconfigurable architecture tailored for low power wireless sensor networks is introduced in this work. Using resource sharing and frequent reconfiguration, the power consumption of the hardware is kept low while data processing is still efficient. Remote reconfiguration becomes also possible with very low overhead.

To improve the computation precision of the beams control system in a heavy ion accelerator system, a floating-point phase and magnitude digital detector is proposed. The coordinate rotation digital computer (CORDIC) algorithm is utilized to compute results in digital form. Due to the hardware design simplicity, shifting and adding operations become two main operators to perform the computation. The proposed CORDIC core is based on floating-point arithmetic units to obtain high accuracy for the closed-loop control system. A Pipeline-based architecture is applied instead of CORIDC's iteration process in order to maximize computation performance. Moreover, comparison of hardware 8-and 16-stage pipeline-based simulations with Matlab/simulink is statically analysis to differentiate the accuracy of the two hardware architectures. Finally, resource efficiencies based on target Xilinx FPGA xc5vlx110 and 130-nm Silicon technology are shown that 8-and 16-stage hardwares consume maximum 18% and 38% of total slices at 134 MHz on the target FPGA, as well as 43,164 um and 83,769 um at 617 MHz on Silicon technology.

This paper presents an implementation of a radio frequency wave energy harvester with the capability of self-adjusting the matching network to adapt to changing load conditions. An auxiliary charge-pump is designed to supply the power for the supplemental control unit. The design is implemented in a standard 0.13-μm CMOS process. The results show that the power transfer efficiency with using the proposed design can achieve a level of over 70% independent of the load conditions.

A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.

Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.

This paper presents the first synthesizable network-on-chip (NoC) based on a mesh topology, which supports adaptive and deadlock-free tree-based multicast routing without virtual channels. The deadlock-free routing algorithms for unicast and multicast packets are the same. Therefore, the routing function gate-level implementation is very efficient. Multicast packets are injected to the network by sending multiple packet headers beforehand. The packet headers contain destination addresses to set up multicast trees connecting a source with multiple destination nodes. An additional locally uniform identification (ID) field is packetized together with flits belonging to the same packet. Therefore, flits of different unicast or multicast packets can be interleaved in the same queue because of the local ID-tags, which are updated and mapped dynamically to support bandwidth scalability of interconnection links. Deadlocks in tree-based multicast routing are handled using a flit-by-flit round arbitration and a fair hold-release tagging mechanism. The effectiveness of the novel mechanism has been experimented under multiple multicast conflicts scenarios, where the experimental results show that all traffic is accepted in-order and lossless in their destination nodes even if adaptive routing functions are used and the sizes of the multicast messages are very long.

The richness of wavelet transformation is known in many fields. There exist different classes of wavelet filters that can be used depending on the application. In this paper, we propose an IEEE 754 floating-point lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs) and Discrete Wavelet Packets (DWPs). Our architecture is based on processing elements that can perform either prediction or update on a continuous data stream in every two clock cycles. We also consider the normalization step that takes place at the end of the forward DWT/DWP or at the beginning of the inverse DWT/DWP. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs/DWPs. Different memory sizes and multi-level transformations are supported. For the 32-bit implementation, the estimated area of the proposed processor with 2times512 words memory and 8 PEs in a 0.18-mum process is 3.7 mm square and the estimated operating speed is 353 MHz.

We explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which combines high energy efficiency with programmability and hence meets the requirements of small energy-constraint embedded systems. Its energy consumption, area, and performance are evaluated and compared to processor and ASIC architectures. Our case study particularly focuses on the question if the architecture concept of frequent dynamic reconfiguration of a small heterogeneous data path can lead to suitable system solutions for the target domain. To answer this, the effect of the reconfiguration overhead on total system efficiency is examined closely. As important result, our experiments show the low energy consumption achieved, the low reconfiguration overhead, and the specific region of the architecture in the design space between processors and ASICs. In particular, large energy-savings of factor 2 to 6 and speed-ups of factor 6 to 14 compared to processors are obtained on average. Our work shows the high suitability of frequent runtime reconfiguration of small coarse-grain data paths for the design of very efficient but yet programmable embedded systems platforms.

Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for implementing the reconfiguration control on the FPGA. First, we extend our existing tool flow with a novel mechanism for efficient partial multi-context reconfiguration and provide tool support to generate according circuitry, control, and configuration data. Second, we propose an extension of current FPGA architectures to efficiently support cycle-based runtime control. We employ a special content-addressable multi-context memory resource for controlling the datapath functionality, which on average requires only 15% memory for storing the control data compared to a BlockRAM based approach, and only 53% compared to regular multi-context switching.

A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise. Using this scheme, the average number of unstable bits i.e. bits which can change in value between readings, measured on an FPGA is shown to be reduced from 5.3% to 0.9% at 20degC. Within the range 20-60degC, the percentage of unstable bits is within 2.8%. An analysis of the effectiveness of the scheme and the distribution of the errors is given over different temperature ranges and FPGA chips.

Synthetic Floating-Point (SFP), a synthetic benchmark generator program for floating-point circuits is presented. SFP consists of two independent modules for characterisation and generation. The characterisation module extracts key dataflow statistics of an arbitrary software program. Generation involves producing randomised circuits with desired statistics which are either the output of the characterisation module or directly generated by the user. Using the basic linear algebra subprograms (BLAS) library, Whetstone benchmark and LINPACK benchmark, it is demonstrated that SFP can be used to generate floating-point benchmarks with different user-specified properties as well as benchmarks that mimic real computational programs.

In this paper, we propose a lifting-based DWT processor that can perform various forward and inverse transforms. Contrary to other lifting-based processors which focus on JPEG2000, our design is based on the fact that the wavelet transformations are not used only in the area of image processing and wavelet filters may not be represented as integer numbers. The proposed architecture is based on NxM processing elements which require only one multiplier and one adder to perform prediction/update on a continuous data stream. The multi-context feature allows the processor to be configured for different types of transformations in a simple manner.

Device parameter variations exhibit an increasingly serious impact on analog and mixed-signal circuit behavior. In this paper, we propose a novel fully-analog on-chip adaptive body bias calibration method, for efficiently reducing mismatches in transistor pairs. We present three circuit implementations which achieve a mismatch reduction between 61% and 73% in terms of standard deviation.

Comparator-based switched capacitor (CBSC) circuits present an alternative approach to designing sampled data systems based on the principle of detecting a virtual ground condition with a comparator rather than actively enforcing it with a high-gain operational amplifier (opamp) in feedback. This work demonstrates a 2nd-order DeltaSigma converter designed using the CBSC technique. The same modulator topology was also implemented using two conventional design methods for a two-stage Miller-compensated amplifier and a single-stage folded cascode amplifier, such that all three blocks can be used as 'drop-in replacements' in the top-level circuit. The designs are done in a 0.13 mum UMC technology. The SNDR performance and power consumption of all three approaches were simulated with a sampling frequency of 5.12 MHz and an oversampling ratio of 64. It can be concluded that the CBSC method provides a great simplification of design effort and significant power savings compared to the traditional OTA-based methods.

This paper presents a flexible mesh router architecture using synchronous parallel pipeline worm-switching supporting unicast and multicast services. A very flexible mechanism to manage broadcast-flow to share the communication link in on-chip network is proposed. The proposed mechanism guarantees, that all flits in multicast packets can be accepted in their multiple destination nodes. Our network-on-chip (NoC) is implemented based on modular synthesizable VHDL objects. The architecture is flexible to design new NoC prototypes. Area overhead to update the NoC from unicast to multicast with the same routing algorithm is only about 15%.

In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and power cost, performance, and reconfiguration time. Thus, architectures with coarse-grained reconfiguration features have also been studied in projects (Sec. 1, 2, 4) within the priority program Reconfigurable Computing Systems and the project CoMap (Sec. 3), which are all sponsored by the German science foundation.

In this paper, we propose a generalized lifting-based wavelet processor that can be configured to compute various forward and inverse DWTs. Our architecture is based on NxM PEs which can perform either prediction or update on a continuous data stream in every two clock cycles. We also consider the normalization step which takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. The proposed processor can be operated at around 186 MHz depending on the data width selection.

In this paper, we present the design and the implementation of an FPGA-based floating-point adder with three inputs. The design is based on a 5-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages and to reduce the resource allocation. Our design is parameterisable in order to cope with different floating-point formats, including the standard IEEE 754 formats and the custom configurations. The proposed design with the single precision, 32-bit floating-point format, can be operated at 143 MHz on Xilinx Virtex2Pro XC2VP30-7.

Application-specific reconfigurable processor architectures provide a remarkable potential for systems which achieve concurrently high performance, area efficiency, energy efficiency, run-time adaptivity, and sufficient flexibility. Thus, they represent competitive design alternatives that provide significant improvements in some of these figures of merit in comparison to non-reconfigurable architectures. Research results of three projects on the analysis of architecture concepts, design, and evaluation of application-specific reconfigurable processors in different domains are presented.

Hardware reconfiguration during run-time provides attractive features like fast adaptivity, high hardware utilisation, and low area consumption due to efficient reuse of hardware components. In this paper, a novel multi-layered reconfiguration mechanism is proposed that allows frequent dynamic reconfiguration at very low latencies. It combines successful existing techniques such as multi-context and partial reconfiguration with new ideas like tag-matching and reconfiguration profiles to one uniform approach. As an important feature, the proposed reconfiguration mechanism is well scalable and can be adapted to given hardware structures easily, thus being applicable to virtually any reconfigurable fabric. In contrast to many existing techniques, it also supports even very heterogeneous architectures found for instance in custom reconfigurable systems. By experimental results, we show that our reconfiguration mechanism provides significantly lower reconfiguration latencies compared to some common existing techniques.

We present a hardware implementation of an efficient image compression method optimised for small FPGAs. The compression method is based on a codebook of reference patterns to support multiplication-free quantisation of the image data. Based on specific features of a low-cost FPGA architecture, a pipelined implementation is developed and evaluated. The implemented hardware benefits from the simple structure of the compression method and is optimised for area and performance. The realised hardware as well as the underlying compression mechanism are described and the synthesis results for different model variants are compared. The results show that a high compression rate is possible at extremely low hardware costs. Also, a high frame rate can be obtained even on a low-cost FPGA.

This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity mapping management. The NoCs are developed based on VHDL-modular approach to support the design flexibility. The on-chip router switches packets using wormhole packet switching method with synchronous parallel pipeline technique. Contention-free routing algorithms and dynamic packet identity management are proposed to support wire- through-share methodology and identity-slot division multiple access technique. The on-chip routers are also equipped with packet flow control and automatic injection rate control mechanism to avoid packet-loss, when the NoC is congested. Some static and adaptive routing algorithms are implemented in the NoC to observe the performance of the NoC over some selected network traffic patterns and the logic consumption (using CMOS standard-cell library). Area overheads to implement several adaptive routings over static routing algorithm are less than 9%. Our NoC guarantees in-order and lossless message flits delivery.

Two major trends can be observed in a modern system-on- chip design: first a growing trend in system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architectures. The second in technology scaling indicates that the wires are getting thinner and results in an increment of wire delay and power consumption. These, in turn, result in the degradation of both device reliability and system performance. As the process technology is scaled down, the effects of process variation are becoming significant on system performance. In order to incorporate the combined effects process variations on the performance of on-chip bus architecture, this work proposes a technique to synthesize an energy conscious robust on- chip bus architecture. The proposed model simultaneously performs on- chip bus synthesis and voltage scaling under both data size and process parameters variations. The problem is relaxed to a nonlinear optimization model, which synthesizes an energy conscious optimal bus widths and the number of buses considering worst case data traffic and process variations. The experimental results show that applying voltage scaling during the synthesis of on-chip bus effectively reduces the dynamic power consumption, leakage power consumption, and mitigates the effects of process variations.

This paper proposes a compact neural classifier, based on the theory of simplicial decomposition and approximation, with a very convenient hardware or software implementation. It can learn arbitrary n-inputs patterns with O(n) time complexity. There are no multipliers required, and the learned knowledge is stored in a general purpose RAM with a size ranging from O(n) to O(n2). The proposed architecture is composed only of four building blocks, an iterative nonlinear expander, a sorter, a RAM memory, and an accumulator, all of them readily available in either digital hardware or software technology. Simulation results indicate good accuracy for a wide variety of benchmark problems. © 2008 Wiley Periodicals, Inc.

Behavioral patterns are useful abstractions to simplify the design of the communication-centric systems. Such patterns are traditionally described using UML diagrams, but the lack of execution semantics in UML prevents the co-validation of the patterns together with simulation models and executable specifications which are the mainstream in today's system level design flows. This paper proposes a method to validate UML-based behavioral patterns within executable system models. The method is based on actor orientation and was implemented as an extension of the Ptolemy II framework. A case study is presented and potential applications and extensions of the proposed method are discussed

We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the software which will run on it. The FLPA/ILPA model used during our work as well as the test scenarios and the measured results are described. Later, the function block separation and the power consumption modeling are discussed. Finally, the model is validated by benchmarking. The obtained model is promising in the sense that a) its estimations are close (4% on average) to the measured data, and b) the model structure is similar to that of hardcore processors which is not a trivial result.

In this paper, a new generic sensor node platform for wireless sensor networks (WSN) is presented, demonstrating that high energy efficiency, flexibility and performance can be achieved by the use of dynamically reconfigurable hardware in the WSN domain. The core of the presented platform is formed by the combination of a RISC processor and a dynamically reconfigurable function unit optimized for efficient data processing in WSN applications. A novel reconfiguration mechanism is applied enabling rapid dynamic reconfiguration with very short latencies. Thereby, we can show that the overhead on performance and energy consumption caused by dynamic reconfiguration can be reduced to a moderate, non-critical value and is clearly outweighed by the significantly improved performance and energy consumption for data processing on the reconfigurable function unit. The evaluation of the platform and its comparison to a standard processor-based platform finally demonstrate high gains in energy-efficiency of one to two orders of magnitude.

This paper proposes a resampler architecture which employs the filtering the input signal with a FIR filter whose coefficients depend on the phase of the interpolated sample relative to the input samples. The novelty of this architecture consists in generating the coefficients by using linear interpolation between a number of predefined coefficient sets for equidistant sub-sample phases. The proposed architecture is particularly efficient for multi-channel interpolation, since all channels are resampled simultaneously and the coefficients generation block can be shared. Only the interpolation FIR filter needs to be replicated for each channel.

The paper introduces a hardware-efficient interpolator architecture that is able to handle very large and fractional interpolation factors. Unlike most existing solution, the interpolation is performed in one step, which obviates the need for complicated multi-stage implementations. Besides the architecture itself, the paper also offers an analysis of the interpolation performance, using various interpolation functions.

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.

We propose a statistical approach for minimizing on-chip communication bus width and number of buses with reduced communication energy under timing yield constraint. The slack is exploited to maximize sharing of buses and to reduce energy by simultaneously scaling the voltage during the communication synthesis. Because of the diversity of applications to be run on a single SoC, there exists variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a normally distributed random variable. The resulting synthesis problem is relaxed to the convex quadratic optimization problem and is solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By varying the value of timing yield constraint, a trade-off between minimization of buses and energy reduction is explored. The experimental results show the significant reduction of communication energy with the increasing timing yield. However, the timing yield offers a limitation to minimize the size of bus width and number of buses, if the yield is increased beyond a certain limit.

In this paper we present a method which allows the statistical analysis of nanoelectronic Boolean networks with respect to timing uncertainty and noise. All signals are considered to be instationary random processes which is the most general signal representation. As one cannot deal with random processes per se, we focus on certain statistical properties which are propagated through networks of Boolean gates yielding the instationary probability density function (pdf) of each signal in the network. Finally, several values of interest as the error probability, the average path delay or the average signal trace over time can be extracted from these pdf

Reconfigurable hardware is often used in an attempt to boost performance of an embedded system while minimizing the cost penalty of additional hardware. The key method applied to achieve this goal is the re-use of hardware resources for different tasks. However, reconfigurable systems tend to have a large internal state, which complicates rapid task switching, as it is required for multitasking in real-time systems, significantly. We present a control technique enabling a fast and efficient preemption of dynamically reconfigurable systems which is largely performed by hardware. The technique handles the problem of internal state preservation and reduces the preemption effort by applying the concept of preemption points. The implementation of the system control and an evaluation of the performance is given, showing the high efficiency of the concept.

In a reconfigurable computing system, some of the on-chip modules can be configured partially to run several applications in a single chip. Due to this feature of partial reconfiguration, the size of data to be transferred among the on-chip modules is random in nature. This paper proposes a method to synthesize an energy efficient on-chip communication bus width and number buses for a reconfigurable architecture. The randomness of data for such an architecture is modeled as a normally distributed random variable. The slack is exploited to maximize sharing of buses and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of communication bus. The resulting synthesis problem is relaxed to the quadratic optimization problem and is solved efficiently using a convex optimization tool. The experimental result shows the synthesis of bus width and number of buses with reduced communication energy for different variability of data size.

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput.

Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usually assume that the worst-case crosstalk occurs with all the aggressors of a victim (net or path) simultaneously inducing crosstalk even though this may not be possible at all. This overestimated crosstalk is called false noise. Logic correlations have been explored to reduce false noise in J.C. Beck, et al., (2004), which also used branch and bound method to solve the problem. In this paper, we propose a novel approach, named tendency graph approach (TGA), which preprocesses the logic constraints of the circuit to drastically speed up the fundamental branch and bound algorithm. The new approach has been implemented in C++ and tested on an industrial circuit in a current 90 nm technology, demonstrating that TGA considerably accelerates the solution to the false noise problem, and makes in many cases branch and bound feasible in the first place.

This paper presents an energy efficient on-chip communication synthesis for shared bus based architecture. An assumption for the synthesis is that a system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. The problem of communication synthesis is modeled in NLP (nonlinear programming), which finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The supply voltage is scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 44.6% by scaling its supply voltage

Due to shrinking process geometries and an increasing number of chip components in very deep sub-micron technologies, interconnects emerged as a main limiting factor for performance, die area, and power consumption. Buffer allocation, interconnect congestion, power dissipation in buffered interconnects pose tremendous difficulties on the design process. It is therefore of paramount importance to address interconnect and buffer planning at early stages in the design flow, especially from the perspective of power consumption and thermal management. The goal of this work is to indicate the remarkable opportunities in reducing power consumption in buffered interconnects during placement, and to extend a classical placement algorithm to include power-optimized interconnect and buffer planning. The authors merge a placement algorithm based on simulated annealing with A-tree construction, van Ginneken's buffer insertion algorithm, and accurate moment-based delay computation. The authors show that dramatic improvements can be achieved in terms of total interconnect structure capacitance and total area of required buffers

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

This paper presents a method of on-chip communication bus topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate modules of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We define the problem of on-chip communication topology synthesis into two main problems namely scheduling and allocation binding problem. The communication behavior of each module is modeled as a set of communication lifetime intervals (CLTIs), which are evaluated and scheduled for different size of bus width to get the minimum number of overlaps, minimum size of bus width and the minimum number of bus(es) using tabu search method. These optimized CLTIs are given to the clique partitioning algorithm as an allocation-binding problem to synthesize the communication topology

In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.

This paper presents a method of on-chip commaunication topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. These optimized CLTIs are later given to the communication topology synthesis algorithm, which gives the number of buses and their interconnection. The results of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrate the utility of our techniques to synthesize a custom on-chip shared multibus based communication architecture for a complex system.

In this paper we describe and compare several architectures of cellular automata to be used as hardware accelerators in the evaluation loop of a genetic algorithm. In addition, two dynamically reconfigurable cell interconnection networks are presented capable to realize nonregular lattices. Cellular automata are basic computational structures of interacting units which may expose self-organization and emergent behaviour. To investigate this behaviour subject to different cell interconnect patterns, an automated inspection flow is needed, including a very fast evaluation of single specimen. For that purpose, a flexible FPGA-based accelerator for cellular automata evaluation is used, which can be accessed transparently by a Java client running the genetic algorithm. Several architectures have been developed for that: a straightforward implementation of the cellular automaton, an area-reduced architecture, a dynamically reconfigurable interconnection network, which allows the interconnection of single cells under certain constraints and, finally, a dynamically reconfigurable interconnection network, which allows to connect cells arbitrarily.

This paper presents the realisation of a hardware-in-the-loop system to investigate the performance of different cellular automata (CA) structures. The system is applied to regular lattice CAs and to small-world CAs, which are expected to expose better characteristics than lattice automata due to their nature-inspired structure. CA functionality is evolved using a genetic algorithm (GA) implemented as a distributed Java program running on a host computer. The performance evaluation of whole generations of individual automata is transferred to a specialised hardware architecture on an FPGA-board in order to speed up this process. For this, a customisable version of an automaton is residing on the board and personalisation data can be downloaded to it. The objective of the approach is to gather qualitative and quantitative data on the differences between the two types of CAs. We discuss two CA implementations, one of a lattice CA and one of a small-world CA. Their properties are characterised and their integration into the overall evaluation system is described.

Routing is one of the most crucial key factors which decides over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-mesh based network-on-chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.

This work presents the hardware design of a dynamically reconfigurable function unit (RFU) to accelerate computation-intensive tasks in Medium Access Control (MAC) layers of WLANs. The function unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for the Advanced Encryption Standard (AES) as specified in upcoming WLAN standards such as IEEE 802.11i. Dynamic reconfiguration allows the processor to use arithmetic components and memory elements of the RFU not only for AES, but also for additional tasks common in the MAC-layer. With our approach it is possible to accelerate Reed-Solomon-Code generation, Cyclic Redundancy Checks as well as other encryption standards like SQUARE, Magenta and Twofish by supporting Galois Field multiplication and table look-ups. The integration of the reconfigurable unit in the processor core results in an architecture that can simultaneously support control-flow and data-flow oriented tasks. This architecture was prototyped onto a Virtex2 FPGA.

A multiplier-less neural architecture for PCA is proposed. The aim is to reduce the VLSI complexity of its implementation by eliminating the multipliers. Comparisons with standard PCA methods show no degradation in performances (in most cases they are even improved) while the reduced hardware complexity allows for efficient low power implementations.

Field-programmable logic has become an increasingly important technology for the design of digital circuits. One interesting point in the field of reconfigurable logic is its classification within the implementation space of other technologies. Such a classification gains importance if FPGA technology becomes an integral part of Systems-on-a-Chip (SoC). The poster discusses an approach to classify technologies based on their granularity. Therefore, a new distinction into homogeneous and heterogeneous granularity is proposed. This leads to a theoretic classification method for the combination of two or more technologies. Using this method the result of a combination of two or more technologies can be determined qualitatively. The poster further shows opportunities to improve standard CAD-software based on the model proposed.

A module generator is described that allows for the generation of synthesizable VHDL modules which implement arbitrary functions in fixed point precision using the Symmetric Table Addition Method (STAM). This module generator was interfaced to a high level synthesis tool "fly" which automatically generates fully-pipelined circuits from a Perl-like language. The resulting system was applied to the N-body problem and results are presented. It was found that a function generator module is a very useful addition to a hardware description language.

This paper focuses on the reconfiguration requirements of hardware platforms for high speed wireless communication systems. Due to the underlying trade-off between flexibility and efficiency, many reconfigurable hardware solutions and FPGA implementations are prone to significant energy and performance penalties in comparison to application specific hardware designs. These penalties can only be alleviated by designing reconfigurable architectures for selected applications fields, since each application field has only a limited set of flexibility requirements. In this paper the analysis is conducted for emerging wireless communication standards based on the OFDM (Orthogonal Frequency Division Multiplexing) or CDMA (Code Division Multiple Access) transmission technique. The requirements for the physical and the medium access layers are analyzed separately. Focus is also set on different market segments.

Article Share on Regularization of hierarchical VHDL-AMS models using bipartite graphs Authors: Jochen Mades Infineon Technologies AG, Munich, Germany Infineon Technologies AG, Munich, GermanyView Profile , Manfred Glesner Institute of Microelectronic Systems, Darmstadt University of Technology, Germany Institute of Microelectronic Systems, Darmstadt University of Technology, GermanyView Profile Authors Info & Claims DAC '02: Proceedings of the 39th annual Design Automation ConferenceJune 2002Pages 548–551https://doi.org/10.1145/513918.514056Published:10 June 2002Publication History 0citation15DownloadsMetricsTotal Citations0Total Downloads15Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A collaborative design system depends heavily on the chosen collaboration methodology, as well as on its technological infrastructure. This paper presents three data repository technologies and discusses their pros and cons on the role of supporting a collaborative design system.

Because of the increasing importance of cross coupled capacitances in deep submicron technologies, it is of great interest to extend the existing high-level power estimation techniques by considering the spatial correlation between adjacent lines. This work addresses the modeling and estimation of power dissipation in on-chip buses based on the statistical properties of data sequences. Using the derived models, a power estimation technique is proposed and evaluated for various coding schemes. For different DSP applications, our results depict less than 5% discrepancy with precise bit level estimations.

Because of the increasing demand of portable digital systems, it is of great interest to extend the existing high-level power estimation techniques to handle architectures with non linear components, as they appear in relevant practical applications. In this paper we focus on the estimation of the transition activity in MAC structures implementing FIR filters. Based on a divide and conquer approach, an accurate yet efficient estimation procedure is developed. The technique has been evaluated for different synthetic and real data sets. In all cases, our results depict only very slight discrepancies with respect to precise bit level simulations.

This paper introduces a novel neural architecture which is capable of similar performance to any of the "classic" neural paradigms while having a very simple and efficient mixed-signal implementation which makes it a valuable candidate for intelligent signal processing in portable multimedia applications. The architecture and its realization circuit are described and the functional capabilities of the novel neural architecture called a simplicial neural cell are demonstrated for both regression and classification problems including nonlinear image filtering.

The performance of a packet-oriented OFDM system relies strongly on the goodness of the synchronization scheme. In practice, the theoretical accuracy of a synchronization technique can be worsened by the finite-precision effects introduced the digitization of signals. This work evaluates the impact of the quantization errors on the performance of the coarse timing synchronization and CORDIC (COordinate Rotation DIgital Computer)-based frequency compensation for OFDM burst-mode applications. Furthermore, an analytical approach allowing one to predict the wordlength according the required accuracy degree is proposed. Simulation results related to the application of this evaluation scheme to the HiperLAN/2 environment are presented.

A tight lower bound on the accuracy of CORDIC (coordinate rotation digital computer) based frequency offset estimation and correction schemes is derived. The evaluation scheme relies on the Cramer-Rao lower bound (CRLB) and the upper bound of the error introduced by the CORDIC algorithm. Simulation results related to the application of the bound to a HIPERLAN/2 simulation model are presented.

The evolving of current and future broadband access techniques into the wireless domain introduces new and flexible network architectures with difficult and interesting challenges. The system designers are faced with a challenging set of problems that stem from access mechanisms, energy conservation, error rate, transmission speed characteristics of the wireless links and mobility aspects. This paper presents first the major challenges in realizing flexible microelectronic system solutions for future mobile communication applications. Based thereupon, the architecture design of flexible system-on-a-chip solutions in the digital baseband processing for future mobile radio devices is discussed. The focus of the paper is the introduction of a new parallel and dynamically reconfigurable hardware architecture tailored to this application area. Its performance issues and potential are discussed by the implementation of a flexible and computation-intensive component of future mobile terminals.

Time frequency distributions (TFDs) based on Cohen's (1995) class have significant potential for the analysis of non-stationary signals. However, the high computational requirement limits their use in systems when hardware resources are costly. Independently of TFDs, developments in wavelets and filter bank theory have led to the design of a signal-adapted principal component filter bank so that good L/sup 2/ approximations to the signal can be computed from a reduced number of channels. In this paper, we integrate these two different but complementary works into a novel cross-term reduced scheme for the TFD computation with incremental refinement feature. The approach allows dead-line based real-time processing of time-critical applications. Further, the polyphase formulation of the filter bank yields parallel structures at reduced operation rate for the same throughput which can be advantageous for VLSI integration in terms of local connections and low power consumption.

Time-frequency distributions (TFDs) based on Cohen's class have significant potential for the analysis of nonstationary signals. By employing a linear orthogonal signal expansion followed by nonlinear thresholding cross-terms, it has been shown that the TFD visuality is improved. The main reason for the limited used of TFDs in on-line applications is however their high computational requirement. In this paper, we present a filter bank based architecture which implements efficiently the cross-term reduced computation of TFDs. Its incremental refinement feature allows especially dead-line based real-time processing of time-critical applications. Moreover, the multirate computing provides a vehicle to operate at a reduced rate while still maintaining the overall throughput. The derived architecture is modular with respect to the number of frequencies to be evaluated, the cross-term reduction degree, and the choice of basis filters. The complexity analysis shows that the proposed architecture can indeed reduce the computation burden. Further, the algorithm can be flexibly tailored to available a-priori knowledge about the signal statistics. The regular structure and the underlying multirate FIR filter bank are suitable for VLSI integration.

We examine the promising approach of using Time-Frequency Distributions (TFDs) based on Cohen's class to characterize the unstable operation (stall) of an axial compressor. Stall precursors are time-localized transients which indicate a coming stall inception. Our approach uses the acoustic vibration signal to reveal the nonstationary behavior when approaching the stall region. The results in this paper show that it is possible to visualize stall precursors by relying on the microphone signal which represents a low cost setup compared to the use of a dynamic pressure probe array. To overcome several drawbacks of standard Fourier scheme, we propose the use of a signal-adapted filter bank and TFD based on Cohen's class to achieve enhanced signatures while reducing efficiently the computational requirements.

Shape-adaptive block-based texture coding schemes such as the shape-adaptive DCT (SA-DCT) raise the need for an architecture performing efficiently the transform of variable length N. For an implementation with both standard DCT and SA-DCT required, it is advantageous to have a VLSI architecture which can be configured to compute both schemes. Existing fast algorithms usually consider only the standard DCT of fixed-size length and lack regular structure leading to complex routing. This paper discusses two different architectures satisfying the given requirement in terms of scalability, modularity and regularity. The first proposed architecture represents a time-recursive, fully modular but non-efficient structure regarding the number of operation counts. The second proposed feedforward architecture overcomes problems of numerical instability found in time-recursive structure. Both architectures are modeled in VHDL and synthesized using 0.7 /spl mu/m two metal-layer CMOS technology for comparison. The design in VHDL is kept generic so that new SA-DCT cores can be easily generated to produce application tailored circuits.

The FlexMux specified in MPEG-4 systems merges different ElementaryStreams into one FlexMux channel. Statistical traffic models for the different ElementaryStream types and for the impact of the FlexMux are considered in order to estimate the statistical properties of the FlexMux output. The resulting FlexMux output p.d.f. is used to estimate the CBR channel bandwidth required to limit the loss to a given percentage.

As MPEG-4 uses objects to compose scenes, and each object is transmitted using one or more data streams (e.g. for audio, video base, and video enhancement layers) the network overhead for a single service can be very high. MPEG-4 systems specifies a multiplexing tool to reduce the network overhead. This multiplexer can drop frames, if the frames deadlines and the network channel QoS make a timely transmission impossible. The need to estimate the loss introduced by the multiplexer arises, even more so since MPEG-4 objects appear and disappear at random times, which increases the dynamic of the output traffic specification and QoS renegotiations. We present an approach to estimate the loss introduced by the multiplexer. The approach is based on statistical models for video and audio streams as well as for the dropping multiplexer.

Shape-adaptive block-based texture coding schemes such as the shape-adaptive discrete cosine transform (SA-DCT) raise the need for an architecture which performs efficiently the transform of variable length N. For an implementation requiring standard DCT and SA-DCT, it is advantageous to have a VLSI architecture which can be configured to compute both schemes. Existing fast algorithms usually consider only the standard DCT of fixed-size length and lack regular structure leading to complex routing. This paper discusses two different architectures satisfying the given requirement in terms of scalability, modularity, and regularity. The first proposed architecture represents a time-recursive fully modular, but nonefficient, structure regarding the number of operation counts. The second proposed feedforward architecture overcomes problems of numerical instability found in time-recursive structure. Both architectures are modeled in VHDL and synthesized using an 0.7-/spl mu/m two metal-layers CMOS technology for comparison. The design in VHDL is kept generic so that new SA-DCT cores can be easily generated to produce application tailored circuits.

The time-frequency distribution (TFD) based on Cohen's (see Time-Frequency Analysis. Signal Processing Series. Prentice Hall PTR, New Jersey, 1995) class has significant potential for the analysis of a number of non-stationary signals. One of the discrete formulations is the recently introduced alias-free generalized discrete-time TFD (AF-GDTFD). The spectral decomposition of the kernel allows the computation of AF-GDTFD as a weighted sum of spectrograms. The partial sum has been shown to offer a vehicle to trade-off between exactness and computational load. This paper proposes a scheme which exploits local approximations by adapting dynamically the accuracy of spectrograms to the eigenvalue magnitudes. The approach employs the wavelet packet transform followed by a block-recursive Fourier transform and a compensation network. Adaptive selection of subbands for further processing reduces substantially the computational cost while still preserving an acceptable quality. The approach is attractive in terms of VLSI aspects due to the modular structure, local connections and stream processing.

Shape-assisted block-based texture coding methodologies such as the shape-adaptive DCT raise the need for an architecture which can perform efficiently the transform of variable length N. This paper presents a 1D DCT architecture satisfying the given requirement in terms of scalability and modularity for 2/spl les/N/spl les/8. The architecture employs a canonical-signed-digit serial multiplication to reduce hardware resources and requires only one multiplier to perform the final scaling. A proposed algorithm searching for an optimal assignment of cosine factors leads to a resource saving of about 12% for the multiplication blocks if carry-ripple-adders are assumed to be used. Different area and speed requirements are possible since only feed-forward paths are involved and easily pipelined. The architecture represents a trade-off between time-recursive, fully modular but operation non-efficient structure and multiplication efficient but irregular and fixed-length implementation.

In this paper we describe a novel type of adaptive system and compare its representation and classification performances with classical solutions. The main feature of our system is that it is based on combining simple perceptrons with a compact and simple to implement nonlinear transform defined as a finite recursion of simple nonmonotonic functions. When such a nonlinear recursion replaces the standard output function of a perceptron-like structure, the representation capability of Boolean functions enhances beyond that of the standard linear threshold gate and arbitrary Boolean functions can be learned. While the use of nonlinear recursion at the output accounts for compact learning and memorization of arbitrary functions, it was found that good generalization capabilities are obtained when the nonlinear recursion is placed at the inputs. It is thus concluded that the proper addition of a simple nonlinear structure to the well known linear perceptron removes most of its drawbacks, the resulting structure being compact, easy to implement, and functionally equivalent to more sophisticated neural systems.

We show the results of an empirical comparison using neural network learning methods which reduce the estimation variance by combining the outputs of individual networks. These network topologies are also known as committee or ensemble of networks. Alternatively, we examine constructive networks which adapt their internal complexity, reducing the overfitting problem automatically. Both classes of networks have been compared within the framework of an engine knock detection system taking into account the generalization performance, the network size and the needed computational load for the training procedure.

We show the application of large margin classifiers to the real world problem of engine knock detection. Large margin classifiers, like support vector machines (SVM) or the Adatron, promise a good generalization performance. Furthermore, the support vector approach has some bounds (e.g. for generalization error and learning convergence) which give this technique a more firm background than the neural network leaning algorithms. One drawback of the SVM, especially the Adatron, is that they tend to produce classification systems which need large computational effort for recall. This is caused by the fact that support vectors are normally sparse, but their number of calls is high. Therefore, we propose here a method which prunes (removes) support vectors that are less important. By an adjustment of the training data and remaining steps of the classifier a performance degradation is avoided.

This paper introduces two methods to reduce the training time of large scale support vector machines (SVMs). To optimize a SVM a quadratic optimization problem has to be solved. For large scale applications with many training vectors this can only be done by splitting the data set into smaller pieces called chunks. The chunking algorithms normally start with a random subset. In this paper we propose two methods that can to find a better than a random starting subset, and therefore accelerate the optimization process. They both estimate which training vectors are likely to be support vectors in the final SVM. In the input space this is difficult to determine, because the decision surface can have an (nearly) arbitrary shape. Therefore, this is done in the high dimensional projected space of the SVM.

In this article, we present an approach to automatic generation of communication topologies for statically scheduled systems of subsystems. Given a specification containing a set of processes that communicate via abstract send and receive functions, we show how a cost-efficient communication topology consisting of one or more buses without arbitration scheme can be set up for such applications.

One of the key problems in hardware/software co-design is communication synthesis which determines the amount and type of interconnect between the hardware components of a digital system. To do so, communication synthesis derives a communication topology to determine which components are to be connected to a common communication channel in the final hardware implementation. In this paper, we present a novel approach to cluster processes to share a communication channel. An iterative graph-based clustering algorithm is driven by a heterogeneous cost function which takes into account bit widths, the probability of access collisions on the channels, cost for arbitration logic as well as the availability of interface resources on the hardware components to trade-off cost against performance in a most optimum fashion. The key aspects of the approach are demonstrated on a small example.

The world-wide demands for reasonable fuel consumption and reduced engine emissions force engine developers to improve the combustion process. Automobile makers are expecting to meet these demands by increasing the engine compression ratio. However, this improvement leads back to the problem of engine knock and appropriate engine control. Thus, the ability to detect engine knock with high precision will be mandatory for car makers. We propose a detection scheme that consists of two main blocks: multi-feature extraction and neural classification. This paper gives a short overview of the concept and presents a developed constructive learning algorithm for the cycle-by-cycle detection task.

Besides foundry facilities, Computer-Aided Design (CAD) tools are also required to move microsystems from research prototypes to an industrial market. Currently available CAD tools need extensions before they can be used for the automated design of micromachined devices. This paper presents a low cost access to microsystem technology (MST), applied by the CMP service, and based on the use of existing microelectronics production lines, with additional post-processing for microsystem specific 2D and 3D structures, and a global CAD approach for the design and simulation of microsystems applied to currently available commercial CAD tools, e.g. Mentor Framework, in order t o ensure a continuous flow from the design to the manufacturing.

To adopt behavioral synthesis techniques in existing design flows, the synthesis methodology must provide the designer with a mechanism to specify a component's interface timing. This will permit pre- and postsynthesis validation through cosimulation with other subsystems or even through formal verification. In control-flow dominated designs, additional timing constraints will result in a complex specification/constraint system for which the scheduling problem has been shown to be NP-complete. In this article, we present a mathematical framework for solving a special instance of the scheduling problem in control-flow dominated behavioral VHDL descriptions given that the timing of I/O signals has been completely or partially specified. It is based on a code-transformation approach that fully preserves the VHDL semantics. The scheduling problem is mapped onto an integer linear program (ILP) solvable in polynomial time assuming a restricted partial order on selected statements. It captures both control-flow and timing constraints in a single model and also exploits dataflow information to optimize the statement sequence across basic block boundaries.

A fuzzy rule-based system is presented that can be used to segment an image completely into disjoint regions. Coding the contours of these regions by an advanced chain code leads to an efficient compression scheme that can be utilized, where high compression rates and an acceptable reconstruction quality are needed.

In this paper we investigate the prototype generation of a basic CAN-Bus controller. The controller is modeled as a hierarchical finite-state-machine from which a behavioral VHDL description is generated automatically. After synthesis the device is prototyped using a FPGA-based emulating system. An experimental CAN-Bus system is presented for design validation. We show that this rapid-prototyping approach, which exclusively uses commercial hard- and software, is feasible and has been successful in two respects. The turnaround time for prototyping has been reduced significantly from 2 months for ASIC fabrication to 10 hours while achieving an operation frequency for the very first prototype totalling one fourth of that of the anticipated final system.

In this paper, three types of fuzzy systems and related hardware architectures are discussed: standard fuzzy controllers, FuNe I fuzzy systems, and fuzzy classifiers based on a neural network structure. Two computer-aided design (CAD) packages for automatic hardware synthesis of standard fuzzy controllers are presented: a hard-wired implementation of a complete fuzzy system on a single or multiple field programmable gate arrays (FPGA) and a modular toolbox called fuzzyCAD for synthesis of reprogrammable fuzzy controllers with architectures due to specified designer constraints. In the fuzzyCAD system, an efficient design methodology has been implemented which covers a large design space in terms of signal representations and component architectures as well as system architectures. Very high speed integrated-circuits hardware-description language (VHDL) descriptions and usage of powerful synthesis tools allow different technologies to be targeted easily and efficiently. Properties and hardware realizations of fuzzy classifiers based on a neural network are introduced. Finally, future perspectives and possible enhancements of the existing toolkits are outlined.

Microsystems technology is a rapidly growing field, but engineering tools for microsystems do not appear as fast as the technology is moving. In this paper, we show that methods and tools developed for the information processing units in macro systems, e.g. mechatronic systems, can be reused in microsystems development. The methods and tools we present cover the requirements analysis phase of the product life-cycle. Rapid prototyping is used to validate the user's requirements of the information processing units.

Research in fuzzy neural networks, which started from application oriented fuzzy system tuning, then moving to the automatic generation of fuzzy systems from data, is reaching a more mature stage, especially after the proof of functional equivalence of certain fuzzy models and neural networks. It is essential that the applicability of such developments is explored emphasizing the directions that research should follow. It can be shown that the nearest prototype classifier is functionally equivalent to an alternative fuzzy classifier model. Efficient, hardware friendly training algorithms are developed for dynamic generation of an optimum number of nearest prototypes for neural classifiers which enable the generation of fuzzy systems in real time. These systems are tested with complex applications showing the simulation results.

The focus of this work is on systematic methods for the visualization and quality assessment with regard to classificatio n of multivariate data sets. Our novel methods and criteria give in visual and numerical form rapid insight in the principal data distribution, the degree of compactness and overlap of class regions and class separability, as well as information to identify outliers in the data set and trace them back to data acquisition. Assessment by visualization and numerical criteria can be exploited for interactive or automatic optimization of feature generation and selection/extraction in pattern recognition problems. Further, we provide a novel criterion to assess the credibility and reliability of the visualization obtained from high dimensional data projection. Our methods will be demonstrated using data from visual industrial quality control and mechatronic applications.

Associative systems provide a flexibility ranging far beyond the scope of a conventional associative memory which simply provides a parallel search within a large amount of keywords to retrieve associated information. This paper presents several approaches to associative data processing. Algorithms are discussed that can easily be implemented or supported on an array computer. By means of dedicated VLSI chips a prototype array computer was implemented at Darmstadt University of Darmstadt. Together with simulations on conventional sequential computers, this array computer serves to prove the validity of developed algorithms on a running system.>

The authors present a digital signal processor (DSP) architecture whose powerful CPU is optimized to solve a state variable filter algorithm, but is not limited to that application. State variable filters perform low pass filtering and generate the derivatives of the filtered signal. These signals are used in systems for real-time process identification. In order to minimize the number of components, program and data memory, timers, and peripheral control logic are integrated on the DSP chip. Software development for this DSP is supported by an assembler, simulator and high level language compiler. In addition to the presentation of the architecture, a design methodology is introduced which uses rapid prototyping techniques to verify system design and algorithms in their real-time environment.>

The authors present new ideas in the field of multilevel optimization for automatic logic macrocell synthesis. The proposed new approach performs a quasi parallel optimization of very different and complex tasks via a simulated annealing based expert system. A true design space exploration is achieved, finding the best solution with respect to a certain cost-function which takes into account actual design parameters like speed, area, power, and not only indirect parameters like number of literals, etc. A small prototype software system had been implemented and it is shown how this new approach, e.g. can be used within a module generator.>

The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. For final structural synthesis an advanced tool based on genetic algorithms is provided. Layout synthesis is assumed to be performed by available tools like the GENESIL silicon compiler.>

The authors describe implementation details of a CAD tool for efficient hardware realization of highly parallel algorithms. The Array Specification Language (ASL) of the tool allows the VLSI designer to specify the input not only at dependence graph level, but also at signal/data flow graph and/or array architecture level. Core of this tool is a multilevel functional-structural simulator, embedded into an environment supporting array processor design for real world applications. Another aspect of the tool is the intended support of advanced fault tolerance techniques in an early design phase. More emphasis is given to fabrication-time/run-time fault tolerance techniques and to find a cost-effective solution with the evaluation of optimality criteria and real design tradeoff.>

The authors present a new approach to timing driven partitioning of combinational logic. Instead of accessing a predefined library, complex gates based on the line-of-diffusion layout style are automatically synthesized. A new timing model for complex gates is presented which permits a fast pattern independent timing analysis with a deviation of less than 10% and two to three orders of magnitude faster than the exact SPICE simulation taking into account all parasitics and signal slopes. To improve the overall timing, a heuristic is presented which is based on iterative partitioning techniques for complex gates. The overall performance is demonstrated on several examples.>

An environment is given for fast prototyping of real-time systems. The supported spectrum of realizations for such systems varies from single task implementations on a general purpose microprocessor to heterogeneous multiprocessor systems with application specific processors. The prototyping environment includes a language to describe a real-time system, a compiler that transforms the description into its specified realization format and a hardware environment that is based on a VMEbus system. The VMEbus system includes a Motorola 68020 CPU with multi-tasking operating system and a prototyping board which can be either configured as multi-DSP board or as emulation board for the implementation of an application specific processor architecture.>

Shows how to use a simple associative memory in application areas like pattern recognition. This special kind of associative memory is, owing to the binary weights of the synapses and binary states of its neurons, very suitable for a hardware implementation using digital VLSI technology. Due to the simplicity of the mathematical operations used for programming (training) and the recall phase, it is very fast, even in simulations on sequential computers

In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom design style. Main components of the ALGIC system are a system monitor module, a parameterisable macrocell generator, an appropriate floorplanner with 100% routing solution including planar VDD/GND trees and a block-oriented timing verifier. One essential feature of the system is the high degree of integration between all program modules using the concept of abstract data types. The flexibility and performance of the whole system is demonstrated by real design examples in the field of DSP applications.

The program SCAT is a new timing verifier within the ALGIC silicon compiler. It provides a precise assessment of the timing behaviour of the automatically generated LSI circuits by means of block-oriented statistical algorithms leading to a running time approximately linear to the number of circuit elements, which are emulated by delay time elements. Interconnect delays are handled by the same statistical model. Synchronous circuits are described by an appropriate coordinate transformation leading to an algorithm for the calculation of the minimum clock period. The special case of recursive structures is briefly mentioned.