This paper presents a study of MENTOR, a web adaptive educational environment (WBES), where the learnerpsilas needs and preferences are diagnosed using an ontology-based Bayesian network approach during the learning process. Firstly, the proposed method uses an OWL ontology to store the affective knowledge regarding the learner. Then, this ontology is extended appropriately to deal with uncertainty so that a Bayesian network (BN) can be constructed from it. Finally, using the derived BN we can make inferences and reasoning on the learnerpsilas individual needs. In this way we form a schema where the uncertain affective information (AfI) can be represented efficiently and exploited properly in order to maintain the efforts of a learner. Therefore, based on this model we can detect the learnerpsilas affective model and to support his efforts during the learning process by suggesting the proper pedagogical guidance.

In this paper a Web-Based Adaptive Educational System to support personalized distance learning, which is named MENTOR is presented. The main purpose of MENTOR is to support learner’s actions during the learning process in an affective way. To achieve this MENTOR incorporates an affective module which enhances the traditional learning practices with an affective dimension. The affective module makes use of an ontological approach in combination with the Bayesian Network model in order to provide learner with the properly affective guidance. In this way the foremost goal of MENTOR, which is to supply the learner with a personalized and emotional awareness learning environment, is achieved.

Hierarchically structured data collections often need to be visualized for the purposes of digital information management and presentation. File browsing, in particular, has an inherent hierarchical structure and plays an important role in the context of personal information management (PIM). A multitude of file browsers are nowadays available, offering different functionalities, while users adopt diverse practices and habits for browsing activities. In this paper, we investigate these aspects to obtain insights into their advantages and disadvantages and suggest solutions in the area of PIM, as well as in other domains employing similar visualization paradigms. The presented study focuses on the two most widespread visualizations used by file browsers, the indented list and zoomable interface paradigms, and assesses their effectiveness for various tasks and contexts, both by exploiting results on existing evaluations on hierarchy visualizations and folder hierarchy visualizations in particular, and by conducting an interview-based user study.

The on-going progress in the area of digital libraries has lead to the beginning of a digitization effort in Historical Archives, as well. The requirements of historical research, which works with histories of entities and incomplete information, create the need for supplementary tools to support users in handling the digitized content. This work is based on a user study of historian information retrieval methods in order to create a set of tools for the context of historical archives, which will facilitate historical data storage, management and visualization.

The need for effective ontology visualization for design, management and browsing has arisen as a result of the progress in the areas of semantic Web and personal information management. There are several ontology visualizations available through existing ontology management tools, but not as many evaluations to determine their advantages and disadvantages and their suitability for various ontologies and user groups. This work presents selected results of an evaluation of four visualization methods in Protege.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

In this paper we present a new text line detection method for unconstrained handwritten documents. The proposed technique is based on a strategy that consists of three distinct steps. The first step includes image binarization and enhancement, connected component extraction and average character height estimation. In the second step, a block-based Hough transform is used for the detection of potential text lines while a third step is used to correct possible splitting, to detect text lines that the previous step did not reveal and, finally, to separate vertically connected characters and assign them to text lines. The performance evaluation of the proposed approach is based on a consistent and concrete evaluation methodology.

Most ontology development methodologies and tools for ontology management deal with ontology snapshots, i. e. they model and manage only the most recent version of ontologies, which is inadequate for contexts where the history of the ontology is of interest, such as historical archives. This work presents a modeling for entity and relationship timelines in the Protégé tool, complemented with a visualization plug-in, which enables users to examine entity evolution along the timeline.

Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operation. Since software-based self-test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications, optimal test period specification is becoming increasingly challenging. In this paper we first introduce a reliability analysis for optimal periodic testing of intermittent faults that minimizes the test cost incurred based on a two-state Markov model for the probabilistic modeling of intermittent faults. Then, we present for the first time an enhanced SBST strategy for on-line testing of complex pipelined embedded processors. Finally, we demonstrate the effectiveness of the proposed optimal periodic SBST strategy by applying it to a fully-pipelined RISC embedded processor and providing experimental results

Digital libraries and historical archives are increasingly employing visualization systems to facilitate the information retrieval and knowledge extraction tasks of their users. Typically, each organization employs a single visualization system, which may not suit best the needs of certain user groups, specific tasks, or properties of document collections to be visualized. In this paper, we present a context-based adaptive visualization environment, which embeds a set of visualization methods into a visualization library, from which the most appropriate one is selected for presenting information to the user. Methods are selected by examining parameters related to the user profile, system configuration and the set of data to be visualized, and employing a set of rules to assess the suitability of each method. The presented environment additionally monitors user behavior and preferences to adapt the visualization method selection criteria

The continuing need for more effective information retrieval has lead to the creation of the notions of the semantic Web and personalized information management, areas of study that very often employ ontologies to represent the semantic context of a domain. Consequently, the need for effective ontology visualization for design, management and browsing has arisen. There are several ontology visualizations available through the existing ontology management tools, but not as many evaluations to determine their advantages and disadvantages and their suitability for various ontologies and user groups. This work presents the preliminary results of an evaluation of four visualization methods in Protege

Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit under test continues to operate correctly in field. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform all types of testing, namely manufacturing, periodic off-line and concurrent on-line. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing. In this paper a novel input-vector monitoring concurrent BIST scheme based on a pre-computed test set is introduced. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both on line and off-line testing

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.

In this paper a novel input vector monitoring concurrent BIST technique based on a RAM (R-CBIST) is presented. This technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be used in practice for exhaustive testing of ROMs since it results in small hardware overhead whereas no need to stop the ROM normal operation is required.

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test sequence is long, the time required for all the test vectors to appear among the normal inputs to the circuit (test latency) is significantly long. Modifications of the C-BIST technique have been proposed in order to reduce the test latency. In this paper we propose a new C-BIST technique termed windowed-CBIST (w-CBIST) for test latency reduction. The proposed technique is shown to be significantly more efficient from the previous methods with respect to test latency and hardware overhead.

Encapsulation constructs with import/export declarations is the structuring facility offered in most commercial Prolog systems. However, real-life applications have shown to require a finer information exchange between encapsulated pieces of code. A refinement of import/export declarations for logic modules is presented both as a stricter form of communication between the modules and as a larger variety of visibility states of the predicates, the standard approaches being special cases of it. The semantics of this module system has been examined and model-theoretic, fixpoint and operational ones have been given and have been proved to be equivalent. In addition, the module system has been naturally transformed to Horn clause logic.>

A design method for a combinational totally self-checking (TSC) 1-out-of-3 code checker is presented. This method is not only simpler and more efficient than others, but is also successful in the case where more than one 1-out-of-3 code exists in a TSC system.>

A design method of totally self-checking (TSC) m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing up the ones received on m input lines, and a k-variable two-pair two-rail code tree that compares the outputs of the two-adder tree. The only modules used are full-adders, half-adders, and two-variable TSC two-rail code checkers. This method is well suited for VLSI MOS implementation and, compared to previous methods, it results in significant circuit cost reduction and smaller test set, without sacrificing performance. Also, the proposed design has the advantages of a modular design.>

The paper presents a new method for designing efficient TSC checkers for m-out-of n codes. The method is based on the partitioning of the input code variables into an arbitrary number of r classes. The paper establishes the necessary design conditions that must hold among m, n and r. The checker is basically composed of an m/n to l/z subchecker concatenated with an l/z to 1/2 subchecker. A cost analysis performed reveals that the most economical checkers are obtained for values of r equal to 3, or 4 for the majority of m/n codes with n ≤ 4m. Comparison with earlier designs reveals impressive improvement both in logic complexity and testing complexity.

This paper considers AN arithmetic codes with radix r > 2 and binary-coded digits (BCr) using weights. The error-correcting capability of the AN codes is single bit within any BCr digit, that is, the corrected errors are of the form ± wirj where wi are the weights of the BCr code. The paper characterizes a class of AN codes having a generator of the form A = r · p where r|r − 1 or τ|r + 1 and p prime is greater than r − 1 or r + 1. It is shown that these codes, under certain conditions, are near perfect.

This paper presents a new class of AN codes of high efficiency capable of correcting single errors in radix-r arithmetic with the binary coded digits—BCr—system. The errors corrected within a single radix-r digit are single errors of the binary digits with weight ±wi≤ r–1,i=1,2,···, m, which are used to encode the BCr digits. The corresponding arithmetic unit is made out of slices, one for each BCr digit. The AN codes considered have a generator A of the form A = τ·p where τ, p odd and rp=n-1 ≤ τk± 1. The criteria are applied to the BCD system, and we determine all τ < 100 and p < 200 for the most important BCD codes with weights ± wi < r –1, i = 1, 2, 3, 4. For each BCD code, the paper gives the numbers τ < 100 for which AN codes exist, and the maximum code efficiency E = 2·m·k/(A-1) attained at some p < 200.

This note is concerned with the design of fast totally self-checking checkers for m-out-of-(2m ± 1) codes. The new method uses only three levels of gates, and is based on the partitioning of the input lines into m blocks of two lines per block except for the last block. A first level of two-input AND and OR gates realizes the majority functions T(ki ≥ 1) and T(ki ≥ 2). These are combined through AND gates of a second level into the so-called product functions Pj1j2...jm, one for each class of input codewords that have jl, j2,···, jm 1's in the corresponding blocks of the input lines. Finally, two OR gates (third level) partition the product functions into two. The property of totally self-checking operation is achieved through the proper partitioning of the product functions into two classes. This note presents a systematic method of such partitioning. Also, the note determines the cost of these checkers and compares them to previous designs.

The microprogrammed filter engine (MICE) is a fast, microprogrammable processor built with ECL bit slices (Motorola ECL 10800 series) intended primarily to be used as an on-line data filtering engine for high energy physics experiments. In this note we describe the use of a hardware description language used to model and simulate the hardware during its development. We treat the problem of describing a pipelined, horizontal (112 bits wide) host machine, implemented using bit slices with considerable potential for parallelism. Several levels of modeling are conceptually applicable to a problem of this nature and the note describes the thorough process followed before we decided on a particular style of description and simulation.

This paper describes architectural considerations which led to the design of a fast programmable processor made from ECL bit-slioes. The processor will be used as an on-line data filtering engine for high energy physics experiments. Unlike prior designs of such engines, the processor supports both user (horizontal) microcode and emulation of the PDP-11 fixed point instruction set (without memory management and multiple interrupt levels). In addition to an overview of the techniques used to achieve an execution speed of roughly three times that of the PDP-11/70 CPU, strengths and weaknesses of bit- slices are discussed, as are the use of a Signetics meta assembler and the ISPS Architecture simulation system.

The correspondence deals with the fail-safe realization of synchronous sequential machines under the assumption that the next-state functions are in any positive form. This leads to new classes of assignments called positive fail-safe assignment's (PFSA) The feasibility conditions of such assignments are given and systematic procedures are presented for deriving them using k-out-of-n codes.

A new type of double-rank sequential circuit is presented in this paper. This new type, called Type 4, differs from its predecessor types in that it employs a Boolean memory as rank-1 memory instead of flip-flops. The Boolean memory used is an aggregate of symmetric Boolean memories with 1-out-of-n state encodings. A procedure for realizing a sequential machine by a Type 4 double-rank sequential circuit is also presented in the paper.

A new approach is presented for the minimization of the word length of the control store in microprogrammed computers. Given the set of microinstructions and the set of microcommands of a microprogrammed computer a minimal subset of microcommands are determined so that every other microcommand not contained in this minimal subset to be generated from it by a single AND or OR gate. The problem of finding such minimal subsets of microcommands is formulated as a Boolean function simplification problem and is based upon an extension of the notion of the minimal dependence sets of a Boolean function.

A new method is presented for determining all minimal dependence sets, irredundant normal forms, and irredundant normal forms of minimal dependence sets of a Boolean function f. The method reduces the above problems into those of determining all minimal positive dependence sets, irredundant positive normal forms, and irredundant positive normal forms of minimal positive dependence sets, respectively, of a Boolean function f* corresponding to f. For each problem a corresponding cover formula is developed such that the prime implicants of it are in one-to-one correspondence to all possible solutions.

The paper presents systematic procedures for decomposing a sequential machine into submachines some or all of which are realized by polylinear sequential circuits. This polylinear decomposition is based upon classes of subsets of the set of states which possess the substitution property rather than upon partitions with substitution property. These classes are easily found using the backward state transition function of the machine and enables one to treat uniformly and simultaneously the problems of state minimization, machine decomposition in the classical or the polylinear way, finding the lattice of the partitions with substitution property, and periodic decomposition based upon classes that correspond to cyclic partitions. Procedures are developed for deriving optimal all polylinear decompositions and "good" partial polylinear decompositions of a machine.

This correspondence presents a new unified approach for defining and finding the various types of partition pairs ("d", "t","r","j") of a sequential machine. The notion of separation (distinguishability) of states is the key factor of the new approach. By this and the notion of transition sets one can easily find all maximal partitions τ which are in "d","t","r", and "j" relation with a given partition ρ.