The CoMetS track aims to bring together leading researchers and practitioners from both the modeling and simulation (M&S) community and the collaborative environments community, in order to focus on innovative research contributions that address both the use of collaborative technologies in the field of M&S and the use of M&S methodologies and tools to address the design of collaborative systems. This paper reports on the motivations of the track and the organization of its fourth edition.

The performance analysis of parallel algorithms and systems is considered. For these, numerical solutions methods quickly show their limits because of the enormous state-space growth. The proposed methodology and software tool, list-manipulation parallel-modeling package (LISPACK) uses string manipulation, lumping, and recursive elimination to define the large Markovian process, its restructuring, and efficient solution. The analysis of a typical parallel system and algorithm model is developed as a case study, to discuss the features of the method. The paper has two contributions. The first is the symbolic-approach methodology proposed for the performance analysis of parallel algorithms and systems. The second is a tool that exploits the capabilities of the symbolic approach in the solution of parallel models, where the numerical techniques reveal their limits.>

A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each state represents an operating chip configuration, and the state transitions take place in the presence of manufacturing defects. Results from the comparison of this method to a method for memory chip yield evaluation, a method for the M-out-of-N yield problem evaluation, and a method for the square grid chip yield evaluation are presented.>

Conventional M-out-of-N yield models can only roughly represent many practical chip architectures. On the other hand, representative models have the drawback of computational complexity. A yield model is introduced that overcomes the limits of existing models and provides ease of computation and predictability in approximation levels. The model is versatile enough to be included in CAM/CAD programming environments. Some application examples are given to illustrate the model accuracy, ease of use, and flexibility.>

The mathematics of product-form queueing networks has traditionally dealt with the "analysis" of computer systems. That is, the system is assumed to be given and the question of how it performs is answered. In this paper the opposite process of system "synthesis" is dealt with: i.e., we answer the question of what the system topology and parameters should be in order to achieve a given performance objective. Possible research and industry applications range from the hierarchial top-down design of software systems to the management and design of computer installations.

Given a closed BCMP queueing network, the problem is considered of studying the behavior of any subsystem a without solving for the entire system. This paper proves that this is possible for a consisting of any number of queues, arbitrarily interfacing the rest of the system, thus generalizing the classic CHW theorem, also known as Norton's theorem. A general flow-equivalent solution procedure is given and its computational complexity is compared with that of the product-form and the exact aggregation procedure. The relative merits of these procedures are also expressed in terms of a's cardinality.