This paper introduces three autonomous, criticality-aware packet scheduling policies that address the impact of high traffic loads and degraded conditions in wireless sensor networks. The proposed policies, collectively referred to as Early Packet Drop (EPD), leverage cross-layer information, including RPL Rank, link quality, and time-slotted Medium Access Control schedule, to mitigate Quality of Service degradation. Simulation results demonstrate that EPD consistently outperforms a Criticality-Monotonic Scheduling (CMS) baseline.

This article considers the use of routerless networks-on-chip as an alternative on-chip interconnect for multi-processor systems requiring hard real-time guarantees for inter-processor communication. It presents a novel analytical framework that can provide latency upper bounds to real-time packet flows sent over routerless networks-on-chip, and it uses that framework to evaluate the ability of such networks to provide real-time guarantees. Extensive comparative analysis is provided, considering different architectures for routerless networks and a state-of-the-art wormhole network based on priority-preemptive routers as a baseline.

Edge computing has gained attention in recent years due to the adoption of many Internet of Things (IoT) applications in domestic, industrial and wild settings. The resiliency and reliability requirements of these applications vary from non-critical (best delivery efforts) to safety-critical with time-bounded guarantees. The network connectivity of IoT edge devices remains the central critical component that needs to meet the time-bounded Quality of Service (QoS) and fault-tolerance guarantees of the applications. Therefore, in this work, we systematically investigate how to meet IoT applications mixed-criticality QoS requirements in multi-communication networks. We (i) present the network resiliency requirements of IoT applications by defining a system model (ii) analyse and evaluate the bandwidth, latency, throughput, maximum packet size of many state-of-the-art LPWAN technologies, such as Sigfox, LoRa, and LTE (CAT-M1/NB-IoT) and Wi-Fi, (iii) implement and evaluate an adaptive system Resilient Edge and Criticality-Aware Best Fit (CABF) resource allocation algorithm to meet the application resiliency requirements using Raspberry Pi 4 and Pycom FiPy development board having five multi-communication networks. We present our findings on how to achieve 100% of the best-effort high criticality level message delivery using multi-communication networks.

This paper proposes two approaches to managing the workload of multiple instances of genetic algorithms (GAs) running as containers over a cloud environment. The aim of both approaches is to obtain, for as many instances as possible, a GA output which achieves a user-defined fitness level by a user-defined deadline. To reach such a goal, the proposed approaches allocate the GA containers to cloud nodes and carefully control the execution of every GA instance by forcing them to run in stages. The paper proposes two approaches, fitness tracking (FT) and fitness prediction (FP), with both approaches compared against state-of-the-art container-based orchestration approaches.

The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

This article describes the motivation, design, analysis, and configuration of the criticality-aware multi-hop wireless communication protocol AirTight. Wireless communication has become a crucial part of the infrastructure of many cyber-physical applications. Many of these applications are real-time and also mixed-criticality, in that they have components/subsystems with different consequences of failure. Wireless communication is inevitably subject to levels of external interference. In this article, we represent this interference using a criticality-aware fault model; for each level of temporal interference in the fault model, we guarantee the timing behaviour of the protocol (i.e., we guarantee that packet deadlines are satisfied for certain levels of criticality). Although a new protocol, AirTight is built upon existing standards such as IEEE 802.15.4. A prototype implementation and protocol-accurate simulator have been produced. This article develops a series of schedulability analysis techniques for single-channel and multichannel wireless Cyber-Physical Systems (CPS). Heuristics are specified and evaluated as the starting point of design space exploration. Genetic algorithms are then defined and evaluated to assess their performance in developing schedule tables incorporating multichannel allocations in these systems.

Industrial wireless sensor networks usually have a centralized management approach, where a device known as network manager is responsible for the overall configuration, definition of routes, and allocation of communication resources. Graph routing is used to increase the reliability of communication through path redundancy. Some of the state-of-the-art graph-routing algorithms use weighted cost equations to define preferences on how the routes are constructed. The characteristics and requirements of these networks complicate to find a proper set of weight values to enhance network performance. Reinforcement learning can be useful to adjust these weights according to the current operating conditions of the network. In this article, we present the Q-learning reliable routing with a weighting agent approach, where an agent adjusts the weights of a state-of-the-art graph-routing algorithm. The states of the agent represent sets of weights, and the actions change the weights during network operation. Rewards are given to the agent when the average network latency decreases or the expected network lifetime increases. Simulations were conducted on a WirelessHART simulator considering industrial monitoring applications with random topologies. Results show, in most cases, a reduction of the average network latency while the expected network lifetime and the communication reliability are at least as good as what is obtained by the state-of-the-art graph-routing algorithms.

In smart factories, process planning and scheduling need to be performed every time a new manufacturing order is received or a factory state change has been detected. A new plan and schedule need to be determined quickly to increase the responsiveness of the factory and enlarge its profit. Simultaneous optimisation of manufacturing process planning and scheduling leads to better results than a traditional sequential approach but is computationally more expensive and thus difficult to be applied to real-world manufacturing scenarios. In this paper, a working approach for cloud-based distributed optimisation of process planning and scheduling is presented. It executes a multi-objective genetic algorithm on multiple subpopulations (islands). The number of islands is automatically decided based on the current optimisation state. A number of test cases based on two real-world manufacturing scenarios are used to show the applicability of the proposed solution.

This paper assesses the potential for mechanised assistance in the formulation of schedulability tests. The novel idea is to use evolutionary algorithms to semi-automate the process of deriving response time analysis equations. The proof of concept presented in this paper focuses on the synthesis of mathematical expressions for the schedulability analysis of messages on Controller Area Network (CAN). This problem is of particular interest, since the original analysis developed in the early 1990s was later found to be flawed. Further, as well as known exact tests that have been formally proven, there are a number of useful sufficient tests of pseudo-polynomial complexity and closed-form polynomial-time upper bounds on response times that provide useful comparisons.

XDense is a novel wired 2D mesh grid sensor network system for application scenarios that benefit from densely deployed sensing (e.g., thousands of sensors per square meter). It was conceived for cyber-physical systems that require real-time sensing and actuation, like active flow control on aircraft wing surfaces. XDense communication and distributed processing capabilities are designed to enable complex feature extraction within bounded time and in a responsive manner. In this article, we tackle the issue of deterministic behavior of XDense. We present a methodology that uses traffic-shaping heuristics to guarantee bounded communication delays and the fulfillment of memory requirements. We evaluate the model for varied network configurations and workload, and present a comparative performance analysis in terms of link utilization, queue size, and execution time. With the proposed traffic-shaping heuristics, we endow XDense with the capabilities required for real-time applications.

This paper aims to reduce the pessimism of the analysis of the multi-point progressive blocking (MPB) problem in real-time priority-preemptive wormhole networks-on-chip. It shows that the amount of buffering on each network node can influence the worst-case interference that packets can suffer along their routes, and it proposes a novel analytical model that can quantify such interference as a function of the buffer size. It shows that, perhaps counter-intuitively, smaller buffers can result in lower upper-bounds on interference and thus improved schedulability. Didactic examples and large-scale experiments provide evidence of the strength of the proposed approach.

A system's ability to precisely locate itself in a known physical environment is key to its capacity to interact with the environment in an intricate manner. The indoor localisation problem has been approached in a variety of ways, ranging from the identification of pre-defined features or topologies to the more general cloud-point matching.

There is increasing impetus towards 'Industry 4.0', a recently proposed roadmap for process automation across a broad spectrum of manufacturing industries. The proposed approach uses Evolutionary Computation to optimise real-world metrics. Features of the proposed approach are that it is generic (i.e. applicable across multiple problem domains) and decentralised, i.e. hosted remotely from the physical system upon which it operates. In particular, by virtue of being serverless, the project goal is that computation can be performed 'just in time' in a scalable fashion. We describe a case study for value-based optimisation, applicable to a wide range of manufacturing processes. In particular, value is expressed in terms of Overall Equipment Effectiveness (OEE), grounded in monetary units. We propose a novel online stopping condition that takes into account the predicted utility of further computational effort. We apply this method to scheduling problems in the (max, +) algebra, and compare against a baseline stopping criterion with no prediction mechanism. Near optimal profit is obtained by the proposed approach, across multiple problem instances.

Recently, an increasing number of public cloud vendors added Containers as a Service (CaaS) to their service portfolio. This is an adequate answer to the growing popularity of Docker, a software technology allowing Linux containers to run independently on a host in an isolated environment. As any software can be deployed in a container, the nature of containers differs and thus assorted allocation and orchestration approaches are needed for their effective execution. In this paper, we focus on containers whose execution value for end users varies over time. A baseline and two dynamic allocation algorithms are proposed and compared with the default Docker scheduling algorithm. Experiments show that the proposed approach can increase the total value obtained from a workload up to three times depending on the workload heaviness. It is also demonstrated that the algorithms scale well with the growing number of nodes in a cloud.

The problem of mapping hard real-time tasks onto networks-on-chip has previously been successfully addressed by genetic algorithms. However, none of the existing problem formulations consider memory constraints. State-of-the-art genetic mappers are therefore able to find fully-schedulable mappings which are incompatible with the memory limitations of realistic platforms. In this paper, we extend the problem formulation and devise a memory architecture, in the form of private local memories. We then propose three memory models of increasing complexity and realism, and evaluate the impact these additional constraints pose to the genetic search. We conduct extensive experiments using tasks and communications from a realistic benchmark application, and compare the proposed approach against a state-of-the-art baseline mapper.

This paper describes the motivation, design, analysis and implementation of a new protocol for critical wireless communication called AirTight. Wireless communication has become a crucial part of the infrastructure of many cyber-physical applications. Many of these applications are real-time and also mixed-criticality, in that they have components/subsystems with different consequences of failure. Wireless communication is inevitably subject to levels of external interference. In this paper we represent this interference using a criticality-aware fault model; for each level of interference in the fault model we guarantee the timing behaviour of the protocol (i.e. we guarantee that packet deadlines are satisfied for certainly levels of criticality). Although a new protocol, AirTight is built upon existing standards such as IEEE 802.15.4. A prototype implementation and protocol-accurate simulator, which are also built upon existing technologies, demonstrate the effectiveness and functionality of the protocol.

In this paper, we introduce a multicore response time analysis ( MRTA ) framework , which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

XDense is a novel wired 2D-mesh grid sensor network system for application scenarios that benefit from densely deployed sensing (e.g. thousands of sensors per square meter). It was conceived for closed-loop cyber-physical systems (CPS) that require real-time actuation, like active flow control (AFC) on aircraft wing surfaces. XDense communication and distributed processing capabilities are designed such that they enable to extract complex features within bounded time and in a responsive manner. In this paper we tackle the issue of deterministic behavior of XDense. We present a methodology that uses traffic shaping heuristics to guarantee bounded communication delays and the fulfillment of memory requirements. We evaluate the model for varied network configurations and workload, and demonstrate the effectiveness of running real-time applications supported on XDense.

Eboracum is an extensible modeling simulation framework for evaluation of reactive and adaptable wireless sensor networks (WSN), which provides high-level primitives for modeling platform and application aspects of WSNs. Combining application to environment-generated workload and computing/communication infrastructure, this framework allows to evaluate the efficiency of WSN configurations with regards to metrics that are meaningful to specific application domains and respective end-users. In this work, we demonstrate that Eboracum can be easily extended to support different types of nodes, events, as well as dynamic adaptability strategies. Moreover, this work discusses how to employ Eboracum to evaluate load balancing strategies and describe two different realistic scenarios, extending its primitives, for instance, to support mobile nodes and trigger events.

Genetic Algorithms (GAs) following a parallel master-slave architecture can be effectively used to reduce searching time when fitness functions have fixed execution time. This paper presents a parallel GA architecture along with two accelerated GA operators to enhance the performance of masterslave GAs, specially when considering fitness functions with variable execution times. We explore the performance of the proposed approach, and analyse its effectiveness against the state-of-the-art. The results show a significant improvement in search times and fitness function utilisation, thus potentially enabling the use of this approach as a faster searching tool for timing-sensitive optimisation processes such as those found in dynamic real-time systems.

This paper presents an energy aware resource allocation approach that benefits from modal nature of hard real-time systems under consideration. The modal nature of considered applications made it possible to decrease the number of active cores consuming high power in certain modes or to switch into core states with lower power consumption, which lead to considerable energy savings while still not violating any of timing constraints. For the considered automotive use case, the number of required cores has been decreased by up to 75% in a particular mode and relatively low amount of data is to be migrated during the mode change. The trade-off between the amount of data to be migrated and energy dissipation in the subsequent state is also analysed.

Modern high performance computing (HPC) data centers consume huge energy to operate them. Therefore, appropriate measures are required to reduce their energy consumption. Existing efforts for such measures focus on consolidation and dynamic voltage and frequency scaling (DVFS). However, most of them do not perform adaptive resource allocation for the executing dependent tasks (or jobs) in order to optimize both value and energy. The value is achieved by completing the execution of a job and it depends on the completion time. A high value is achieved if the job is completed before its deadline, otherwise a lower value. In this paper, we propose an adaptive resource allocation approach that uses design-time profiling results of jobs for efficient allocation and adaptation in order to optimize both value and energy while executing dependent tasks. The profiling results for each job are obtained by exploiting efficient allocation combined with identification of voltage/frequency levels of used system cores and used in adapting to different number of cores based on the monitored execution progress of the job and available cores. Experiments show that the proposed approach enhances the overall value by about 10% when compare to existing approaches while showing reduction in energy consumption and percentage of rejected jobs leading to zero value.

Flit-level preemptions via virtual channels have been proposed as one viable method to implement priority-preemptive arbitration policies in NoC routers, and integrate NoCs in the hard real-time domain. In recent years, researchers have explored several aspects of priority-preemptive NoCs, such as different arbitration techniques, different priority assignment methods (where applicable) and different workload mapping approaches, all with the common objective to use interconnect mediums more efficiently. Yet, the impact of different routing techniques on such a model is still an unexplored topic. Motivated by this reality, in this work we study the effects of routing flexibility on wormhole-switched priority-preemptive NoCs.

The conventional approaches to reduce the energy consumption of high performance computing (HPC) data centers focus on consolidation and dynamic voltage and frequency scaling (DVFS). Most of these approaches consider independent tasks (or jobs) and do not jointly optimize for energy and value. In this paper, we propose DVFS-aware profiling and non-profiling based approaches that use design-time profiling results and perform all the computations at run-time, respectively. The profiling based approach is suitable for the scenarios when the jobs or their structure is known at design-time, otherwise, the non-profiling based approach is more suitable. Both the approaches consider jobs containing dependent tasks and exploit efficient allocation combined with identification of voltage/frequency levels of used system cores to jointly optimize value and energy. Experiments show that the proposed approaches reduce energy consumption by 15% when compared to existing approaches while achieving significant amount of value and reducing percentage of rejected jobs leading to zero value.

Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first aim is to improve the average latency of low-criticality packets following a mode change by allowing NoC arbiters to service them during cycles in which no high-criticality flows can be transmitted. The second aim is to reduce the worst-case latency of high-criticality packets transmitted by the NoC. The former objective improves the system's responsiveness, while the latter contributes to increased resource efficiency. The achieved improvements are evaluated, respectively, by cycle-accurate simulation and by schedulability analysis, showing full delivery of low-criticality packets following a criticality change, and achieving full schedulability in 8.2% more flow sets than the state of the art.

Hard-real time video systems require deterministic admission control decisions to maintain high levels of predictability. These decisions can be based on the state-of-the-art schedulability analysis of tasks and flows. However, due to the pessimistic behaviour of the schedulability analysis and the uncertainties in the application, the multi-core system resources are usually under-utilised. In this paper we propose two task allocation techniques that exploit application and platform characteristics in order to increase the number of simultaneous, fully schedulable, video streams handled by the system. The first, more generic technique, uses the worst-case remaining slack of the mapped tasks as a heuristic to determine the task to processing core allocation. The paper also investigates a second technique that maps the heavily communicating, critical path tasks of the applications onto same core to reduce the communication overhead. We compare against other heuristic based dynamic mapping techniques in the literature, and show that an overall improvement of up to 10%-15% can be obtained, in admission rates and system utilisation.

Arbitration policies and predictability enhancement measures typically employ packet priority as the decisive parameter. Though packet timeliness is a key attribute, Network-on-Chip designs rarely consider timeliness as a parameter mostly due to the impracticality of utilising time stamping which relay on the notion of a global time. In this paper, we introduce a low overhead approach where packets carry a slack value, which would notify the router of the latency the packet can suffer without any adverse effects. This would enable routers to service late packets (even lower priority ones) by trading the expendable time associated with the high priority packets hence improving overall quality of service. Utilising a Hardware Description Language coded prototype, we demonstrate the effectiveness of the technique and quantify the associated hardware overhead.

A task mapping is deemed feasible for a hard real-time embedded system if the end-to-end response times of all tasks, which include the computation and the communication delays, does not exceed their deadlines. In this paper, we propose a new fitness function based on the concept of breakdown frequency to address the task mapping optimisation problem of hard real-time embedded systems. As a property of task mapping, the breakdown frequency is the minimal operating frequency under which a task set and its messages are able to execute in any scenario without missing their deadlines. With the frequency, unschedulable tasks and messages can become schedulable without changing the task mapping itself. These advantages are difficult to find in the state-of-the-art optimisation techniques that use the number of unschedulable tasks or latency as the property of task mapping. Results from the case studies suggest that the proposed function enables a wider design space exploration, allowing designers to easily trade-off operating frequency and core count without sacrificing hard real-time schedulability.

In a hard real-time embedded system based on a fixed priority pre-emptive Networks-On-Chip (NoC), the provision of guaranteed services may require pre-emption of some tasks and messages based on their priorities. In a worst case scenario, the interference imposed to low priority tasks can cause substantial computation and communication delays that can exceed their deadlines, leading to an unschedulable system. In a task mapping optimisation process, changing task mappings does not always produce a schedulable task mapping. In this paper, we propose an approach that simultaneously optimises task mapping and priority assignment, aiming to find a configuration that can completely satisfy the timing constraints of the system. Differing to the state-of-the-art, our approach takes into account the overall schedulability of the system by considering the worst-case end-to-end response time of all mapped tasks. As a result, we are able to increase the quality of task mappings at the same time improving the convergence of the optimisation algorithm, better than the previous approaches that solely focus on the task mapping optimisation to make the system schedulable.

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect.

Wireless Sensor and Robot Networks (WSRNs) are heterogeneous collections of sensor nodes and robotic vehicles that communicate wirelessly. In the last decade many research studies have attempted to address the challenging trade-offs of Wireless Sensor Networks (WSNs) that arise due to their resource limitations, however, much work is still to be done. A recent trend is to merge different subclasses of cyber-physical systems together to achieve the desired performance goals by benefiting from their heterogeneity. This paper presents a bio-inspired robot guidance technique that is used to improve network coverage, increase service availability and minimise energy consumption of WSNs using robotic agents on vehicles. We explore the performance consequences of the Pheromone Signalling-based Load Balancing (PS) Robot Guidance on an abstract level simulator which provides a system perspective. The effectiveness of the algorithm is evaluated with different network topologies and investigated on various scenarios. Simulated experimental results on mesh and sparse topologies validate that robot guidance based on PS increases network lifetime.

Performance predictability enhancement in Network-on-chip routers are usually brought about by employing techniques like Time Division Multiplexing or Virtual Channels, which comes with overheads in area and energy which can be substantial. With this paper, we present an alternative approach that can emulate the effect of preemption without the major area overheads which are associated with preemption implementation. The technique employs routers capable of splitting low priority packets (rather than preempting) when a higher priority packet is encountered which is destined to use the same link. This splitting would hence allow the high priority packet to have the same effect as if the low priority packet was preempted while having lower implementation overhead as the splitting logic is simpler. We test the technique with different traffic scenarios and load levels, and analyse performance merits as well as implementation overheads.

Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.

Performance predictability in Networks-on-Chip usually comes with high area and energy overheads. As an alternative approach, this paper presents a low overhead technique called Priority Forwarding and Tunnelling (PFT) which aims to enhance performance predictability in simple non-preemptive NoC routers. It addresses the negative impact of Head-of-line (HOL) blocking by temporarily boosting the priority of low priority packets that prevent the timely transmission of high priority packets. Further HOL blocking is prevented by opening priority tunnels across the NoC, preventing lower priority packets from acquiring output ports that will be needed by high priority packets in the near future. Extensive evaluation using the R3 NoC under different traffic loads shows the effectiveness of the proposed technique and quantifies the required hardware overheads.

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

This article explores the use of virtualization to enable mechanisms like task migration and dynamic mapping in heterogeneous MPSoCs, thereby targeting the design of systems capable of adapt their behavior to time-changing workloads. Because tasks may have to be mapped to target processors with different instruction set architectures, we propose the use of Low Level Virtual Machine (LLVM) to postcompile the tasks at runtime depending on their target processor. A novel dynamic mapping heuristic is also proposed, aiming to exploit the advantages of specialized processors while taking into account the overheads imposed by virtualization. Extensive experimental work at different levels of abstraction---FPGA prototype, RTL and system-level simulation---is presented to evaluate the proposed techniques.

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

Networks-on-Chip (NoC) allow several data transfers to occur in parallel and are indeed the communication infra-structure of future hundred-cores Systems-on-Chip (SoCs). However, if specialized modules are sending data at full speed to the NoC, Quality of Service (QoS) can be no longer guaranteed. This work presents a multi-layer mesh NoC approach to improve the QoS of such communication hungry SoCs. While one mesh layer is fixed in the system for control purposes, other data layers can be configured at runtime to provide the desired data throughput required by the application. This is accomplished by partially and dynamically reconfiguring the data layer routers. Arbitration algorithms, routing algorithms and huge crossbars are removed from the data layer routers, because all data routers in the path a configured accordingly before its utilization. A SoC following this idea was prototyped in a Virtex-4 FPGA and the Early Access Partial Flow was used to partially and dynamically reconfigure the NoC. We show that 120 (5!) different configurations are needed for each reconfigurable router with 5 bidirectional ports. Each configuration requires 33KB of memory and occupies 32 CLBs of area.

Behavioral patterns are useful abstractions to simplify the design of the communication-centric systems. Such patterns are traditionally described using UML diagrams, but the lack of execution semantics in UML prevents the co-validation of the patterns together with simulation models and executable specifications which are the mainstream in today's system level design flows. This paper proposes a method to validate UML-based behavioral patterns within executable system models. The method is based on actor orientation and was implemented as an extension of the Ptolemy II framework. A case study is presented and potential applications and extensions of the proposed method are discussed

Reconfigurable hardware is often used in an attempt to boost performance of an embedded system while minimizing the cost penalty of additional hardware. The key method applied to achieve this goal is the re-use of hardware resources for different tasks. However, reconfigurable systems tend to have a large internal state, which complicates rapid task switching, as it is required for multitasking in real-time systems, significantly. We present a control technique enabling a fast and efficient preemption of dynamically reconfigurable systems which is largely performed by hardware. The technique handles the problem of internal state preservation and reduces the preemption effort by applying the concept of preemption points. The implementation of the system control and an evaluation of the performance is given, showing the high efficiency of the concept.

A collaborative design system depends heavily on the chosen collaboration methodology, as well as on its technological infrastructure. This paper presents three data repository technologies and discusses their pros and cons on the role of supporting a collaborative design system.