Information and communication technologies (ICT) represent a fundamental element in the growth and performance of smart grids. A sophisticated, reliable and fast communication infrastructure is, in fact, necessary for the connection among the huge amount of distributed elements, such as generators, substations, energy storage systems and users, enabling a real time exchange of data and information necessary for the management of the system and for ensuring improvements in terms of efficiency, reliability, flexibility and investment return for all those involved in a smart grid: producers, operators and customers. This paper overviews the issues related to the smart grid architecture from the perspective of potential applications and the communications requirements needed for ensuring performance, flexible operation, reliability and economics.

Parallel prefix adders are used for efficient VLSI implementation of binary number additions. Ling architecture offers a faster carry computation stage compared to the conventional parallel prefix adders. Recently, Jackson and Talwar proposed a new method to factorize Ling adders, which helps to reduce the complexity as well as the delay of the adder further. This paper discusses the design and implementation details for such lower complexity, fast parallel prefix adders based on Ling theory of factorization. In particular, valency or radix, the number of inputs to a single node, is explored as a design parameter. Several low and high valency adders are implemented in 65 nm CMOS technology. Experimental results show that the high-valency Ling adders have superior area×delay characteristics over previously reported Ling-based or non-Ling adders for the same input size. Moreover, our 20-bit high valency adder has a better area×delay measurement than the previously-published 16-bit adders.

60 GHz wireless personal area networks (WPANs) offer multi-Gbps throughput, which will provide for a new wave of high data rate applications. This paper exploits the use of location information to improve the performance and enhance range of 60 GHz multi-user beamforming systems. When the location information is available at the transmitter, the scheduler chooses a set of maximum angularly separated users to share wireless resources simultaneously. If additional feedback of signal-to-interference and noise ratio (SINR) is known, a location-assisted scheduler is employed to increase the system overall performance. Both numerical and simulated results show that significant enhancement can be achieved by the proposed schedulers for 60 GHz WPAN systems.

The IEEE 802.11ad task group has published its first draft to cope with the characteristics in 60 GHz millimeter-wave (mmWave) wireless communications. In this paper, three different 2×2 multiple-input multiple-output (MIMO) techniques are considered to enhance the performance of 60 GHz wireless personal networks (WPANs). Packet Error Rate (PER) and link throughput performance are simulated under different channel conditions. In addition, the system throughput over operation range is presented in the paper. Results show that significant enhancements in both coverage and capacity can be achieved by employing space-time block codes (STBC), spatial multiplexing (SM) and three different configurations of beamforming.

Recently, the development and requirement for ultra-high data rate wireless communication applications has increased dramatically. The 60 GHz millimeter-wave wireless technology is getting increasing attention, and the IEEE 802.11 Task Group AD is making standardization efforts for multi-gigabit data rate communications on both the physical (PHY) and medium access control (MAC) layers. This paper presents a performance evaluation of the PHY and MAC layers of IEEE 802.1 lad. Packet error rate and PHY throughput are presented for different modes, and the theoretical MAC throughput is analyzed for different bit error rates, packet sizes and modes. In addition, 2×2 space-time block coding (STBC) is employed for range extension. The cross layer results show our approach enhance the throughput and coverage compared to the case of single antenna.

In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction in the code tree simultaneously. It is shown that the proposed BFA can achieve more than twice the decoding throughput compared to the conventional unidirectional Fano algorithm (UFA) and there is higher throughput improvement at low signal-to-noise ratio (SNR). This new BFA decoding technique is applied in the parallel convolutional decoding architecture in very high throughput systems, such as the WirelessHD system. Due to the variability in the decoding delays of the parallel codewords, a scheduler is introduced in the parallel Fano decoding architecture which can dynamically allocate the idle decoders to assist with decoding the other parallel codewords in a bidirectional manner. It is shown that the proposed parallel Fano decoding with scheduling can dramatically increase the decoding throughput compared to the parallel Fano decoding without scheduling, and its computational complexity is much lower than that of parallel Viterbi decoding, especially at high SNR. The performance of the parallel Fano decoding with different scheduling schemes is also compared and analyzed in detail in the paper.

For 100 years, there has been no change in the basic structure of the electrical power grid. Experiences have shown that the hierarchical, centrally controlled grid of the 20th Century is ill-suited to the needs of the 21st Century. To address the challenges of the existing power grid, the new concept of smart grid has emerged. The smart grid can be considered as a modern electric power grid infrastructure for enhanced efficiency and reliability through automated control, high-power converters, modern communications infrastructure, sensing and metering technologies, and modern energy management techniques based on the optimization of demand, energy and network availability, and so on. While current power systems are based on a solid information and communication infrastructure, the new smart grid needs a different and much more complex one, as its dimension is much larger. This paper addresses critical issues on smart grid technologies primarily in terms of information and communication technology (ICT) issues and opportunities. The main objective of this paper is to provide a contemporary look at the current state of the art in smart grid communications as well as to discuss the still-open research issues in this field. It is expected that this paper will provide a better understanding of the technologies, potential advantages and research challenges of the smart grid and provoke interest among the research community to further explore this promising research area.

This paper presents a method to protect memories against multiple bit upsets and to improve manufacturing yield. The proposed method, called a Matrix code, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and multiple bit-upsets. The method is evaluated using fault injection experiments. The results are compared to well-known techniques such as Reed-Muller and Hamming codes. The proposed technique performs better than the Hamming codes and achieves comparable performance with Reed-Muller codes with very favorable implementation gains such as 25% reduction in area and power consumption. It also achieves reliability increase by more than 50% in some cases. Further, the yield benefits provided by the proposed method, measured by the yield improvements per cost metric, is up to 300% better than the ones provided by Reed-Muller codes.

The bidirectional Fano algorithm (BFA) can achieve at least two times decoding throughput compared to the conventional unidirectional Fano algorithm (UFA). In this paper, bidirectional Fano decoding is examined from the queuing theory perspective. A Discrete Time Markov Chain (DTMC) is employed to model the BFA decoder with a finite input buffer. The relationship between the input data rate, the input buffer size and the clock speed of the BFA decoder is established. The DTMC based modelling can be used in designing a high throughput parallel BFA decoding system. It is shown that there is a trade-off between the number of BFA decoders and the input buffer size, and an optimal input buffer size can be chosen to minimize the hardware complexity for a target decoding throughput in designing a high throughput parallel BFA decoding system.

In this paper, we explore the feasibility of achieving gigabit baseband throughput using the vast computational power offered by the graphics processors (GPUs). One of the most computationally intensive functions commonly used in baseband communications, the Fast Fourier Transform (FFT) algorithm, is implemented on an NVIDIA GPU using their general-purpose computing platform called the Compute Unified Device Architecture (CUDA). The paper, first, investigates the implementation of an FFT algorithm using the GPU hardware and exploiting the computational capability available. It then outlines the limitations discovered and the methods used to overcome these challenges. Finally a new algorithm to compute FFT is proposed, which reduces interprocessor communication, and it is further optimized by improving memory access, enabling the processing rate to exceed 4 Gbps, achieving a processing time of a 512-point FFT in less than 200 ns.

Recently, we introduced a bidirectional Fano algorithm (BFA) [10] which can achieve much higher decoding throughput compared to the regular unidirectional Fano algorithm (UFA), especially at low signal-to-noise-ratio (SNR). However, the decoding throughput improvement of the conventional BFA with respect to the UFA reduces as the SNR increases and converges to 100% at high SNR. In this paper, two parameters in the BFA, which are known as the number of merged states (NMS) and the threshold increment value Δ, are exploited to improve the decoding throughout of the conventional BFA. The improved BFA can achieve much higher decoding throughput compared to the UFA and the conventional BFA, especially at high SNR. For example at Eb/N0=5dB, the throughput improvement achieved by the improved BFA is about 280% compared to the UFA and about 80% compared to the conventional BFA, and its computational complexity is only 4% of the Viterbi algorithm.

Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure. However, for very high throughput systems operating in the multi-Gb/s range conventional decoding methods based on message passing are limited, due largely to the sheer volume of messages being exchanged. Thus, simpler decoding methods have been proposed such as bit flipping permitting efficient and fast hardware implementation. This paper presents two new bit flipping algorithm designed to reduce latency and power consumption. For a small loss in bit error rate performance (0.5 dB) we show how the application of an early stopping criteria uses 89% fewer iterations compared to a similar published algorithm. We also present a method for reducing power consumption by placing processing elements into a quiescent state based on a bit-local metric. Using this technique we show a potential reduction in power consumption of 76%.

Journal Article Two Decades of Random Neural Networks Get access Taskin Koçak Taskin Koçak * Department of Electrical and Electronic Engineering, University of Bristol, Bristol, BS8 1UB, United Kingdom *Corresponding author: [email protected] Search for other works by this author on: Oxford Academic Google Scholar The Computer Journal, Volume 53, Issue 3, March 2010, Pages 249–250, https://doi.org/10.1093/comjnl/bxp063 Published: 10 July 2009

No abstract available.

Layered decoding of Low Density Parity Check (LDPC) codes has been shown to give faster convergence and use less storage than the conventional Two Phase Message Passing (TPMP) algorithm in decoding such codes. To achieve higher throughput, multiple rows of the parity check matrix may be decoded in parallel, as in the Parallel-Turbo Decoding Message Passing (P-TDMP) algorithm. However, contention for globally shared memory permits only a subset of rows to be decoded in parallel thus limiting overall throughput. This paper uses a near optimal scheduling algorithm, based on graph colouring, to overcome memory contention, allowing processing of multiple rows without code modification, resulting in significant throughput gains over the standard P-TDMP algorithm. For the LDPC codes studied, throughput gains compared to the P-TDMP algorithm, of between ten and fifteen are shown to be possible.

Various techniques, such as bidirectional search, have been employed in sequential decoding to reduce the decoding delay. In this paper, a bidirectional Fano algorithm (BFA) is proposed, in which a forward decoder (FD) and a backward decoder (BD) search in the opposite direction simultaneously. It is shown that the proposed BFA can reduce the average decoding delay by at least 50% compared to the unidirectional Fano algorithm (UFA). Due to the reduction in the variability of the computational effort by using bidirectional search, there is even higher decoding throughput improvement at low signal-to-noise-ratio (SNR). For example at Eb/No=3dB, there is 300% throughput improvement by using the BFA decoding compared to the conventional UFA decoding. The proposed BFA decoding technique can be employed in very high throughput wireless communication systems with low hardware complexity and power consumption.

This paper proposes a new clustering algorithm for global positioning system (GPS)-based mobile ad hoc networks that takes into consideration the direction of the overall traffic flow in the network. The proposed cluster leader logic algorithm is motivated by the GPS quorum hybrid routing algorithm, where clusterheads are positioned on the terrain upon a conceptual cellular grid. The proposed distributed clustering algorithm chooses the clusterheads based on the traffic flow patterns, i.e. the nodes best suited to forward and route network traffic are selected. Our approach allows a clusterhead which is overwhelmed with sending packets to identify an additional clusterhead from nodes available in its cell to share its load. Likewise, clusterheads with low load will try to relinquish their role as a clusterhead. We propose a new concept called cell fanning that allows collocated clusterheads in one cell to share routing responsibilities by declaring which cells they are responsible for routing packets to. We conducted extensive simulation experiments with enforced directional traffic patterns. Two important results are presented: power consumption per clusterhead and average queuing delay for each clusterhead. Results in terms of message overheads, number of clusterheads, power consumption, and queuing delay reveal that system performance is enhanced when clusterheads are chosen considering the direction of the traffic flow.

The bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This paper proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA.

Department of Computing, Imperial College London, London, UK. Email: [email protected] A resurgence in product-forms Interest in the stochastic behaviour of queueing networks began in the 1960s with the work by Jackson, Gordon, Newell and others [1–3]. These authors derived the so-called product-form solutions for the equilibrium probabilities of the joint state in such a continuous time Markov chain (CTMC). From the preceding lecture, of course, these networks are special cases of G-networks, where there are no negative customers, triggers, signals, etc. After a number of generalizations of Jackson networks in the 1970s and 1980s, it was thought by many that a product-form for a stochastic network would only exist if that network satisfied a condition called partial or local balance [4, 5]. Essentially, this specifies a specific way by which the global balance equations of probability fluxes into, and out of, a given state (the steady-state theorem for CTMCs) are constructed from balanced subsets of these equations, each subset relating to a component of the network. Gelenbe's G-network model [6–14], and the related RNN model [15], with its non-linear traffic equations in particular, provided counter-examples to this widely held view. In turn, this sparked a resurgence of interest in the quest for product-forms, which continues today.

As internet protocol (IP) networks in the enterprise space continue to mature, with regards to stability and availability, the desire for these networks to deliver multimedia content will grow. Although IP networks have long had enough bandwidth to support multimedia streams, the deployment of this content seems to have been somewhat limited in the enterprise. The control mechanisms for multicast traffic, both at the IP layer and the data link layer, are still the areas that have not been adopted as widely as their more common unicast counterparts. The authors examine the internet group messaging protocol (IGMP) snooping process that currently runs on enterprise switches and propose an offload hardware engine to accelerate it. Currently, many enterprise switches handle this task with a general-purpose processor within the switch. Although this process adds very little to the overall load of systems currently, as multicast transmissions become more commonplace, the need for this process to be offloaded onto specialised hardware will be a necessity, in order to maintain the stability of the switch and the surrounding network. The proposed hardware model simulations reveal significant increase in the number of packets per second that can be handled compared to software implementations.

Blacklists (BLs), also called Domain Name System-based Blackhole List (DNSBLs) are the databases of known internet addresses used by the spammers to send out the spam mails. Mail servers use these lists to filter out the e-mails coming from different spam sources. In contrary, Whitelists (WLs) are the explicit list of senders from whom e-mail can be accepted or delivered. Mail Transport Agent (MTA) is usually configured to reject, challenge or flag the messages which have been sent from the sources listed on one or more DNSBLs and to allow the messages from the sources listed on the WLs. In this paper, we are demonstrating how the bandwidth (the overall requests and responses that need to go over the network) performance is improved by using local caches for BLs and WLs. The actual sender's IP addresses are extracted from the e-mail log. These are then compared with the list in the local caches to find out if they should be accepted or not, before they are checked against the global DNSBLs by running 'DNSBL queries' (if required). Around three quarters of the e-mail sources have been observed to be filtered locally through caches with this method. Provision of local control over the lists and lower search (filtering) time are the other related benefits. Keywords ­ DNSBL, Blacklist, Whitelist, Spam, Cache

Software-based detection techniques are commonly used to identify the predefined signatures in network streams. However, the software-based techniques can not keep up with the speeds that network bandwidth increases. Hence, hardware-based systems have started to emerge. Bloom filters are frequently used to identify malicious content like viruses in high speed networks. However, architectures proposed to implement Bloom filters are not power efficient. We propose a new Bloom filter architecture that exploits the well-known pipelining technique. Through extensive power analysis we show that pipelining can reduce the power consumption of Bloom filters up to 90 %, which leads to the energy-efficient implementation of network intrusion detection systems.

Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processor-memory environments, to create data transfer bottlenecks and hot-spots. Solutions to the memory bandwidth bottleneck are limited by the area available on the line card and network processor I/O pins. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that replace the existing systems and that provide extraordinary high throughput. We utilize our custom-designed, event-driven, interconnect simulator to evaluate the performance of wormhole routed packet-based off-chip k-ary n-cube interconnect architectures for line cards. Our performance results show that wormhole routed k-ary n-cube based interconnect topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads

Although software based techniques are widely accepted in computer security systems, there is a growing interest to utilize hardware opportunities in order to compensate for the network bandwidth increases. Recently, hardware based virus protection systems have started to emerge. This type of hardware systems work by identifying the malicious content and removing it from the network streams. In principle, they make use of string matching. Bit by bit, they compare the virus signatures with the bit strings in the network. The bloom filters are ideal data structures for string matching. Nonetheless, they consume large power when many of them used in parallel to match different virus signatures. In this paper, we propose a new type of Bloom filter architecture which exploits well-known pipelining technique

The trend in network processing is towards layer 4-7 processing in the routers and switches. In this paper, we present a hybrid network processor (NPU) architecture that supports high-speed execution of higher layer TCP/IP protocol processing. The architecture achieves this by employing optimized logic blocks for specific tasks in the processing elements. This is a unique architecture such that it can realize both task-level and packet-level parallelism. We also present an example of implementation of a fast adaptive routing algorithm, Cognitive Packet Networks (CPNs), using the proposed NPU architecture. CPN uses a neural network model with a reinforcement learning algorithm to find routes. The applicability of the CPN concept has been demonstrated through several software implementations. Through hardware implementation, we show that this new network model can sustain similar line rates as the current IP protocols.

Random neural network (RNN) is an analytically tractable spiked neural network model that has been implemented in software for a wide range of applications for over a decade. This paper presents the hardware implementation of the RNN model. Recently, cognitive packet networks (CPN) is proposed as an alternative packet network architecture where there is no routing table, instead the RNN based reinforcement learning is used to route packets. Particularly, we describe implementation details for the RNN based routing engine of a CPN network processor chip: the smart packet processor (SPP). The SPP is a dual port device that stores, modifies, and interprets the defining characteristics of multiple RNN models. In addition to hardware design improvements over the software implementation such as the dual access memory, output calculation step, and reduced output calculation module, this paper introduces a major modification to the reinforcement learning algorithm used in the original CPN specification such that the number of weight terms are reduced from 2n/sup 2/ to 2n. This not only yields significant memory savings, but it also simplifies the calculations for the steady state probabilities (neuron outputs in RNN). Simulations have been conducted to confirm the proper functionality for the isolated SPP design as well as for the multiple SPP's in a networked environment.

Cascade, single and multi-bit, /spl Sigma//spl Delta/ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded /spl Sigma//spl Delta/ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded /spl Sigma//spl Delta/ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized.