The growing interest in affective computing has resulted in substantial advancements in emotion recognition through the application of various machine learning and deep learning techniques. Nevertheless, existing methodologies exhibit notable limitations. Specifically, they often fail to address extreme-edge design requirements, making them unfeasible for deployment in wearable systems under real-world conditions. With this aim, this paper introduces a novel end-to-end fear recognition system based on physiological signals designed specifically for deployment in extreme-edge contexts. This solution combines advanced feature engineering techniques with optimized lightweight 1D-CNN model architecture that integrates the advantages of both hand-crafted features and advanced deep-learning convolutional techniques. An experimental validation conducted with the WEMAC dataset provides f1-scores of 80% and accuracy rates of 74%, and reveals significant performance improvements with respect to our previous model proposed: 11.6% and 26.4% in accuracy and F1-score metrics, respectively. Additionally, this research demonstrates the successful integration and validation of the model within an ultra-low-power ARM Cortex™-M4 architecture, which exhibits an average power consumption of 16 mW at 5 V, with each inference requiring 496 ms. These results pave the way to a sustainable implementation of deep learning solutions in extreme-edge devices.

Designing AI-based applications personalized to each user's behavior presents significant challenges due to the cold start problem and the impracticality of extensive individual data labeling. These challenges are further compounded when deploying such applications at the edge, where limited computing resources constrain the design space. This paper introduces a novel approach to AI-driven personalized solutions in biosensing applications by combining deep learning with clustering-based separation techniques. The proposed Clustering and Learning for Emotion Adaptive Recognition (CLEAR) methodology strikes a balance between population-wide models and fully personalized systems by leveraging data-driven clustering. CLEAR demonstrates its effectiveness in emotion recognition tasks, and its integration with fine-tuning enables efficient deployment on edge devices, ensuring data privacy and real-time detection when new users are introduced to the system. We conducted experiments for model personalization on two edge computing platforms: the Coral Edge TPU Dev Board and the Raspberry Pi with an Intel Movidius Neural Compute Stick 2. The results show that initial cluster assignment for new users can be achieved without labeled data, directly addressing the cold-start problem. Compared to baseline validation without clustering, this proposal improves accuracy metric from 75% to 81.9%. Furthermore, fine-tuning with minimal labeled data significantly improves accuracy, achieving up to 86.34% for the fear detection task in the WEMAC dataset while remaining suitable for deployment on resource-constrained edge devices.

Wearable technology is having a profound impact in healthcare applications. In this context, one of the main goals of current wearable systems is to provide new devices capable of delivering a greater amount of more precise information. Amongst the different applications, physiological continuous monitoring is becoming one of the most wanted features. In fact, most of the commercially and research grade wearable systems include cardiac activity acquisition, which is generally performed by means of photoplethysmography sensors (PPG). These optical-based sensors present different challenges related to the prevailing of a good signal quality. Thus, in case of dealing with digital processing algorithms which are responsible for extracting different features from such signal, this fact can lead to erroneous results. On this basis, this paper presents an ongoing work towards the design of an interval type-II fuzzy-based system for the PPG signal quality assessment. Moreover, this initial proposed system is implemented into a constrained 32-bit ARM Cortex-M4 system-on-chip. Specifically, the system uses a reduced set of features together with a low complexity fuzzy rule base Mamdani inference model, and is based on a non-overlapping 3-second signal processing window. Results show that the system achieved overall accuracy of 94.84%. The proposed system has great potential for integrating accurate and reliable continuous health monitoring systems into constrained edge devices.

The main research motivation of this article is the fight against gender-based violence and achieving gender equality from a technological perspective. The solution proposed in this work goes beyond currently existing panic buttons, needing to be manually operated by the victims under difficult circumstances. Instead, Bindi, our end-to-end autonomous multimodal system, relies on artificial intelligence methods to automatically identify violent situations, based on detecting fear-related emotions, and trigger a protection protocol, if necessary. To this end, Bindi integrates modern state-of-the-art technologies, such as the Internet of Bodies, affective computing, and cyber–physical systems, leveraging: 1) affective Internet of Things (IoT) with auditory and physiological commercial off-the-shelf smart sensors embedded in wearable devices; 2) hierarchical multisensorial information fusion; and 3) the edge-fog-cloud IoT architecture. This solution is evaluated using our own data set named WEMAC, a very recently collected and freely available collection of data comprising the auditory and physiological responses of 47 women to several emotions elicited by using a virtual reality environment. On this basis, this work provides an analysis of multimodal late fusion strategies to combine the physiological and speech data processing pipelines to identify the best intelligence engine strategy for Bindi. In particular, the best data fusion strategy reports an overall fear classification accuracy of 63.61% for a subject-independent approach. Both a power consumption study and an audio data processing pipeline to detect violent acoustic events complement this analysis. This research is intended as an initial multimodal baseline that facilitates further work with real-life elicited fear in women.

Wireless Sensor Networks are nowadays employed in several applications. Cyber-physical systems, health-care instruments and Internet of Things are using hundreds of smart sensors, which include also processing capability together with sophisticated communication protocols. The presence of faults in these critical applications must be checked during runtime, to detect transient and permanent faults that could seriously affect the entire system dependability and endanger human users. Continuous checking has been proven as inefficient in many cases, due to the low degrees of observability and controllability and to the limited life time of batteries. Even, on-line testing is often unable to report the presence of internal errors, which can remain latent during long times. In this paper, a proposal is presented for improving the on-line testability of the different type of nodes in a WSN, saving energy and tracking error from their origin.

Traditionally, heavy ion radiation effects affecting digital systems working in safety critical application systems has been of huge interest. Nowadays, due to the shrinking technology process, Integrated Circuits became sensitive also to other kinds of radiation particles such as neutron that can exist at the earth surface and affects ground-level safety critical applications such as automotive or medical systems. The process of analyzing and hardening digital devices against soft errors implies rising the final cost due to time expensive fault injection campaigns and radiation tests, as well as reducing system performance due to the insertion of redundancy-based mitigation solutions. The main industrial problem arising is the localization of the critical elements in the circuit in order to apply optimal mitigation techniques. The proposal of this tutorial is to present and discuss different solutions currently available for assessing and implementing the fault tolerance of digital circuits, not only when the unique design description is provided but also at the component level, especially when Commercial-of-the-shelf (COTS) devices are selected.

True-random number generators (TRNGs) are being recently defined, designed and prototyped on digital electronic circuits, like part of encryption and decryption algorithms. They provide very interesting results in terms of security and cost. In harsh environments, like aerospace applications, Single Event Upsets (SEUs) are a main concern. TRNGs are currently used in satellite communications to enhance security by ciphering critical data. This work studies the effects of SEUs on a particular architecture of TRNGs. The analysis is performed by injecting fault models in a physical TRNG implementation.

The current state-of-the-art radiation tolerant or hardened reconfigurable SRAM-based FGPAs offer qualification for space applications, dynamic partial reconfiguration for in-flight adaptability, high density and performance. These FPGAs are very suitable for implementation of digital signal processing algorithms, providing the possibility for orders of magnitude increases in performance over processor-based implementations and thus are well suitable to establish dependable reconfigurable space systems. Alternatively, reconfigurable Complex Programmable Logic Devices (CPLDs) can be used as low-cost, low-power solutions for non-critical space applications. In this paper, challenges and new trends for dependable reconfigurable space systems are discussed and illustrated with 3 case studies.

Permanent faults (e.g., due to electronic components aging) represent a real problem in nowadays digital systems working in automotive vehicles. Mandatory tests should be done at the vehicle key-on in order to detect damaged elements. Generation and validation of these tests can be improved in a great manner considering the characteristics of the target distributed subsystems. In this work, an approach for in-field detection of permanent faults in a LIN network is proposed.

Robust communications protocols are widely used in safety critical applications, such as aerospace or automotive systems. On-board complex systems, working in harsh environments, are composed of distributed modules with a high degree of interaction and critical tasks replication. Single Event Upsets (SEUs) are very probable to affect these modules and their communications. Robust protocols are usually designed to correct communication data errors, usually due to problems in the physical medium (e.g. noise). They provide robustness in data transmission but fault tolerance is not ensured in the interface control logic. In this work, a study of the SEU sensitivity of a typical robust communication protocol, the CAN bus, is performed. Authors have applied an extensive fault injection campaign in the internal modules of the circuit that implements this standard in order to perform a depth analysis. Experimental results prove robustness is not complete in the control part of this protocol. Selective hardening will enhance this robustness with low extra cost in terms of area or performance.

Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic circuits driven by testability estimations. Using the concept of unate functions, approximations are performed in lines with low testability in order to minimize the impact on error coverage. The proposed approach is scalable and can provide a variety of solutions for different trade-offs between error coverage and overheads.

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

The process of designing robust digital systems is getting heavier and longer due to the increase of functional complexity and circuit sensitiveness [1][2]. Furthermore, aerospace and automotive electronics are including more digital systems with critical tasks distribution among several single and cheaper modules. Although collaborative hardening is providing very interesting results in terms of cost and reliability, the design process becomes more difficult. Redundant tasks, hardware and software, must be evaluated together with the global and local error mitigation techniques. Also, network links affect error propagation and mitigation. Finally, the error accumulation must be considered in these systems working in harsh conditions. In this paper we present a general method for evaluating the Single Bit Upsets (SBU) sensitivity of complex digital systems with critical tasks distribution and collaborative hardening. This method performs a detailed analysis of signal integrity along system operation thanks to hardware emulation in the early steps of the design cycle.

Pseudorandom number generators (PRNGs) are used frequently in secure data processing algorithms. Randomness measuring is an essential test, performed on these generators, that help to range the security of the designed algorithm with respect to assure strong messing-up of the processed data. This paper describes a solution for accelerating statistical tests of Diehard Battery based on reconfigurable hardware, benefiting from task parallelization and high frequencies. With this proposal, users can obtain a fast, cheap and reliable measure of the randomness properties that can enable a complete exploration of the design space to produce better devices in shorter times.

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

An increasing number of applications require being able to detect possible faults arising during the normal activity of the electronic system: for this reason, on-line fault detection is a hot topic today. This paper proposes a new technique which is suitable for microprocessor-based systems (no matter whether they are implemented in a single device or with discrete COTS) that exploit hardware duplication and combines it with the On-Chip Debug features existing in many processors. The new technique increases the observability of faults (thus increasing detection probability and reducing latency) and is characterized by a very reduced intrusiveness in terms of changes required in the application code.

A new solution is presented for fast measuring of randomness properties of cryptographic algorithms. Statistical Tests from NIST are hardware implemented in order to enable an on-line detection of intentional attacks in cryptographic ciphers. The small area overhead and the short processing times provide a good solution for hardening this type of circuits.

SEU effects are a main concern in an increasing number of applications. Selective hardening in early design stages is intended to design a robust circuit in a fast and cost-efficient way. In this paper, a method to performing selective hardening in digital circuits against SEUs is described. This method is based on the autonomous emulation fault injection technique. It allows the designer to identify the critical parts of the circuit and use different hardening techniques to reach a trade-off between the obtained robustness and area and performance penalties. A PIC microcontroller has been analysed in detailed against SEU effects as case study, injecting millions of faults. Results points out that hardening just 17% of the circuit flip-flops reduces the failure rate induced by SEUs in 99%.

Latest mitigation techniques proposed at register-transfer level for dependable cryptosystems deal with time redundancy in an active on-line error-detection scheme. Round-based block ciphers are very likely to be hardened with these techniques. Although good results are achieved in terms of area or time overhead, intentional attacks are still able to obtain crucial information by means of intensive fault injection campaigns. In this paper, a new solution is presented and analyzed, dealing with pseudo-random number generators (PRNG) with the goal of misleading attackers and, therefore, making cryptosystem more robust. With this approach, attackers must face two difficulties: dealing with on-line error detection and ignoring the fault location in the round sequence. PRNG will produce different repetition sequences for the rounds of the cryptosystem, making very difficult to correlate output data with injected faults.

We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.

Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness together with a small penalty in the algorithm throughput when dealing with specific intentional attacks. Experimental results on Advanced Encryption Standard are presented and discussed.

Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). It can be widely applicable to different processors since JTAG standard is an extended interface and OCDs are usually available in current processors. The hardware implementation avoids the communication between the target system and the software debugging tool. The method has been applied to a complex processor, the ARM7TDMI. Results illustrate the approach is a fast, efficient and cost-effective solution.

Systems-on-programmable-chip (SoPCs) include processors, memories and programmable logic that allow to catch multiple application requirements such as high performance, reconfigurability and low-costs. Due to these characteristics, they are also becoming very attractive for safety-critical applications. However, the issue of assessing the reliability they can provide and debugging the possible safety-related mechanisms they embed is still open. In this paper, we present a new fault-injection approach for evaluating the impact of transient faults in SoPCs. Fault-injection experiments are reported on a case study consisting of a Web server implemented on a Xilinx Virtex-II FPGA embedding a PowerPC 405 and running the whole TCP/IP stack

FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed autonomous emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the autonomous emulation techniques to circuits with embedded memories is presented. The LEON2 processor benchmark is used to demonstrate as an application for the proposed techniques

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitivity to radiation. So errors are currently appearing in ICs working at the Earth's surface. Hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the FT evaluation. In this work, a new emulation system for FT evaluation with respect to SEU effects is proposed, providing shorter evaluation times by performing all the evaluation process in the FPGA and avoiding emulator-host communication bottlenecks.

Platform FPGAs provide a high degree of reconfigurability and a high density of integration. These features make these devices very suitable for hardware emulation and in particular for fault tolerance evaluation. There are several FPGA-based approaches that enhance notably the fault tolerance evaluation process achieving an important speed up. However, such methods are limited by the communication between the FPGA and the host computer, which manages the emulation process. In order to minimize this communication and therefore accelerate the overall process, an autonomous emulation system is proposed in this paper. This solution profits from additional hardware resources available in current platform FPGAs such as embedded RAM. In the proposed system, a complete emulation campaign and its management is embedded in the FPGA, accelerating emulation process up to two orders of magnitude without losing flexibility with respect to other hardware solutions.

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Therefore, hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of CAD tools, for the generation and the validation of fault tolerant circuits, will allow designers to obtain hardened devices in a cost-effective way with short development times and with high reliability results. While automatic insertion of fault tolerant structures in designs is already possible, automatic evaluation with an optimum time-cost relation is still needed. In this sense, the use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the fault tolerance evaluation. In this work, a new emulation system for the evaluation of FT with respect to SEU effects is proposed. This solution gets profit of hardware resources for accelerating the FT evaluation. It is analysed and compared with respect to other emulation techniques. The proposed solution provides not only short times but also low cost in area for FT validation, giving better results than pure software or hardware solutions.

Fault-tolerant circuits are currently required in several major application sectors, and a new generation of CAD tools is required to automate the insertion and validation of fault-tolerant mechanisms. This paper outlines the characteristics of a new fault-injection platform and its evaluation in a real industrial environment. The fault-injection platform is mainly used for assessing the correctness and effectiveness of the fault tolerance mechanisms implemented within ASIC and FPGA designs. The platform works on register transfer-level VHDL descriptions which are then synthesized, and is based on commercial tools for VHDL parsing and simulation. It also details techniques devised and implemented within the platform to speed-up fault-injection campaigns. Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.

When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising a sample safety-critical device. Designers were permitted to assess the effects of transient faults, automatically add fault-tolerant structures, and validate the results working on the same circuit descriptions and acting in a coherent framework. The evaluation showed the effectiveness of the proposed environment.