Thermal issues of 3D-ICs have become increasingly severe in recent years. Thus, thermal simulation is needed to ensure thermal safety during the design stage. However, performing thermal simulation iteratively requires a significant amount of time. As a result, a fast and accurate method for thermal prediction is a promising alternative to improve the turnaround time. In this paper, we propose a fast thermal prediction method using machine learning models. In the training phase, we employ two models: one for the initial three time steps and another for the subsequent time steps. To enhance prediction accuracy, we introduce two types of features: spaced-windowed features and time-decayed features. These features help us to capture spatial and temporal information effectively. In our experiment, the mean absolute error for the predicted temperature is 1.12°C, and the maximum error is 7.27 °C. In the prediction phase, we achieve a 116X speed-up compared to a commercial tool. With our proposed method, users can predict transient thermal profiles quickly and accurately to ensure thermal safety.

Randomized benchmarking (RB) is widely used in the calibration process of quantum computers with the main focus on average gate fidelity. This work proposes a version with the ability of detecting user-specified faults, and successfully detected faults in simulations and real IBM quantum processors. Our proposal can evaluate error per gate (EPG) and detect faults at the same time. We have shown our FDRB successfully detect axial-tilt fault and rotation fault in both simulation and real experiments. The overhead of our proposal is the quantum native gate count increase depending on the number of faults specified by the user.

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.

At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vminpose a risk of over-testing and production yield loss. This is particularly problematic if the Vminof the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmindebug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vminby preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vminby 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.

We propose a complete flow of multi-core minimum operating voltage (Vmin) prediction method using a nondestructive stress test. We process stress-test fail-logs and generate features to predict Vmin. In addition, we select important features by Pearson correlation and F-regression. Then, select specified test patterns that correlate to each core’s Vminby genetic algorithms to reduce stress test time. Experimental results on advanced 4nm multi-core CPU designs show that the best average RMSE of our predicted Vmincan be as low as 8.30 mV. Also, we have achieved over 66% test pattern reduction rate.

As the complexity of integrated circuits advances, wafer sort faces the difficulty of balancing test time, test quality, and the preservation of diagnostic information. On the one hand, we need a high-quality wafer sort that detects defective chips at the early test stage. On the other hand, high-quality wafer sort can be time-consuming. In addition, diagnostic information from defective dies-under-test (DUTs) is crucial to improve the yield. In response, we propose a machine learning (ML)–based adaptive wafer sort for DUT testing. By skipping some test suites, the adaptive method can save test time while retaining high quality and preserving diagnostic information. Given the competitive trade-off between test time and test quality, the adaptive wafer sort improves bin swap and failure information loss by 7.8× and 338× compared to the traditional test time reduction method applying a fixed set of test suites

Neuromorphic chips are promising hardware implementations for artificial intelligence (AI) applications owing to their low power consumption. However, neuromorphic chips are difficult to test since they have many potential configurations but lack design for testability (DfT). We propose an algorithmic test generation method for neuromorphic chips without DfT, including fault activation and fault propagation. Fault activation differentiates a neuron's good output and faulty output. Fault propagation sensitizes fault effects to differentiate outputs of faulty chips and good chips. On an L-layer Spiking Neural Network (SNN) model, we achieve 100% fault coverage using O(L) test configurations and test patterns under negligible or no weight variation. Our results show that test effectiveness is maintained even with 4-bit weight quantization. We incur no test escape and overkill even under 10% weight variation. Our total test length is over 73K times shorter than previous works.

We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications.

Thermal issues during testing of Very Large Scale Integration (VLSI) chips have become more severe as design complexity increases. Test frequency optimization is needed because high test frequencies can cause thermal damage to circuits under test (CUT), while low test frequencies can result in long test time. In this paper, we propose three techniques to minimize the test time of ATPG scan tests without peak temperature violation. First, we propose a single test frequency optimization using machine learning predicted power maps. Second, we partition a test schedule into subschedules and perform multiple test frequency optimization for each subschedule to further reduce test time. Third, we show that we can partition a test schedule by our proposed Power Gap to obtain an even shorter test time. Our experimental results show that the total test time at our optimized multiple test frequencies is 45.91% shorter than the total test time at the original single test frequency.

Errors caused by faults would strongly affect the correctness of noisy intermediate-scale quantum (NISQ) circuits. In this work, we propose a technique for diagnosing coherent and incoherent faults for NISQ circuits. The proposed technique contains three phases: rough diagnosis, fine diagnosis, and depolarizing diagnosis. Rough diagnosis grid searches the Bloch sphere to locate an approximate range of a coherent fault. Fine diagnosis then precisely locates the coherent fault size based on the narrowed-down search space. At last, depolarizing diagnosis measures the depolarizing fault size. We demonstrate our technique using the Qiskit simulator with noise-free and noisy backends. The diagnosis accuracy between the diagnosed faulty gates and the injected faulty gates is over 99.95%, which is better than traditional quantum process tomography under the same conditions. Our results show that the diagnosis error of coherent faults does not affect the diagnosis accuracy of depolarizing faults. Experiments on the IBM Q devices have also been performed, and results of over 99.83% diagnosis accuracy show that our technique still preserves good resolution on real quantum circuit devices.

Probabilistic error cancellation (PEC) is a promising error mitigation technique that reduces the error rate without auxiliary quantum bits. However, PEC has two problems that need to be resolved: 1) there is no good PEC technique for parameterized gates and 2) sampling overhead (SO) grows exponentially with the number of PEC mitigated gates. We first propose a parameterized gate PEC (PGPEC) that mitigates the error without fully characterizing the gates, as the original PEC requires. The result shows that the number of gates requiring characterization for a thousand random circuits can be reduced by 97% or more. We next propose two novel approaches to solving the second problem. We propose a macro gate PEC (MGPEC) technique that aggregates multiple gates as a single macro gate to reduce the exponent of the SO. MGPEC reduces the SO by 49% on the QFT7 under the IBMQ noise model, which simulates real operation conditions of quantum circuits. We propose a design diversity PEC (DDPEC) technique to reduce the exponential basis of the SO. The results show that our DDPEC with design diversity check reduces overall SO by 13% on the QFT7 circuit under the IBM Q noise model. Combining the DDPEC with the MGPEC, we can reduce overall SO by 73%.

Delay faults have become increasingly important in modern designs due to decreasing technology node size and increasing operation frequency. However, diagnosis of delay faults can be challenging since there are typically few failing bits in the test failures. In this work, a two-phase flow is presented to identify systematic delay failures and improve their corresponding diagnosis resolution. First, the subset relationships among test failures are analyzed to identify systematic defects. Then, representative test failures in the subset relationships are selected to diagnose the defect behavior. Experiments on two cores of an industrial design with three cases show over 33×, 69×, and 8× improvement on delay fault diagnosis resolution. Furthermore, the proposed technique can be easily integrated with commercial tools.

High test power causes thermal damage to chips under test. We need power and thermal analyses to ensure thermal safety of ATPG patterns. This requires long runtime and large disk storage because there are many cycles in ATPG patterns. In this paper, we propose power and thermal predictions for test applications. To save runtime, we use multiple ML models and decay surface models for power and thermal predictions, respectively. To save storage, we build features from flip-flop values, so we don't need internal logic values from gate-level simulation. Our mean absolute percentage error (MAPE) for power prediction is less than 8%. Our mean absolute error (MAE) for thermal prediction is less than 1.2°C. We enable transient thermal analysis of long ATPG patterns, with 75X runtime speedup and 118X storage reduction. Our predictions are scalable with test speed, so they can be used to optimize test time while ensuring thermal safety.

Currently, noisy intermediate-scale quantum (NISQ) circuits may not always generate correct outputs due to noise and faults. In this work, we propose a diagnosis technique for NISQ circuits. The proposed technique contains static diagnosis and dynamic diagnosis. Static diagnosis uses a fault dictionary that contains output probability distribution for each fault. Dynamic diagnosis uses binary search to find the accurate fault locations of faulty quantum circuits. We demonstrate our technique using the Qiskit simulator with realistic noise models. We evaluate 15 benchmarks with unitary and non-unitary faults injected. Simulation results show that the average accuracy and resolution are 97.70% and 1.81. Experiments on the IBM Q devices have also been performed, and results show that our technique is feasible on real quantum circuit devices.

Vector-based dynamic IR-drop analysis of the entire vector set is infeasible due to long runtime. In this paper, we use machine learning to perform vector-based IR drop prediction for all logic cells in the circuit. We extract important features, such as toggle counts and arrival time, directly from the logic simulation waveform so that we can perform vector-based IR-drop prediction quickly. We also propose a feature engineering method, density map, to increase correlation by 0.1. Our method is scalable because the feature dimension is fixed (72), independent of design size and cell library. Our experiments show that the mean absolute error of the predictor is less than 3% of the nominal supply voltage. We achieve more than 495 speedups compared to a popular commercial tool. Our machine learning prediction can be used to identify IR-drop risky vectors from the entire test vector set, which is infeasible using traditional IR-drop analysis.

The demand for low-power, high-performance neuromorphic chips is increasing. However, conventional testing is not applicable to neuromorphic chips due to three reasons: (1) lack of scan DfT, (2) stochastic characteristic, and (3) configurable functionality. In this paper, we present an automatic test configuration and pattern generation (ATCPG) method for testing a configurable stochastic neuromorphic chip without using scan DfT. We use machine learning to generate test configurations. Then, we apply a modified fast gradient sign method to generate test patterns. Finally, we determine test repetitions with statistical power of test. We conduct experiments on one of the neuromorphic architectures, spiking neural network, to evaluate the effectiveness of our ATCPG. The experimental results show that our ATCPG can achieve 100% fault coverage for the five fault models we use. For testing a 3-layer model at 0.05 significant level, we produce 5 test configurations and 67 test patterns. The average test repetitions of neuron faults and synapse faults are 2,124 and 4,557, respectively. Besides, our simulation results show that the overkill matched our significance level perfectly.

Scan chain diagnosis plays a key role in ramping up production yield. However, this is challenged by high test compression ratios of modern designs, increasing the probability of multiple faulty chains feeding the same compressor. In our analyzed silicon data, we observe that 8.76% of scan chain failures have such two faulty chains. We propose a technique to help address this problem, separating the superposition of chain fault effects to diagnose these chips. This technique first uses jump simulation to identify and classify failures that are attributable to only one of the faulty chains. It then uses commercial tools to diagnose the classified failures of each chain individually. Experiments are conducted on both simulated and silicon test data to show the efficacy of our technique, and the proposed method showed improvements over standard diagnosis with commercial tools in resolution (2.38 candidates) and accuracy (92.0%). This method was also applied on industrial chips with potentially systematic double faulty chain failures.

A two-phase chip performance prediction flow is presented to avoid severe costumer return, reduce power consumption, and mitigate yield loss. In phase I, we first predict the initial value of minimum operating voltage (Vmin). In phase II, we predict the bin for each chip in order to apply different guard bands. Experiments on 851 advanced 7nm mobile chips show that predicted Vminis larger than actual Vminfor all chips to avoid customer return. Also, power consumption is reduced by 2.69%. Yield loss is mitigated by up to 5.05% when our Vminrequirement is 1.20 scaled Vmin. To implement our flow, we only need to spend a little more runtime compared to the conventional flow. While the runtime of our flow is still short, we can save the long time of measuring Vminfor every chip.

The demand for neuromorphic chips has skyrocketed in recent years. Thus, efficient manufacturing testing becomes an issue. Conventional testing cannot be applied because some neuromorphic chips do not have scan chains. However, traditional functional testing for neuromorphic chips suffers from long test length and low fault coverage. In this work, we propose a machine learning-based test pattern generation technique with behavior fault models. We use the concept of adversarial attack to generate test patterns to improve the fault coverage of existing functional test patterns. The effectiveness of the proposed technique is demonstrated on two Spiking Neural Network models trained on MNIST. Compared to traditional functional testing, our proposed technique reduces test length by 566x to 8,824x and improves fault coverage by 8.1% to 86.3% on five fault models. Finally, we propose a methodology to solve the scalability issue for the synapse fault models, resulting in 25.7x run time reduction on test pattern generation for synapse faults.

Spiking neural network (SNN) is a very promising low-power neural network that can be implemented in asynchronous circuits. However, it is hard to test SNN chips since they are inherently probabilistic and fault tolerant. So far, there is no good fault model and test methodology suitable for SNN chips. In this paper, we propose seven behavior fault models for SNN based on the function of neurons and synapses. We also propose a test methodology, which considers the output response as a distribution rather than specific values. The experiment results on a MNIST dataset show that although SNN is fault tolerant, two fault models are still critical for SNN chips. Given the digit recognition application, the accuracy of chips that passed our test is 88.90%, which is indistinguishable from that of good chips, even in the effects of random seeds.

We propose a new methodology to predict minimum operating voltage (Vmin) for production chips. In addition, we propose two new key features to improve the prediction accuracy. Our proposed accumulative learning can reduce the impact of lot-to-lot variations. Experimental results on two 7nm industry designs (about 1.2M chips from 142 lots) show that we can achieve above 95% good prediction. Our methodology can save 75% test time compared with traditional testing. To implement this method, we will need to have a separate test flow for the initial training and accumulative training.

Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginalities, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques is demonstrated on two industrial designs in cutting-edge process nodes and verified by targeted analysis and testing. The number of suspects is reduced by 3.1x and 575.2x on average. The proposed techniques can be implemented using existing commercial diagnosis tools with runtime overheads below 1%.

Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.

Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2nx 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level.

Probabilistic circuits are a potential solution for low power designs which trade off correctness for power consumption. The behavior of probabilistic circuits are more complicated than deterministic circuits because the former produce different outputs given the same inputs. We need to apply test pattern many times to obtain output distribution of probabilistic circuits. In this paper, we apply multivariate hypothesis testing to reduce pattern repetition. We also reduce overkill by tomographic testing to determine pass or fail of CUT. Experimental results show that our proposed technique can reduce pattern repetition by 82% and reduce overkill by 99%.

This paper proposes an automatic flow to repair IR-drop violations by Engineering Change Order (ECO). Our ECO technique provides cell move and downsize solutions. We use machine learning to predict IR-drop so that we can prevent over-fixing. We use a commercial tool to predict timing so that this is a timing-aware ECO. With the above two predictions, we propose a novel multi-round bipartite matching to optimize the ECO resource utilization. Experimental results show that for a 5M gate real design, our proposed method repairs 2,504 (22%) violation cells out of the original 11,555 violation cells and repairs 36,272mV (37%) total excessive IR out of the original 98,674mV total excessive IR. We are able to perform ECO on seven thousand cells within 13 hours, so our ECO flow is practical and can be applied to large industrial designs.

Power supply noise induced IR drop can cause transition delay faults (TDF) clustered in a small region. However, traditional diagnosis technique cannot handle clustered multiple TDF very well. This paper proposes a diagnosis tool for clustered multiple TDF. Star tracing for TDF is applied to find possible suspects. To tolerate fault masking and fault reinforcement effects, we propose an approximate covering heuristic to find a group of suspects. During approximate covering, we extract important suspects which are likely to be true suspects. We assume many suspects physically cluster around true suspects so our technique prunes suspects based on this assumption. We use correlation coefficient to determine the optimal number of clusters (Optimal NC) so we can apply the K-means algorithm to group suspects. Finally, we prune the least possible cluster but keep important suspects. Simulation on benchmark circuits shows that average accuracy of our tool (0.80) is much better than that of a commercial tool (0.47). Average resolution of our tool (0.35) is also better than that of the commercial tool (0.23).

Researchers now use randomized benchmarking or quantum volume to test quantum circuits (QC) in the laboratory. However, these tests are long and their fault coverage is unclear. In this paper, we propose behavior fault models based on the function of quantum gates. These fault models are scalable because the number of faults is polynomial, not exponential, to the size of QC. We propose a novel test generation that uses gradient descent to generate test configuration with short length. We revise the chi-square statistical method to decide the number of test repetitions under the specified test escape and overkill. Experimental results on IBM Q systems show that our generated test configurations are effective, and our test lengths are 1,000X shorter than traditional test methods.

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.

As Engineering Change Order (ECO) has attracted substantial attention in modern VLSI design, the open net problem, which aims at constructing a shortest obstacle-avoiding path to reconnect the net shapes in an open net, becomes more critical in the ECO stage. This paper addresses a multi-layer obstacle-avoiding region-to-region Steiner minimal tree (SMT) construction problem that connects all net shapes by edges on a layer or vias between layers, and avoids running through any obstacle with a minimal total cost. Existing multi-layer obstacle-avoiding SMT algorithms consider pin-to-pin connections instead of region-to-region ones, which would limit the solution quality due to its lacking region information. In this paper, we present an efficient algorithm based on our new multi-layer obstacle-avoiding region-to-region spanning graph to solve the addressed problem, which guarantees to find an optimal solution for a net connecting two regions on a single layer. Experimental results show that our algorithm outperforms all the participating routers of the 2017 CAD Contest at ICCAD in both solution quality and runtime.

During design signoff, many iterations of Engineer Change Order (ECO) are needed to ensure IR drop of each cell instance meets the specified limit. It is a waste of resources because repeated dynamic IR drop simulations take a very long time on very similar designs. In this work, we train a machine learning model, based on data before ECO, and predict IR drop after ECO. To increase our prediction accuracy, we propose 17 timing-aware, power-aware, and physical-aware features. Our method is scalable because the feature dimension is fixed (937), independent of design size and cell library. Also, we propose to build regional models for cell instances near IR drop violations to improves both prediction accuracy and training time. Our experiments show that our prediction correlation coefficient is 0.97 and average error is 3.0mV on a 5-million-cell industry design. Our IR drop prediction for 100K cell instances can be completed within 2 minutes. Our proposed method provides a fast IR drop prediction to speedup ECO.

Among many asynchronous design styles, precharge half/full buffers (PCHB/PCFB) are popular due to small area and high performance. This paper proposes new test methodology for PCHB/PCFB asynchronous circuits. Our proposed design for testability (DfT) does not break any internal feedback loop so it is small in area. There are two major theoretical contributions in this paper. First, this paper analyzes the fault effects of transition delay faults, which were not studied in depth by previous research. Second, we also analyze faults on fanout branches that break the isochronic fork assumption. One important conclusion is that these faults can not only degrade the circuit performance but also modify data so they must be tested. We propose three-pattern tests for stuck-at faults and four-pattern tests for transition delay faults. In addition, we propose a new model for ATPG so that existing tools can be used. On the average, our work achieves 93% and 92% stuck-at and transition delay fault coverage, respectively, which is much higher than previous techniques.

Excessive power supply noise (PSN), such as IR drop, can cause timing violation in VLSI chips. However, simulation PSN takes a very long time, especially when multiple iterations are needed in IR drop signoff. In this work, we propose a machine learning technique to build an IR drop prediction model based on circuits before ECO (engineer change order) revision. After revision, we can re-use this model to predict the IR drop of the revised circuit. Because the previous circuit(s) and the revised circuit are very similar, the model can be applied with small error. We proposed seven feature extractions, which are simple and scalable for large designs. Our experiment results show that prediction accuracy (average error 3.7mV) and correlation (0.55) are very high for a three million-gate real design. The run time speedup is up to 30X. The proposed method is very useful for designers to save the simulation time when fixing the IR drop problem.

Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS'89 benchmark circuits show the total test length of our proposed ILP method is 64% shorter than a greedy method.

With low power and variation-tolerant features, asynchronous have been widely used in advanced VLSI designs. Testing asynchronous circuits has become a very important practical issue. This research presents new test methodology, including design for testability (DFT) and automatic test pattern generation (ATPG), for asynchronous dual-rail circuits. The proposed DAC-scan cell is a hazard-free scan design, which can be applied to various implementations of dual-rail asynchronous circuits. Two-pattern stuck-at test and three-pattern delay test techniques are presented to detect local feedback faults in the circuits without inserting extra DFT into feedback loops. With our test methodology, we can use traditional full-scan ATPG to generate high fault coverage test patterns. Moreover, designers can tradeoff between fault coverage and area overhead by using different versions of DAC-scan cells.

This paper presents a physical-aware diagnosis technique for failing dies with multiple interconnect defects, including open and bridging. Our diagnosis technique considers fault masking/reinforcement and Byzantine effects. We use a section, a piece of interconnect, as the physical-aware diagnosis unit. We adopt the Single Location in a Cluster (SLIC) technique, where sections with similar simulation failure are grouped into a cluster. Simulations on benchmark circuits demonstrated that our accuracy is much higher than that of a commercial tool, with very close diagnosis resolution, when 10 defects are injected.

This paper proposes a technique, GALAXY, to speed up multicircuit simulation, where each circuit under simulation is identical in schematic but different in some parameters. GALAXY is based on the successive chord method, where the inverse Jacobian matrix (J-1) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up singlecircuit simulation by reusing J-1between consecutive time steps. Compared with a traditional Newton-Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%.

This paper presents a novel technique that modifies automatic test pattern generation test patterns to reduce time-averaged IR drop of a test pattern. We propose a fast average IR drop estimation, which is very close to the time-averaged IR drop of time-consuming transient simulation (R2= 0.99). We calculate the contribution of every node to these nodes inside IR-drop hotspot so that we can effectively modify only a few don't care bits in the test patterns to reduce IR drop. The experimental results show that our technique successively reduces time-averaged IR drop by 10% with almost no fault coverage loss and no test pattern inflation.

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36% test length reductions on large benchmark circuits while the SDQL quality remains almost the same.

This paper presents a novel diagnosis technique for multiple defects. This technique proposes a simple heuristic to partition the failures log so that hard-to-detect defects and easy-to-detect defects are likely to be separated. This technique requires only commercial diagnosis software with a simple add-on tool. No customized diagnosis software is needed. Simulations on benchmark circuits demonstrated the effectiveness of the proposed technique. Real silicon experiments on a real industrial product have been verified by physical failure analysis that our technique does not lead to wrong diagnosis for single defect cases.

Flexible electronics are a possible alternative for portable consumer applications and have many advantages. However, the circuit design for flexible electronics is still challenging, especially for sensitive analog circuits. Due to the different properties of flexible thin-film transistors (TFTs), conventional CMOS design techniques cannot be used directly on flexible electronics. Significant parameter variations and degradation effects of flexible TFTs further increase difficulties for circuit designers. In this paper, a reliability-aware circuit sizing approach is proposed for the analog circuits with flexible TFTs. The process variation, bending, and degradation effects of flexible TFTs in the optimization flow are considered simultaneously. Instead of optimizing the fresh yield and lifetime yield separately, a unified optimization approach is proposed to consider the two yield issues simultaneously. As shown in the experimental results, the proposed approach can further improve the lifetime yield and significantly reduce the design overhead with a fast computation time.

Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are <; 5%.

This paper presents a representative random walk technique for fast transient IR-drop analysis. It selects only a small number of nodes to model the original network for simulation so that the memory and runtime are significantly reduced. Experimental results on benchmark circuits show that our proposed technique can be up to 330 times faster than a commercial simulator while the average error is less than 10%. Furthermore, the exhaustive simulation of all 26-K delay fault test patterns on a 400-K-gate design can be finished within a week. The proposed technique is very useful to simulate capture cycles for identifying the test patterns that cause excessive IR drop during at-speed testing.

Rnv8T nonvolatile SRAM combines conventional SRAM and resistive RAM to provide both fast access speed and data retention. Traditional test methods for conventional SRAM or resistive RAM are not suitable for nonvolatile SRAM. This paper analyzes the defective behavior of the Rnv8T nonvolatile SRAM based on defect injection and simulation. Simulation results showed that the inject defects caused stuck-at faults and transition faults which escaped from conventional March tests. Based-on the defective behavior and circuit operations, a straight forward test algorithm is proposed to detect the escaped faults.

This paper presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious IR drop. However, leakage defects in power TSV should be tested, even though the number of power TSV is large. This paper proposes a test generation flow to detect path delay faults induced by defective power TSV. The proposed technique is demonstrated on an 18-tier, 7 x 7 multi-core 3D IC model. In the experiment of b18 and b19 benchmark circuits, all detectable path delay faults induced by power TSV can be tested by around hundred test patterns. This technique requires no extra DfT hardware overhead.

This is a massively parallel ATPG that explores device-level, block-level and word-level parallelism in GPU. Eight-detect transition fault ATPG experiments on large benchmark circuits show that our technique achieved 5.6 and 1.6 times speedup compared with a single-core and 8-core CPU commercial tool, respectively. Test patterns selected from our test set are about the same length and quality as those selected from commercial N-detect ATPG. To the best of our knowledge, this is the first proposed GPU-based ATPG algorithm.

Testing integrated circuits under delay defects becomes an essential quality control step in nanometer fabrication technologies, which encounter inevitable process variations. Prior methods on automatic test pattern generation (ATPG) for delay defects, however, are either overly simplified (e.g., timing unaware) or computationally too expensive. This paper proposes a viable ATPG method based on a satisfiability (SAT) formulation using timed characteristic functions (TCFs), which gained notable scalability enhancement very recently. The approach provides a balanced trade-off between accuracy and efficiency. Experimental results show promising runtime and fault coverage improvements over prior SAT-based timing-aware ATPG methods. Moreover, our method provides a nice complement to commercial tools in enhancing test quality.

This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.

This paper proposes four logic-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-chain bridging faults, unlike existing scan chain fault models, depend on the previous scan inputs as well as primary inputs. A bridging pair extraction algorithm is proposed to quickly extract bridging pairs from the layout. The paper proposed two sets of structural reduction techniques so that runtime is very short. Experimental results on ISCAS benchmark circuits show that, on the average, logic-chain bridging faults can be diagnosed within an accuracy of four bridging pairs. The techniques are still applicable when there are only 10 failing patterns due to limited ATE failure memory. This paper demonstrates the feasibility to diagnose logic-chain bridging faults by software.

This article presents a hybrid Automatic Test Pattern Generation (ATPG) technique using the staggered Launch-On-Shift (LOS) scheme followed by the one-hot launch-on-shift scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multimillion-gate scan designs. In case the scan design contains multiple synchronous clock domains, and each group of synchronous clock domains is treated as a clock group and tested using a launch-aligned or a capture-aligned LOS scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.6X to 1.8X, while the ATPG runtime was increased by 40% to 50%, when compared to the one-hot clocking scheme alone.

This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.

This paper presents a novel diagnosis algorithm for small delay defects (SDD). Faster-than-at-speed test sets are generated by masking long paths in the circuit for testing SDD. The proposed diagnosis technique uses timing upper and lower bound to improve the diagnosis resolution. Also, timing-aware single location at a time (TA-SLAT) technique is proposed to diagnose multiple SDD. Test results of different test speeds, if available, can be combined to further improve the diagnosis results. Experimental results on five advanced industrial designs show the accuracy of the proposed technique.

This paper presents a design for testability (DfT) technique to reduce the peak power supply noise (PPSN) during scan chain shifting. The proposed partition technique reduces the maximum flip-flop density that belongs to the same test clock. The experimental data on large benchmark circuits show that IR drop are reduced by 38.7% on the average compared with the circuit before optimization. Our proposed technique quickly optimizes a half million gate design within 14 minutes while the commercial IR drop simulation tool took over 3 hours.

This paper proposes a bit-level parallel ATPG algorithm (SWK) that generates multiple test patterns at a time. This algorithm converts decisions into bitwise logic operation so that W (CPU word size) test patterns are searched independently. Multiple objectives for different quality metrics can therefore be achieved in a single test generation process. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits show that SWK test sets are better in many quality metrics than traditional 50-detect test sets, while the length of the former is shorter. Also, patterns selected from large N-detect pattern pool cannot achieve the same or higher quality than patterns generated by SWK.

This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multi-million-gate scan designs. In case the scan design contains multiple synchronous clock domains, each group of synchronous clock domains is treated as a clock group and tested using a launch aligned or a capture aligned LOC scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.1X to 2.1X, while the ATPG runtime was increased by 10% to 50%, when compared to the one-hot clocking scheme alone.

This paper presents a static timing analyzer for flexible TFT circuits (STAF). Gate delay models are first characterized by SPICE simulation as a function of load capacitance and mobility. A block-based STA algorithm is then applied to identify the longest path delay and shortest path delay change in different regions under bending. STAF plots maps that show "bending hot spots" which, when bended, significantly change the circuit timing. Experimental results on ISCAS'89 benchmark circuits show that the longest path delay can increase by up to 32% when a single region is bended. What is worse, the shortest path change can be up to 9%, which cannot be simply fixed by reduced clock speed. STAF provides important timing information for flexible TFT circuit designers.

This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.

This paper presents a design for testability and minimum leakage pattern generation technique to reduce static power during test and burn-in for nanometer technologies. This technique transforms the minimum leakage pattern generation problem into a pseudo-Boolean optimization (PBO) problem. Nonlinear objective functions of leakage power are approximated by linear ones such that this problem can be solved efficiently by an existing PBO solver. A partitioning-based algorithm is applied for control point insertion and also CPU time reduction. Experimental results on the IEEE ISCAS'89 benchmark circuits using Taiwan Semiconductor Manufacturing Company 90-nm technology show that, for large circuits, the static power is reduced from 8.3% (without partition) to 17.47% (with 64 partitions). Besides, the overall CPU time is reduced from 3600 s (without partition) to 83 s (with 64 partitions). This technique reduces the static power without changing the manufacturing process or library cells.

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS'89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.

Diagnosis for systematic defects is very critical for yield learning in nanometer technology. This paper presents a bridging fault diagnosis which identifies a single layer of systematic defects (LSD), where more than expected numbers of bridging faults are located. The proposed technique is a layout-aware diagnosis which contains bridging pair extraction, structural analysis, and layer-oriented covering. Instead of treating each failing CUT independently, a statistical method (Z-test) is applied to diagnose all CUTs simultaneously. Experiments on six of seven large ISCAS'89 benchmark circuits successfully diagnose LSD for single bridging fault as well as multiple bridging faults.

This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10 V) and very low voltage (7 V), followed by a 200 second voltage stress at 30 V. Seven unreliable CUT that escape nominal voltage (NV) testing are successfully caught by VLV testing and there is no CUT that is caught by NV testing but escapes VLV testing. The results indicate that VLV testing is more effective than NV testing in screening out unreliable a-Si TFT circuits.

Built-in Self Test (BIST) is a crucial technique for testing embedded memory cores in a System-on-Chip (SoC). However, there is not much published work on BIST design optimization for multiple memory cores in the SoC designs. In this paper, we present a method for the BIST design optimization problem for large-scale SoC embedded memory cores, considering various real-world constraints such as peak current, IR drop, etc. Our method is based on a three-stage technique: (1) assignment, (2) legalization, and (3) refinement. The first stage adopts an integer linear programming (ILP) formulation for each memory partition to find a desired assignment of memory cores to controllers. The second stage then legalizes the assignment to meet user-specified assignment constraints. The last stage refines the solution to further reduce its cost. Experimental results show that our method can reduce the test time by 26.6%, the routing length by 8.9%, and the area by 24.1%, compared with a heuristic method currently used in industry.

This poster presents Power Scan, a design-for-testability for power switches in VLSI designs. It measures IR drop in function mode and detects leakage current in sleep mode. Power Scan reduces the test cost at the price of small area overhead.

This poster presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin-film (a-Si TFT) transistor technology as an economic alternative to burn-in. A total number of 140 CUT implemented in 8¿m a-Si TFT technology are tested at nominal voltage and very-low-voltage. The results indicate that VLV testing is effective in screening out unreliable a-Si TFT circuits.

This poster presents a secure test wrapper (STW) design that is compatible with IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information such as encryption keys. To reduce the STW area, flip-flops in the wrapper boundary cells are configured as an LFSR to generate the gold key. Experimental results on AES show that STW provides very high security (2257) at the price of about 5% area overhead with respect to the original IEEE 1500 standard test wrapper.

We propose five logic-to-chain bridging fault models, which involve one net in the combinational logic and the other net in the scan chain. Test results of logic-to-chain bridging faults, unlike any existing fault, depend on the previous scan inputs as well as primary inputs. An accurate diagnosis technique is presented to locate logic-to-chain bridging faults. In addition, a bridging pair extraction algorithm is proposed to quickly extract bridging net pairs from the layout. Experimental results on ISCAS benchmark circuits show that, on the average, logic-to-chain bridging faults can be diagnosed within an accuracy of three bridging pairs. The technique is still applicable when only ten failing patterns are recorded on the tester.

A diagnosis technique is presented to locate multiple timing faults in scan chains. Jump simulation is a novel parallel simulation technique which quickly searches for the upper and the lower bounds of every individual fault. The proposed technique takes into account the interaction of multiple faults so the diagnosis results are deterministic, not probabilistic. This technique is very useful in the production test environment because it requires only regular automated test pattern generator patterns, not specialized diagnosis patterns. Experiments on ISCAS'89 benchmark circuits show that this technique can successfully pinpoint almost every single one of 16 hold-time faults in a scan chain of more than 800 scan cells. The proposed technique is still effective when failure data are limited or faults are clustered.

A cyclic-CPRS (column parity row selection) technique is presented to diagnose built-in self tested (BISTed) circuits, even in the presence of many unknowns and transient errors. The novel cyclic scan chains retain the transient errors and unknowns in the CUT until they are fully diagnosed. Instead of masking the unknowns, Cyclic-CPRS directly diagnoses the unknowns as if they were errors. Direct diagnosis of unknowns not only eliminates the masking circuitry but also enhances the diagnosis resolution. Experimental results show that Cyclic-CPRS is very successful even in the presence of 10% errors and unknowns. The proposed technique is especially suitable for nanometer technologies, in which transient errors and systematic defects are becoming serious problems.

Column selection row parity (CPRS) diagnosis is an X-tolerant and low aliasing technique that is suitable for the BIST environment. A row selection LFSR randomly selects outputs of multiple scan chains so that unknowns can be tolerated. Column and row parities of selected outputs are observed to solve linear equations for the error positions. Experimental data show that CPRS achieves nearly perfect diagnosis, even in the presence of 1 percent unknowns. CPRS compresses the diagnosis data because only parities of circuit responses, instead of responses themselves, are observed. Two error distribution models (scattered and clustered) are developed and analyzed to show the effectiveness of CPRS. The analytical results are demonstrated to be accurate by more than 10,000 experiments

A diagnosis technique is presented to locate seven types of single faults in scan chains, including stuck-at faults and timing faults. This technique implements the Jump Simulation, a novel parallel simulation technique, to quickly search for the upper and lower bounds of the fault. Regardless of the scan chain length, Jump Simulation packs multiple simulations into one so the simulation time is short. In addition, Jump Simulation tightens the bounds by observing the primary outputs and scan outputs of good chains, which are ignored by most previous techniques. Experiments on ISCAS'89 benchmark circuits show that, on the average, only three failing patterns are needed to locate faults within ten scan cells. The proposed technique is still very effective when failure data is truncated due to limited ATE memory

A BIST diagnosis technique is presented to diagnose multiple errors in multiple scan chains. An LFSR randomly selects outputs of multiple scan chains every scan cycle. The column parity and row parity of the selected scan outputs are observed every scan cycle and every scan unload, respectively. Compared with other techniques, which diagnose no more than 15% errors, CPRS correctly diagnoses all errors in the presence of 1% unknowns. The cost of this technique is area overhead and one additional output observed every scan cycle.

This paper presents a Jump scan technique (or J-scan) for low power testing. The J-scan shifts two bits of scan data per clock cycle so the scan clock frequency is halved without increasing the test time. The experimental data show that the proposed technique effectively reduces the test power by two thirds compared with the traditional MUX scan. The presented technique requires very few changes in the existing MUX-scan design for testability methodology and needs no extra computation. The penalties are area overhead and speed degradation.

This paper presents a diagnosis technique to locate hold-time (HT) faults and setup-time (ST) faults in scan chains. This technique achieves deterministic diagnosis results by applying thermometer scan input (TSI) patterns, which have only one rising or one falling transition. With TSI patterns, the diagnosis patterns can be easily generated by existing single stuck-at fault test pattern generators with few modifications. In addition to the first fault, this technique diagnoses remaining faults by applying thermometer scan input with padding (TSIP) patterns. For the benchmark circuits (up to 6.6 K scan cells), experiments show that the diagnosis resolutions are no worse than 15, even in the presence of multiple faults in a scan chain.

A resistive-open defect is an imperfect circuit connection that can be modeled as a defect resistor between two circuit nodes that should be connected. A stuck-open (SOP) defect is a complete break (no current flow) between two circuit nodes that should be connected. Conventional single stuck-at fault diagnosis cannot precisely diagnose these two defects because the test results of defective chips depend on the sequence of test patterns. This paper presents precise diagnosis techniques for these two defects. The diagnosis techniques take the test-pattern sequence into account, and therefore, produce precise diagnosis results. Also, our diagnosis technique handles multiple faults of different fault models. The diagnosis techniques are validated by experimental results. Twelve SOP and one resistive-open chips are diagnosed out of a total of 459 defective chips.

A diagnosis technique to locate single stuck-at faults and multiple timing faults in scan chains is presented. This technique applies single excitation (SE) patterns, in which only one bit is flipped in the presence of multiple faults. With SE patterns, the problem of unknown values in scan chains is eliminated. The diagnosis result is therefore deterministic, not probabilistic. In addition to the first fault, this technique also diagnoses the remaining timing faults by applying multiple excitation patterns. Experiments on benchmark circuits show that average diagnosis resolutions are mostly less than five, even for the tenth fault in the scan chain.

LSI logic has designed and manufactured two test chips at CRC. These test chips were used to investigate the characteristics of actual production defects and the effectiveness of various test techniques in detecting their presence. This paper presents a characterization of the defects that shows that very few defective chips act as if they had a single-stuck fault present and that most of the defects cause sequence-dependent behavior. A variety of techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This strategy doesn't guarantee that the defect coverage is retained. This paper presents data obtained from applying a variety of test sets on two chips (Murphy and ELF35) and recording the test escapes. The reductions in test size can thus be compared with the increases in test escapes. The data shows that, even when the fault coverage is preserved, there is a penalty in test quality. Also presented is the data showing the effect of reducing the fault coverage. Techniques studied include various single-stuck-fault models including inserting faults at the inputs of complex gates such as adders, multiplexers, etc. This technique is compatible with the use of structural RTL netlists. Other techniques presented include compaction techniques and don't care bit assignment strategies.

A technique capable of diagnosing single and multiple stuck-open and stuck-at faults is presented. Eleven sequence-dependent chips (test results depend on the order of test patterns) are diagnosed. Seven of them are diagnosed as having single stuck-open faults. Two of them are diagnosed as having multiple stuck-at and stuck-open faults.

This paper studies the behavior of stuck and resistive open defects. The effects on test results of three test conditions (supply voltage, speed, temperature) as well as test patterns applied are evaluated. Diagnosis schemes for stuck and resistive opens are also presented. Five Murphy chips are diagnosed as having stuck open defects and one chip is diagnosed as having a resistive open defect. Their experimental data match our expectations for stuck opens and resistive opens.

This paper resolves two issues regarding diagnosis of tunneling opens: efficient screening and accurate localization. In the first part, a test pattern selection and sorting algorithm is presented. It is shown that the presented algorithm saves I/sub DDQ/(t) test time without impacting on its effectiveness. The second part of this paper presents a locating algorithm which combines both VLV and I/sub DDQ/(t) test results. This technique is shown to be able to accurately locate the tunneling opens with higher resolution than commercial single stuck-at fault diagnosis tool.

A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or I/sub DDQ/ testing. Theoretical calculations as well as Boolean and I/sub DDQ/ experiments confirm the existence of tunneling opens. The Murphy experimental data show that seven out of nine VLV-only failure circuits can be explained by this failure mode. All these seven circuits survived 366 hours temperature burn-in. Finally, a cost effective screening strategy is proposed.

This paper presents the results for very detailed studies of pattern and timing-dependent failures from the 309 dies in the retest of an experimental test chip. 22 out of the 50 CUTs with pattern-dependent failures had test escapes if the test sets were reordered. Some timing-dependent failures became timing-independent combinational (TIC) defects at very low voltage. Multiple-detect single stuck fault test sets have high transition fault coverage. Most dies with TIC or non-TIC defects were close to gross failures or next to the wafer periphery.