This paper describes a fully synthesizable digital-to-analog converter (DAC). It is important to develop an automated netlist generation and synthesizable design methodology for mixed-signal circuits. To fill in the scarcity of synthesizable DACs, we propose a multi-bit full-synthesizable current DAC using shifting current mirror architecture with a multi-segmented data weighted averaging (MSeDWA) mismatch correction algorithm. It provides robustness against process, voltage, and temperature (PVT) variations by means of a programmable bias generator, which suppresses the circuit variations by >2.7 ×. The use of power-gating standard cells provides a flexible selection of current mirror types, thus achieving a widening of the voltage operation range. Moreover, stage separation and appropriate gain configuration ensure high linearity.With the MSeDWA technique, the total harmonic distortion (THD) is further improved by 7.7 dB. Operating between 14 MHz to 56 MHz, the analog and digital circuits consume 8.64-56.64 μW and 217-629 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.03 μW/kHz while maintaining a maximum THD of 39.9 dB (1.01%).

Ferroelectric random access memory (FeRAM) is a promising candidate to further dynamic random access memory (DRAM) scaling. However, the design of the FeRAM bit cell is nontrivial as the ferroelectric device model is not well supported by EDA tools. Modern integrated circuit design heavily depends on circuit-level SPICE simulators that integrate compact device models through modified nodal analysis (MNA) representation. This paper presents a novel MNA-based SPICE simulation method for ferroelectric device models, targeted at the design space exploration of FeRAM bitcells. Furthermore, this paper provides a co-design procedure for FeRAM bitcells and sense amplifiers via a comprehensive case study.

This paper presents a system-on-chip (SoC) architecture for an active implantable microsystem that combines electrical recording with optogenetic stimulation for closed-loop neuromodulation. The SoC is designed to support a 4-shank optrode (opto-electrode) fork with 8 differential recording channels (0.1-5000Hz bandwidth, 10mVpp range, 12-bit resolution) to observe neural signals on electrodes and 32 driver circuits (2mA range, 6-bit current resolution with μs timing resolution) for microLED optical stimulation. Each SoC additionally integrates diagnostic instrumentation to measure electrical resistance across any of its I/O lines. The SoC features a custom 4-wire interface that provides power and data communication across multiple chips using a shared bus allowing for multiple forks to be stacked to form two dimensional optrode arrays. Each chip has an independent controller that receives, interprets and executes commands, and can transmit neural data while simultaneously controlling LED outputs. The circuit is implemented in a 180nm CMOS process, with each chip occupying a 5mm×2.45mm silicon footprint, designed specifically to mount on the base of the silicon optrode fork.

This paper presents a low-power, low-noise, gain and bandwidth individually tunable analog front-end (AFE) for ExG signals. The proposed three-stage AFE with a bandwidth programmable amplifier enables individually tuning the bandpass cutoff frequencies in the range of 0.4 to 1.9kHz as well as the gain from 40 to 63dB. Designed in a$0.35 \mu\mathrm{m}$CMOS process with an area of 0.3mm2, the AFE achieves over 120dB CMRR with input referred noise of 516nVrms and a noise efficiency factor of 2.57. The chip consumes$2.5 \mu\mathrm{A}$at 1.8V supply.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

Concurrent neural signal instrumentation withstanding neural stimulation artifacts is essential for bi-directional neural interfaces to guarantee signal integrity. In this work, different front-end structures and stimulation artifact mitigation techniques are firstly reviewed to benchmark their step response speed. Then, a mixed domain level-crossing scheme is proposed to achieve fast dynamic response with minimized hardware overhead. The benefit of extending the phase detection range of the phase detectors in VCO-based continuous time$\rm \Delta \Sigma $modulators is investigated with stability and noise consideration. Then a shift-register-based phase counter is proposed to extend the phase detectors’s detection range, thereby increase quantization resolution and stability margin for in-band noise optimization. The proposed VCO-based neural front-end was fabricated in a 180 nm CMOS process. The prototype achieves$6.38~\mu $Vrms input-referred noise over 0.5 Hz-10 kHz bandwidth. With a linear input range of 120 mVpp, it exhibits a SNDR of 71.6 dB and a DR of 77.0 dB, which could be further extended up to 100 dB in the artifact adaption mode. Measurements verify that the proposed neural front-end can recover from rail-to-rail differential mode or common mode artifacts within 10$\mu \text{s}$(minimum$6.25~\mu \text{s}$) while the superposed small signal can be recorded uninterruptedly.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

High-density large-scale implantable electrode arrays enable neural recording with cellular level resolution. Active electrodes with integrated instrumentation and processing are necessary for single neuron activity recording to minimize interference and reduce bandwidth for the signal conversion and transmission. This introduces design challenges for circuits miniaturization to match the electrode density and meet the dynamic range requirement. This paper proposes a clockless, area efficient spike detection neural front-end enabled by a VCO-based level-crossing analog to digital converter (LC-ADC) and spike detection algorithm based on continuous time nonlinear energy operator (CT-NEO). Level-crossing events and corresponding timing information can be directly generated by the proposed LC-ADC. A continuous time NEO algorithm is proposed and implemented, featuring low complexity and high detection accuracy, MATLAB simulation shows that the algorithm can still achieve 70% accuracy at an estimated signal-to-noise ratio (SNR) of -4dB. Implemented in a 65 nm CMOS process, the proposed front-end consumes 3.15 $\mu$W and 0.00385 mm2active area.

An input-output regulated adaptive ramp ($\mathrm{IOR}^{2})$ for fast load transition of pulse width modulation (PWM) buck convertor is presented. The scheme employs an adaptive ramp regulated by input and the voltage from the error amplifier to achieve fast load response and low line and load regulation rate. Simulation shows that an under/overshoot voltage of −32 mV and 35 mV, with $8 \mu$ and $8.3 \mu \mathrm{s}$ recovery time are respectively obtained for the load current stepping between 1 A and 1.7 A. The line/load regulation rate is respectively $12.4 \mu \mathrm{V} / \mathrm{V}$ and $1.04 \mathrm{mV} / \mathbf{A}$. Implemented in a $0.25 \mu \mathrm{m}$ BCD process, the proposed IOR2PWM regulator is capable of converting input voltage of 5 V to 65 V to output range of 3.3 V to 60 V with adjustable switching frequency up to 2.2 MHz, showing a peak efficiency of 94.5% at 1 A load current.

Brain machine interface systems will require recording thousands of neural channels in parallel to acquire large scale neuronal activity. High bandwidth action potential signal will overload the data communication bandwidth, and on-site spike sorting can extract essential information, however, requires extensive computational resources to achieve high classification accuracy. This demands for high resources consuming, especially in large-scale real-time sorting systems. In this work, a customized unsupervised training engine incorporated with distributed and optimized sorting channels is presented in order to reduce the hardware complexity without compromising the accuracy of spike sorting. A mixed-domain feature set is extracted in each channel, followed by feature based sorting. Each channel will constantly monitor the sorting accuracy and will request training engine intervention when in need. The proposed system is implemented in a 180 nm CMOS process, consuming only 0.33 μ W/channel with a clock of 25 kHz and power supply of 1.8 V, and in-channel sorting occupies 0.0023 mm2, with training engines occupying 1.956 mm2, which can be shared by all the channels.

In this paper, we proposed a resource-efficient 'QRS' detector with superior detection accuracy. Inspired by the strategy of the folded architecture, we adopted a reconfigurable time-sharing computation unit with a pipeline schedule. To further precisely locate the position of the 'R' peak and minimize the extra hardware cost, we designed the position calibration unit (PCU) based on the data compression technique. The proposed architecture was implemented on Xilinx Zynq-7000 with Verilog programming language. The proposed architecture achieves a sensitivity, Se of 99.76%, a precision, +P of 99.85%, and a detection error rate, DER of 0.40% on MIT-BIH database, which attains the best performance compared to state-of-the-art designs. Furthermore, the proposed architecture achieves a better hardware efficiency with 13×, 1.28×, and 4.35× reductions in computing resources, storage memory, and power consumption, respectively.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

This paper presents a 32×32 ISFET sensing array with in-pixel digitisation for pH sensing. The in-pixel digitisation is achieved using an inverter-based sensing pixel that is controlled by a triangular waveform. This converts the pH response of the ISFET into a time-domain signal whilst also increasing dynamic range and thus the ability to tolerate sensor offset. The pixels are interfaced to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast sensor readout whilst using minimal silicon area. Parallel output of 32 TDC interfaces are serialised to achieve fast data though-put. This system is implemented in a standard 0.18 μm standard CMOS technology, with a pixel size of 26 μm × 26 μm and a TDC of 26 μm × 180 μm. Simulation results demonstrate that chemical sampling of up to 5k frames per second can be achieved with a clock frequency of 160 MHz and a TDC resolution of 190 ps. The total power consumption of the overall system is 7.34 mW.

This paper presents an oscillator based potentiostat with switch-cap feedback for current sensing applications. In this work, a sigma-delta modulator is realized using current as input and charge as the feedback. The current input is integrated at the input capacitance and the voltage difference between the integrated value and reference input is converted to current via a transconductor. This current is then fed into a current controlled ring oscillator and the frequency output drives the switch-cap circuits to compensate the input current. Therefore, the current input can be directly readout as frequency deviation, or can be further converted to digital output via a frequency to digital converter. The proposed system is implemented in a typical 0.18μm CMOS technology, with total area of 80 × 250μm2. A differential structure was implemented to minimize the parasitic and kick back influence, with oscillator base frequency at 491MHz. A counter based frequency to digital converter with an additional CIC filter was implemented to convert the differential frequency signal to digital domains at 16MHz sampling frequency. Simulation results demonstrated that a dynamic range of 52dB was achieved with input range of ±2.5μA.

Closed loop neuromodulation, where the stimulation is controlled autonomously based on physiological events, has been more effective than open loop techniques. In the few existing closed loop implementations which have a feedback, indirect non-neurophysiological biomarkers have been typically used (e.g. heart rate, stomach distension). Although these biomarkers enable automatic initiation of neural stimulation, they do not enable intelligent control of stimulation dosage. In this paper, we present a novel closed loop neuromodulation System-on-Chip (SoC) based on a dual signal mode that is detecting both electrical and chemical signatures of neural activity. We use vagus nerve stimulation (VNS) as a design case here. Vagal chemical (pH) signal is detected and used for initiating VNS and vagal compound nerve action potential (CNAP) signals are used to determine the stimulation dosage and pattern. Although we used the paradigm of appetite control and neurometabolic therapies for developing the algorithms for neurostimulation control, the SoC described here can be utilised for other types of closed loop neuromodulation implants.

This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 μm CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO® Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10 kHz bandwidth, 110 dB dynamic range and μV-level output noise.

The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75 μW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3 kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4 μW. The circuit has been implemented in a commercially available 0.35 μm CMOS technology with core occupying a footprint of 0.12 mm2.

In this paper, we present a new method for neural spike sorting based on Continuous Time (CT) signal processing. A set of CT based features are proposed and extracted from CT sampled pulses, and a complete event-driven spike sorting algorithm that performs classification based on these features is developed. Compared to conventional methods for spike sorting, the hardware implementation of the proposed method does not require any synchronisation clock for logic circuits, and thus its power consumption depend solely on the spike activity. This has been implemented using a variable quantisation step CT analogue to digital converter (ADC) with custom digital logic that is driven by level crossing events. Simulation results using synthetic neural data shows a comparable accuracy compared to template matching (TM) and Principle Components Analysis (PCA) based discrete sampled classification.

This paper identifies and addresses key design considerations and trade-offs in the implementation of a CMOS high-resolution microheater array for Lab-on-Chip (LOC) applications. Specifically, this is investigated in the context of facilitating the in vitro thermal stimulation of single neurons. The paper analyses the electro-thermal response (by means of COMSOL simulations) and reliability issues (such as melting and electromigration) of different microheater designs. The analysis shows that a small-area heater is more efficient in terms of power, but it has more reliability problems essentially due to electromigration effects. For the proposed heater designs, the expected lifetime is a few days (in continuous operation) in the worst scenario, which is still generally acceptable for LOC applications.

This paper proposes a novel, octagonal shaped CMOS image sensor (CIS) array for use in tandem with colored LED illumination and a corresponding, innovative pixel scanning method. The octagonal shape of the pixel array allows the CIS to make near-optimal use of silicon real estate by matching the perimeter of the pixel array to the focal plane area of lenses used in Wireless Capsule Endoscopies (WCE). Providing illumination by sequencing different-colored LEDs allows the system to reuse the same pixels to capture different colors at different times, thus removing the need for manufacturing a Color Filter Array (CFA) and effectively trading temporal for spatial resolution. The system was designed with AMS 0.35µm 2P4M CMOS technology. The simulated system consumes 1.06 mW from a 2.5 V supply at 2.217 frames/sec operation.

This paper presents a novel method and circuit for feature-driven data acquisition in single neuron recording. By dynamically adjusting the phase of the sampling clock in a Successive Approximation Register (SAR) Analogue to Digital Converter (ADC), the samples can be maximally aligned to the spike extrema (peaks). This is achieved by using spike detection to switch from a `coarse' to `fine' sampling clock, and triggering a peak-search algorithm to determine the offset between the peak occurrence and the coarse clock. Subsequent samples are then aligned to the peak by shifting the coarse clock by the measured offset. This adaptive sampling scheme thus allows for improved temporal precision on features of interest (i.e. peaks) whilst maintaining a coarse effective sampling rate, also minimising power consumption. The proposed method reduces the output data bandwidth by approximately 70% in comparison to a fixed-sampling rate data converter that would achieve similar precision in peak alignment. The circuit implementation achieves 9-bit resolution with a 93 fJ/conversion-step energy efficiency in a standard 0.35 μm CMOS technology.

This paper introduces a CMOS based system that has been designed to allow parallel comparison of fragmented DNA sequences for on-chip assembly. The compatibility of different existing PC-based algorithms for implementation in CMOS is compared and the overlap-layout-consensus approach is found to be the most suitable one. The designed system comprises a scalable processing array capable of parallel computation, which allows identification of overlaps in DNA fragments in addition to error tolerance through dynamic programming. Analysis shows that there is a “pixel area vs computation time” trade-off when implementing such a parallel architecture. Results from a hypothetical assembly confirm good overlap detection and error tolerance, with up to 94% similarity in the detected overlaps, when the error is as much as 10%.

In this paper, we present a novel, ultra-long-time-constant analogue integrator for a PID controller in Lab-on-Chip (LOC) applications. A time constant of up to 5 seconds is achievable using a capacitance of only 18pF by exploiting transconductance reduction techniques involving current splitting and gm-attenuated OTA. Additionally, this architecture provides the ability to digitally tune the time constant from 200ms to 5s with 4-bit programmability. The design achieves a temperature dependance of 1.2% over the range from 0°C to 100°C with micropower consumption.

In this paper, a novel chemical sensor system utilizing an Ion-Sensitive Field Effect Transistor (ISFET) for pH measurement is presented. Compared to other interface circuits, this system uses auto-zero amplifiers with a pingpong control scheme and array of Programmable-Gate Ion-Sensitive Field Effect Transistor (PG-ISFET). By feedback controlling the programable gates of ISFETs, the intrinsic sensor offset can be compensated for uniformly. Furthermore the chemical signal sensitivity can be enhanced due to the feedback system on the sensing node. A pingpong structure and operation protocol has been developed to realize the circuit, reducing the error and achieve continuous measurement. This system has been designed and fabricated in AMS 0.35μm, to compensate for a threshold voltage variation of ±5V and enhance the pH sensitivity to 100mV/pH.

This paper presents a novel readout circuit for a pH sensitive programmable-gate ion-sensitive field effect transistor (PG-ISFET) to overcome bias issues due to threshold voltage variation and increase output-referred sensitivity. Compared to other commonly-used ISFET readouts, this circuit uses two extra programmable nodes which are driven by a feedback configuration. Using the device in a source follower configuration, one node is used to evaluate and cancel the offset of the intrinsic device while the other tracks and amplifies changes in pH. A sample and hold protocol has been developed to minimize the leakage effects and improve the pH sensing range. The system has been designed and fabricated in AMS 0.35 mum, to compensate for a threshold voltage variation of plusmn10.5 V and provide a pH sensitivity of 200 mV/pH.