COVID-19 is highly transmissible and pathogenic, representing a potential threat to health conditions in correctional environments worldwide. This threat could worsen in prison systems in developing countries due to high crowding levels, lack of individual hygiene materials, inadequate primary sanitary conditions, and difficulties in using health services. Attempts to provide a landscape of academic research findings on COVID-19 data usage from prison systems in developing countries have been limited. This scenario motivated us to carry out this systematic mapping study (SMS) to provide a comprehensive overview of the impacts that may prevent the effective use of COVID-19 data, critical issues, and gaps in the current academic research. Following the steps of a systematic mapping, we examined 79 studies returned from a search string and eight studies returned from the use of the snowballing technique and selected 37 from related journals and conferences published between 2020 and 2021. The results point to possible problems in the use of COVID-19, preventing its effective use in information systems.

This paper presents an approach on entrepreneurship education which helps to turn ideas into Minimum Viable Products (MVP) and to capacitate students to become entrepreneurs. In this approach, we integrate development and management project to different business models. Students acquire, in addition to technical competencies, skills on market knowledge and business modeling. This approach has been applied for several years in an informatics engineering course and suggests a set of activities on 18 weeks. Teachers’ perceptions and students’ opinions were collected through direct observations and using a questionnaire in order to evaluate the process behind this pedagogical project which goes beyond the walls of the university. Most of the students are satisfied with the process since they develop projects that have a good fit with the market needs and opportunities and some of them are close to creating a startup.

This work aimed to perform a systematic review of the literature on teaching parallel programming using low-cost clusters, identifying the main programming languages, hardware platforms and software tools used in teaching-learning this type of programming. The research results showed that the most used clusters in the teaching of parallel programming were assembled from multicore machines (Cluster Beowulf) and by single board computers (SBC), in addition to multicore machines with graphics acceleration cards (GPUs). Regarding the use of programming languages, software tools and parallelism libraries used in teaching parallel programming, it is observed that most of the researched works mentioned the use of C, C++, and JAVA programming languages, and as parallelism libraries the use of MPI, OpenMP, CUDA and Apache Hadoop. Furthermore, the tests on the clusters were carried out through the implementation of parallelized generic algorithms and, in some cases, using algorithms that involve matrix operations.

The growing gap between users and the Big Data analytics requires innovative tools that address the challenges faced by big data such as volume, variety, and velocity. Therefore, it becomes computationally inefficient to analyze this massive volume of data. Moreover, advancements in the field of Big Data applications and data science poses additional challenges, where High-Performance Computing (HPC) solution has become a key issue and has attracted attention in recent years.

Context: The growing use of Convolutional Neural Networks (CNNs) in scientific experiments and industry has resulted in the development of several Convolutional Neural Networks libraries. There is a need on the part of developers and scientists to identify scholarly works that evaluate the performance of these libraries on different computer architectures. Objective: Identify and systematize the CNN libraries benchmarkings. Method: A systematic literature mapping was conducted to analyze the scientific research in the field. Results: Systematic mapping found 12 papers that evaluate the performance of Convolutional Neural Networks on different computer architectures. Conclusion: The state of the art has been mapped, there are still few works that evaluate Convolutional Neural Networks libraries with statistical accuracy.

Context: The popularization of the use of Convolutional Neural Networks has created new challenges such as the use in embedded systems applications. Scientists, developers and organizations need to analyze the evolution of the field in industry and academia. Objective: To analyze the evolution of the area of Convolutional Neural Networks in industry and academia comparing the development between them. Methodology: A scientific mapping was conducted to analyze the scientific research in the field and a technological mapping was conducted to analyze the technological development in the field. Results: We identified 545 scientific papers and 33 patent applications. Conclusion: There is still a big difference between scientific development and technological development of the area, but the evolution of both is increasing.

In this paper we present a new WEB-based tool which allow the observation, analysis and identification of possible opportunities and threats on technological trends. For this purpose, we insert a new index, named for us as TW-Index - this name was given in reference to the term Technology Watch, which is a technique for technological forecasting called Monitoring and Intelligence Systems. The purpose of TW-Index is to provide the user the capacity of monitoring and identifying whether certain terms which are used for defining a technology or research are currently been searched and used in the Internet. For this, we used as a basis the Google Trends. So, in this paper we present three contributions: (i) the concept of the TW-index, (ii) a WEB-based system for measuring the impact of certain technology or research using their keywords, which are quantified using our TW-Index, and (iii) the analysis of patents deposited from UFS (Federal University of Sergipe, Brazil), from 1998 until 2014, which were studied using our TW-Index. These patents were classified into three areas of knowledge - Engineering and Sciences, Agrarian and Food Technology, and Health area. To use this software, can make a download and install it, using the code available in Moreno (2020).

Summary Summary Software‐Defined Networking (SDN) is an emerging network paradigm that has gained significant traction from many researchers to address the requirement of current data centers. Although central control is the major advantage of SDN, it is also a single point of failure if it is made unreachable by a Distributed Denial of Service (DDoS) attack. Despite the large number of traditional detection solutions that exist currently, DDoS attacks continue to grow in frequency, volume, and severity. This paper brings an analysis of the problem and suggests the implementation of four machine learning algorithms (SVM, MLP, Decision Tree, and Random Forest) with the purpose of classifying DDoS attacks in an SDN simulated environment (Mininet 2.2.2). With this goal, the DDoS attacks were simulated using the Scapy tool with a list of valid IPs, acquiring, as a result, the best accuracy with the Random Forest algorithm and the best processing time with the Decision Tree algorithm. Moreover, it is shown the most important features to classify DDoS attacks and some drawbacks in the implementation of a classifier to detect the three kinds of DDoS attacks discussed in this paper (controller attack, flow‐table attack, and bandwidth attack).

This Special Issue of Concurrency and Computation: Practice and Experience gathers seven selected research articles, which are the result of extended work previously presented at the Brazilian “XVII Simpósio em Sistemas Computacionais de Alto Desempenho,” WSCAD 2016, held in conjunction with the 28th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2016, Aracaju, SE, Brazil, October 5-7, 2016. Since 2000, this workshop has presented important and interesting research in the fields of computer architecture, high-performance computing, and distributed systems. The scope of the current special Issue is broad and representative of the multidisciplinary nature of high-performance and distributed computing, covering important issues of the field, such as parallel applications, GPU computing, energy consumption, and cloud computing. The papers and their main focus are the following. The paper entitled “Parallel rule-based selective sampling and on-demand learning to rank” by Mateus F. e Freitas, Daniel X. Sousa, Wellington S. Martins, Thierson C. Rosa, Rodrigo M. Silva, and Marcos A. Gonçalves uses parallelism techniques to improve the performance of the Learning to Rank (L2R) task. More specifically, the authors1 propose two methods to exploit parallelism on rule-based systems: Learning to Rank (L2R) training data sets using selective sampling and query-customized ranking models generated on the fly. The authors propose parallel algorithms and GPU implementations for these two cases showing that data set reduction takes only a few seconds with speedups of up to 148× over a serial baseline and that queries can be processed in only a few milliseconds with speedups of 1000× over a serial baseline and 29× over a parallel baseline for the best case. The extended work provides the implementations on multiple GPUs, further increasing the speedup over the baselines. Focusing on GPU computing, in the contribution2 entitled “Maximizing the GPU resource usage by reordering concurrent kernels submission,” authors Rommel A.Q. Cruz, Cristiana Bentes, Bernardo Breder, Eduardo Vasconcellos, Esteban Clua, Pablo M.C. de Carvalho, and Lúcia M.A. Drummond propose a reordering strategy to identify the best order to submit the kernels to execute on the GPU, aiming at maximizing its utilization and increasing the overall throughput. The authors model the problem as a series of knapsack problems and use a dynamic programming approach to solve them. The amount of resources is modeled as the knapsack capacity, and the strategy tries to fulfill the knapsack with kernels that take the most advantage of the available resources, favoring kernels with smaller execution time. The proposed strategy was evaluated using real-world and synthetic applications with different numbers of kernels and resource requirements. The results show that the reordering strategy provides significant gains in the average turnaround time and system throughput compared to the kernels submission implemented in modern GPUs. Tackling energy efficiency issues, in the work3 entitled “Energy efficiency and I/O performance of low-power architectures,” authors Pablo J. Pavan, Ricardo K. Lorenzoni, Vinícius R. Machado, Jean L. Bez, Edson L. Padoin, Francieli Z. Boito, Philippe O.A. Navaux, and Jean-François Méhaut present an energy efficiency and I/O performance analysis of low-power architectures with the goal of evaluating the viability of using them as storage servers. The results show that despite the fact that the power demand of the storage device accounts for a small fraction of the power demand of the whole system, significant increases in power demand are observed when accessing the storage device. The authors also investigate the access pattern impact on power demand, looking at the whole system and at the storage device by itself, finally comparing all of the tested configurations regarding energy efficiency. This study provides guidelines for the replacement of traditional storage servers by low-power alternatives. As a consequence, the choice will depend on the expected workload, estimates of power demand of the system, and factors limiting the performance. Related to cloud computing models, in the contribution4 entitled “Statistical analysis of Amazon EC2 cloud pricing models,” authors Gustavo Portella, Genaina N. Rodrigues, Eduardo Nakano, and Alba C.M.A. Melo show a statistical analysis for two Amazon cloud pricing models: on demand and spot. While the on-demand cloud instances are charged a fixed price and can only be terminated by the user, with very high availability, the spot instances are charged dynamically, which price is determined by a market-driven model and can be revoked by the provider when the spot price becomes higher than the user-defined price, having possibly low availability. The analysis for on-demand instances resulted in multiple linear regression equations that represent the influence of the characteristics of the processor and RAM memory in the composition of the price of different types of instances available on the Amazon EC2 provider. To analyze the Amazon spot pricing, the authors used time-smoothed moving averages by 12-hour periods, aiming to provide a price-availability trade-off to the user. With an extensive experimental evaluation, the authors conclude that the user's bid can be set at 30% of the on-demand price, with an availability above 90%, depending on the instance type. Also dealing with GPU computing, in the contribution5 entitled “DTM@GPU: characterizing and evaluating trace redundancy in GPU,” authors Leandro A. J. Marzulo, Alexandre C. Sena, Alexandre S. Nery, Cristiana Bentes, Igor M. Coelho, Maria Clicia S. de Castro, Saulo T. Oliveira, Tiago A. O. Alves, and Felipe M. G. França explore the concept of instruction reuse in GPUs. They propose the DTMGPU model that adapts the DTM (Dynamic Trace Memoization) technique to the NVIDIA GPU architecture. The proposed model considers the particularities of the GPU architecture in the reuse mechanism. Instruction reuse can be of two types: intra-thread and inter-threads. The authors perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%. Dealing with parallel and dataflow models, the paper6 entitled “DF-DTM: Dynamic Task Memoization and reuse in dataflow” and authored by Leandro Rouberte, Alexandre C. Sena, Alexandre S. Nery, Leandro A. J. Marzulo, Tiago A. O. Alves, and Felipe M. G. França also discusses instruction reuse and the DTM (Dynamic Trace Memoization) technique, but in a different environment, a Dataflow System. The authors propose the Dataflow Dynamic Task Memoization (DF-DTM) technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF-DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. This work also evaluates how reuse rates can be affected by limiting the subgraph size, memoization table size, task granularity, and problem size, showing that DF-DTM can yield good reuse rates in more realistic environments. Finally, considering GPU issues, the paper in this Special Issue,7 “Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs,” authored by Thiago Nasciutti, Jairo Panetta, and Pedro Lopes, presents a performance study on different optimizations for 3D stencil computations on GPUs. The focus is on memory-oriented optimizations with varying grid and stencil sizes. The optimizations reduce global memory contention caused by the set of multiprocessors. The optimizations evaluated are grid tiling, inserting spatial and temporal loops into kernels, register reuse, and some of their combinations. A standardized experiment evaluates performance variation with grid size and stencil size for each optimization. Experimental data show that codes that use these optimizations are up to 3.3 times faster than the classical stencil formulation and that the optimization degree depends on the grid and stencil sizes. We hope that the readers can benefit from the perspectives presented in this Special Issue. The topics covered in the papers are timely and important, and the authors have done an excellent job in presenting their innovative contributions. Regarding the reviewing process, our referees (integrated by recognized researchers from the international community) made a great effort in evaluating the papers. We would like to acknowledge their effort in providing us with excellent feedback at the right time. Therefore, we wish to thank all the authors and reviewers. Finally, we would also like to express our gratitude to the Editor in Chief of this Journal, for his advice, vision, and support.

This work investigates the use of Multi-layered Perceptron Networks (MLP) for attack detection, using the Arduino embedded system as a case study. This paper also investigates techniques to reduce the computational cost of ANN (Artificial Neural Networks), taking into account the low cost and low consumption requirements in order to ensure the feasibility of its implementation. As a result, we evaluated the MLP networks using metrics such as accuracy, precision, and coverage, as well as the classifier performance running on Arduino through time measurements (microseconds).

The complexity and growth of new smart objects networks are generating a new demand for the maintenance of these devices, with the need to remotely monitor and control these devices without consuming significant resources. Analyzing the memory and electric power consumption of the protocols used in the management of these networks is a way to highlight the best protocol alternatives for this type of application. This study develops an experimental study, analyzing the behavior of SNMP, Zabbix, and MQTT protocols, in terms of memory and electric power consumption, when it is used in an Internet of Things application, with a sensor device implemented on the ESP8266. The experiment is performed by monitoring devices in an environment with some Motes and a Zabbix server. The study analyzes the ROM and RAM memories occupied by the firmware code, in addition to the electric power consumption of each protocol. At the end, the study confirms that the three protocols analyzed are supported by the platform used. The research shows that the SNMP is the protocol that consumes the least amount of device memory, that there is no significant difference in the energy consumption between the protocols, and that the MQTT protocol is suitable to be used in this environment and it also enables a significant reduction in energy consumption.

This paper presents a survey on the main security problems that affect the communication protocols in the context of Internet of Things, in order to identify possible threats and vulnerabilities. The protocols RFID, NFC, 6LoWPAN, 6TiSCH, DTSL, CoAP and MQTT, for a better organization, were explored and categorized in layers according to the TCP / IP reference model. At the end, a summary is presented in tabular form with the security modes used for each protocol is used.

Internet of Things (IoT) is becoming part of our daily life. Indeed, studies predict a sharp market growth by 2020. One of the challenges of this fast-growing market is how to store and manage the amount of non-structured data generated by IoT devices. In this paper, we propose a hybrid storage architecture for IoT for addressing scalability, performance, and heterogeneity issues. We selected three of the most commonly used NoSQL databases (Redis, MongoDB, and Cassandra) to perform the first evaluation of our architecture. Our results suggest that the hybrid storage architecture is a feasible and promising approach to address some of the issues related to the ever-growing amount of data generated by IoT devices. Additionally, our findings also show that Redis achieves a better overall performance for the two chosen types of data, namely scalar and positional.

Ambient Assisted Living (AAL) is a proposal to assist in the maintenance of the health and well-being of the elderly or people with special needs. To this end, intelligent devices are used to extend the autonomy of individuals in the execution of the simple daily activities as well as to remotely provide health and social services. However, a problem emerges, how is it possible to ensure, in this context, that the AAL system is not interpreting a misplaced situation of the ambient or the patient? In this sense, the present work aims to study the context of failure detector in asynchronous distributed systems with unknown membership in order to design and develop a failure detector for the AAL system. As a result, it was statistic verified, in the controlled experiment, the necessity to improve the existent algorithm to this purpose.

Traffic reduction in network segments through cache implementations has become a major research topic due to the exponential increase in data requests through the network. Even with high-speed connections, the conventional model still depends on point-to-point communication between two systems. Throughout the world, more connected devices are, accessing services and obtaining information. To support this activity, servers must have massive storage to support creation, retrieval, updated and deletion of large amounts of data. Therefore, in studies of Information Centric Networks (ICN), this model has been widely discussed as the new content distribution model for the Internet. To provide improved network management many approaches are using software-defined networks (SDN) to develop flexible content-based networks. This paper proposes to use cache replication for ICN through SDN to avoid duplicated requests in the same connection. The redundant cache reduced the bandwidth consumed by duplicated requests, from a maximum of 3.20 Gbps to 2.07 Gbps, reducing the bandwidth consumption by 11.3%.

Systems-on-a-chip (SoC) represents a rupture on the traditional HPC infrastructure and started to be adopted together OS-level virtualization to provide services in Fog and Edge computing scenarios. In this work, we analyzed the performance of OS-level virtualization solutions - Linux Containers (LXC) and Docker - for HPC activities running in SoC systems in order to discover how OS-level virtualization and resource sharing affects the performance of virtualized environments. We evaluated CPU and (network and inter-process) communication performance taking in account two different scenarios: without communication between benchmark processes in execution and; with processes communication in a cooperative way. Results shows that both tools are suitable for HPC applications in SoC systems, despite the notice of some performance reduction due resource sharing.

Organizations need process data in real time. Cloud Computing is a common choice but it presents high latency on data transfer. As an alternative to reduces the latency, Edge computing based on System-on-a-Chip systems (SoC-based systems) can retain part of the data processing, allowing resource sharing among multiple requests through the use of OS-level virtualization. In this work, we analyze the performance of two popular OS-level virtualization solutions - Linux Containers (LXC) and Docker - for I/O-bound activities running in SoC systems, in order to understand how resource sharing affects the processing performance.

Software Defined Networking (SDN) is a new approach to computer networks that decouple the control from the data transmission function and is directly programmable through a high level programming language. In parallel Information Centric Network (ICN) influences the use of information through network caching, multipart communication and interaction of models, separating senders and recipients. Moreover, to due programmable features, SDN and ICN projects are architectures developed to flexibilize environments, mitigate traffic problems, deliver content through a scalable network structure, and yet avaiable a simple management. The premise of the SDN that contemplates the ICN besides decoupling, is the flexibility of the network configurations to reduce the overhead of the segments because of the retransmission of duplicate files by the same segment where they travel. Another important point is that contents provided do not give guarantees on the files integrity since they are routed through the same nodes several times pointing to biases. Based on this information, an architecture is designed to provide reliable content, that can be replicated in the network [16]. The proposed architecture aims to develop an ICN network, storing the information through a logical volume using private clouds, and that the stored content remains in a file system external to the network.

Internet of Things (IoT) applications carry on at an environment that is mainly highly dynamic and real time nature. Due that environment, such applications should be able to reason autonomously and give self-adaptive decisions. To date, there has not been an adequate architecture to incorporate self-adaptive property in that type of environment. Thus, we design a management architectural pattern for adaptation system in Internet of Things based on modeling of control loops. The architectural pattern is presented considering problem/motivation, solution, consequences and examples. An example of application of pattern is showed through a self-protecting architecture for Internet of Things.

The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor, we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.

Our investigation aims to answer which scenarios LXC, a lightweight virtualization solution, can offer a better performance than KVM, a hypervisor-based virtualization, or even equal to native environments. For that, we are considering HPC I/O bound applications and the effects of resource sharing on the performance of virtualized environments with both tools. We conducted experiments with traditional benchmarks in two different scenarios: without communication between benchmark processes in execution and; with processes communication in a cooperative way. Results indicate that LXC can offer a better performance for I/O-bound applications in most cases than KVM; and LXC is less affected while we increase the degree of resource sharing between multiple abstractions hosted at the same host server.

Despite of Cloud infrastructures can be used as High Performance Computing (HPC) platforms, many issues from virtualization overhead had kept them unrelated. However, with advent of container-based virtualizers, this scenario acquires new perspectives because this technique promises to decrease the virtualization overhead, achieving a near-native performance. In this work, we analyzed the performance of a container-based virtualization solution - Linux Container (LXC) - against a hyper visor-based virtualization solution - KVM - under HPC activities. For our experiments, we considered CPU and communication (network and inter-process communication), and results showed the virtualizer type can impact distinctly in performance according to resource used by application.

This paper presents the concept and preliminary tests in FPGA of architecture for a flexible multicore microcontroller. It is aimed to intermediate complexity embedded applications. A previous exact characterize of the microcontroller model and its target applications is a costly time task, and depends mostly on the engineers' and programmers' experiences. The proposed architecture can aid the development of new applications, by resources selection during the development of the application. We have designed a prototype in FPGA and it is working with seven CPUs.

High Performance Computing (HPC) aggregates computing power in order to solve large and complex problems in different knowledge areas. Nowadays, HPC users can utilize virtualized infrastructures as a low-cost alternative to deploy their applications. However, virtualization brings some challenges for HPC, specially in regard to overhead caused by hyper visors. In this work, our main goal is to analyze the performance of two hyper visors (KVM and Virtual Box) under HPC activities, considering full virtualization, and Para virtualization approaches. We used the HPC Challenge Benchmark (HPCC) to evaluate processor, RAM, inter-process communication and network communication performance. Our results show KVM in Para virtualization mode has a similar performance of a native cluster.

This paper presents an innovative and efficient approach to code compression. Our method reduces code size by up to 32.6% and 31.9% (including all extra costs) respectively, for ARM and MIPS processor, and presents an improvement of almost 7% over the traditional Huffman method. We performed simulations and analyzes, using the applications from benchmark MiBench. In spite of these experiments, our method is orthogonal to approaches that take into account the particularities of a given instruction set architecture, becoming an independent method for any specific architecture.

Parameters of cache performance may improve or worsen the performance of the all processing and of cache memory itself. Through simulation techniques using the SimpleScalar tool, which simulates the architectural characteristics, we simulate the ARM platform and we performed simulations changing the capacity and replacement methods of cache levels L1 and L2 separately. We observe the cache performance for hashing algorithms: Blake from SHA-3 candidates and traditional SHA-1. It was observed that Blake is better than the SHA-1, and that among the Blake options, the best are the Blake 384 and 512. So, Blake algorithm is better in terms of security, and efficiency of the cache and processor. We show that is clear, using miss rate and CPI (cycles per instruction).

This work shows a new architecture for a VLIW-based cryptoprocessor, which is implemented on FPGAs. The cryptoprocessor was designed to execute symmetric cryptography algorithms preferentially. To do so, special modules (such SBOX and PERBIT for substitution and permutation operations, respectively) were described in order to increase the performance and simplify the source program. The cryptoprocessor was described using VHDL language, and a prototype was synthesized and implemented in a FPGA Virtex generating occupation statistic data and temporary performance. It is important to note that the special modules which makes the cryptoprocessor different are not specific to a certain cryptography algorithm, and they were projected in order to be preconfigured according to the characteristics of the algorithm to be executed.