This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one misprediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint

This paper presents an improved two-pass hexagonal (TPA) algorithm constituted by linear hashtable motion estimation algorithm (LHMEA) and hexagonal search (HEXBS) for motion estimation. In the TPA, motion vectors (MV) are generated from the first-pass LHMEA and are used as predictors for second-pass HEXBS motion estimation, which only searches a small number of macroblocks (MBs). The hashtable structure of LHMEA is improved compared to the original TPA and LHMEA. The evaluation of the algorithm considers the three important metrics being processing time, compression rate and PSNR. The performance of the algorithm is evaluated by using standard video sequences and the results are compared to current algorithms.

This paper contributes to a dynamic branch predictor algorithm based on a perceptron in two directions: Firstly, a new block form of computation is introduced that reduces theoretically by half the combinational critical path for computing a prediction. Secondly, implementation in FPGA hardware is fully developed for quantitative comparison purposes. FPGA circuits for a one-cycle block predictor produces 1.7 faster clock rates than a direct implementation of the original perceptron predictor. This faster clock allows to realize predictions with longer history lengths for the same hardware budget.

We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align data flow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.

This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.

This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case.

The paper is concerned with the uniformization of a system of affine recurrence equations. This transformation is used in the design (or compilation) of highly parallel embedded systems (VLSI systolic arrays, signal processing filters, etc.). We present and implement an automatic system to achieve uniformization of systems of affine recurrence equations. We unify the results from many earlier papers, develop some theoretical extensions, and then propose effective uniformization algorithms. Our results can be used in any high level synthesis tool based on polyhedral representation of nested loop computations.

We have designed and constructed a genetic algorithm engine using a systolic design methodology. The approach has a number of advantages. Firstly the design processes is systematic. A C source code version of the algorithm is used as a starting point and progressively the code is re-written into a form from where systolic cells can be designed. Secondly the modular nature of the arrays allow easy expansion of the design for different requirements (larger populations in this example). Hardware designs are re-used extensively and, in combination with reconfigurable computing techniques, can be swapped in or out on an application specific basis to construct arrays of the correct size. This can also be extended to swapping in and out whole elements of the macro-pipeline so that alternative operators, such as Tournament Selection can be employed. Thirdly, a traditional benefit of systolic arrays applies. The resultant design is massively parallel and significant throughput can be achieved.

A methodology for partitioning and mapping of arbitrary uniform recurrence equations (UREs) expressed as computation graphs onto a given regular array is proposed. Deriving and based on a set of canonical dependencies together with two models of space projection, we give a general method of parallelization. The method has significant advantages in mapping an arbitrary computation graph onto a given processor array while preserving high efficiency in both communication and computation.>

A systolic array for the fast computation of the Faddeev algorithm is presented. Inversion of an n*n matrix on a systolic array is known to tend to 5 n inner product steps under the assumption that no data are duplicated. The proposed Faddeev array achieves matrix inversion in just 4 n steps with O(n/sup 2/) basic cells using careful duplications of some data. The array consists of two half-arrays which compute two separate but coupled triangularizations. The coupling is resolved by an on-the-fly decoupling process which duplicates pivot row data and passes them between the arrays using only nearest neighbor connections.>

An improved two layer systolic algorithm for computing the product of two n × n band matrices A and B with bandwidths w1 and w2 respectively is described. The array requires [equation: see PDF] basic inner product cells where [equation: see PDF] and [equation: see PDF] , and efficiency e = 1 and computation time [equation: see PDF] inner product steps and requires only a single pass of data through the design.

A systolic array for the solution of the assignment problem is presented. The algorithm requires O(n2) time and an orthogonally connected array of (n+2)*(n+2) cells consisting of simple adders and control logic. The design is area-efficient and incorporates the new concept of a Systolic Control Ring (SCR) to generate the necessary systolic wavefronts in any orientation within the design, while special cells are positioned only on the periphery of the design. The resulting Assignment Problem Iteration (API) is suitable for Wafer Scale integration using only single input and output for data permitting low bandwidth.

A templating method for the fast derivation of systolic arrays is presented and discussed in relation to differencing formulae and similar problems which generate tabular representations. Individual designs can be optimised and generate a full table in O(n) rather than the O(n2) operations (where n is the number of starting values). Finally the designs are incorporated into a single array i.e. the Unified Systolic Array for Differencing (USAD), which can be used as a cheap chip-based ‘add-on’ device to accelerate algorithms involving table generation and differencing.

A volume-efficient retimed hexagonal array for computing matrix product is described. The new array requires the same time as the well-known hex array of Kung and Leiserson but uses only half the hardware. The design is separated out on to two planar layers which communicate with each other only at the array boundaries, and requires the same number of input–output connections as the traditional array. Individual cells compute with an efficiency of e = 2/3.