Abstract Dynamical Ising machines are based on continuous dynamical systems evolving from a generic initial state to a state strongly related to the ground state of the classical Ising model on a graph. Reaching the ground state is equivalent to finding the maximum (weighted) cut of the graph, which presents the Ising machines as an alternative way to solving and investigating NP-complete problems. Among the dynamical models, relaxation-based models are distinguished by their relations with guarantees of performance achieved in time scaling polynomially with the problem size. However, the terminal states of such machines are essentially non-binary, necessitating special post-processing relying on disparate computing. We show that an Ising machine implementing a special continuous dynamical system (called the $$V_2$$ V 2 model) solves the rounding problem dynamically. We prove that the $$V_2$$ V 2 model, starting from an arbitrary non-binary state, terminates in a state that trivially rounds to a binary state with the cut at least as big as obtained by optimal rounding of the initial state. Besides showing that relaxation-based dynamical Ising machines can be made self-contained, this result presents a non-Boolean realization of solving a non-trivial information processing task on Ising machines. Moreover, we prove that if the initial state of the $$V_2$$ V 2 -machine is a random limited amplitude perturbation of a binary state, the machine progresses to a state with at least as high cut as that of the initial binary state. Since the probability of improving the cut is finite, this shows that the $$V_2$$ V 2 -machine with random agitations converges to a maximum cut state almost surely.

Determining the maximum cut of large graphs may require impractically long time, necessitating approximate algorithms and/or specialized computing platforms. A heuristic by Burer, Monteiro and Zhang for max-cut has not only been shown to be advantageous in many respects, but is also applicable to other NP-complete problems. From the perspective of accelerated computing, the heuristic's implementational challenge lies in its gradient-descent dynamics, which could be reduced to severalsinusoidalkernel operations applied to each edge of the graph. We had previously established the theoretical underpinnings of a relaxed dynamical heuristic for max-cut similar to the one proposed by Burer et al. but suited for accelerated computing on custom analog CMOS. In this work, we present the first fully custom analog integrated circuit implementing the dynamics of our heuristic on 130-nm CMOS technology. In an era of increasing specificity of computing machines, our algorithm-circuit co-design, originally for max-cut, introduces a versatile approach applicable to a diverse set of practical large-scale NP-complete problems.

This article addresses the problem of dynamic pinning synchronization of fuzzy-dependent-switched (Fds) coupled memristive neural networks (CMNNs) with mismatched dimensions on time scales. To begin with, the probabilistic coupling delays, time scales, mismatched dimensions, and function projective synchronization rules are considered to design the novel CMNNs to improve the reliability and generalization ability of the model. Then Fds rules and dynamic pinning control (DPC) method are adopted to design the CMNNs, which can effectively promote the information exchange between the switching signals and the fuzzy processes and can improve the utilization of the communication bandwidth between the nodes of CMNNs. Meanwhile, the method of constructing auxiliary state variables is adopted here to deal with the presented model, so that the coupled and isolated systems with different dimensions can realize information exchange and data sharing. This method also provides a solution for researchers by using low-dimensional systems to estimate or synchronize high-dimensional systems. Moreover, by means of Lyapunov–Krasovskii functional, auxiliary orthogonal matrix, and some inequality processing techniques, the conditions of modified function projective synchronization for Fds CMNNs are derived via the DPC on time scales. Finally, two numerical examples are provided to illustrate the effectiveness of the main results.

A well-known empirical rule for the demand of wireless communication systems is that of Edholm's law of bandwidth. It states that the demand for bandwidth in wireless short-range communications doubles every 18 months. With the growing demand for bandwidth and the decreasing cell size of wireless systems, terahertz (THz) communication systems are expected to become increasingly important in modern day applications. With this expectation comes the need for protecting users' privacy and security in the best way possible. With that in mind, we show that quantum key distribution can operate in the THz regime and we derive the relevant secret key rates against realistic collective attacks. In the extended THz range (from 0.1 to 50 THz), we find that below 1 THz, the main detrimental factor is thermal noise, while at higher frequencies it is atmospheric absorption. Our results show that high-rate THz quantum cryptography is possible over distances varying from a few meters using direct reconciliation, to about 220m via reverse reconciliation. We also give a specific example of the physical hardware and architecture that could be used to realize our THz quantum key distribution scheme.

The inception of spoof surface plasmon polariton (SSPP) mode realized in planar, patterned conductors to manage light beyond diffraction limit at a chosen frequency garnered significant attention of late. We show that, an SSPP channel can be chosen to act in two distinct ways: first, as a regular RC limited electrical interconnect at low frequencies; and second, as an exotic, beyond RC limit communication channel near its resonant frequency by binding the electromagnetic field on its surface to the elimination of capacitance C. A dynamic transformation between these two modes can constitute an energy economic, tera-scale inter-chip hybrid communication network. We have investigated theoretical limits on the information transfer capability of SSPP interconnects. We show that, a geometry dependent tradeoff relation between cross-talk limited bandwidth density and information traveling length emerges in SSPP-based communication networks. According to our analysis, a bandwidth density of 1 Gbps/μm is attainable in SSPP communication network with ~10-mm information transfer distance, where each channel can carry ~300-Gb/s information with nominal crosstalk.

In this paper, we propose an event-triggered hardware architecture for spiking neural networks with a weight-dependent spike-timing-dependent plasticity (STDP) learning algorithm. Several algorithm adaptations are made on the original learning algorithm in order to reduce the hardware complexity and to improve the energy efficiency of the hardware. In addition, an algorithm-hardware co-design approach is employed to boost the performance. Through leveraging the sparsity of spike trains and local storage units in the network, both the memory requirement of the algorithm and the clock cycles needed per learning iteration are significantly reduced. The proposed hardware architecture is implemented in a 65-nm technology. A three-layer neural network with a configuration of 256-50-10 is demonstrated. The designed chip can conduct inference on a down-sampled MNIST dataset with an energy consumption of 1.12 μJ/inference while achieving a recognition rate above 90%.

In this paper, we propose an online learning algorithm for supervised learning in multilayer spiking neural networks (SNNs). It is found that the spike timings of neurons in an SNN can be exploited to estimate the gradients that are associated with each synapse. With the proposed method of estimating gradients, learning similar to the stochastic gradient descent process employed in a conventional artificial neural network (ANN) can be achieved. In addition to the conventional layer-by-layer backpropagation, a one-pass direct backpropagation is possible using the proposed learning algorithm. Two neural networks, with one and two hidden layers, are employed as examples to demonstrate the effectiveness of the proposed learning algorithms. Several techniques for more effective learning are discussed, including utilizing a random refractory period to avoid saturation of spikes, employing a quantization noise injection technique and pseudorandom initial conditions to decorrelate spike timings, in addition to leveraging the progressive precision in an SNN to reduce the inference latency and energy. Extensive parametric simulations are conducted to examine the aforementioned techniques. The learning algorithm is developed with the considerations of ease of hardware implementation and relative compatibility with the classic ANN-based learning. Therefore, the proposed algorithm not only enjoys the high energy efficiency and good scalability of an SNN in its specialized hardware but also benefits from the well-developed theory and techniques of conventional ANN-based learning. The Modified National Institute of Standards and Technology database benchmark test is conducted to verify the newly proposed learning algorithm. Classification correct rates of 97.2% and 97.8% are achieved for the one-hidden-layer and two-hidden-layer neural networks, respectively. Moreover, a brief discussion of the hardware implementations is presented for two mainstream architectures.

In this work, we propose a hardware-friendly reinforcement learning algorithm. The learning algorithm is based on an actor-critic structure implemented with spiking neural networks (SNNs). A biologically plausible and hardware-friendly spike-timing-dependent plasticity learning rule is formulated and employed in the training of SNNs. Several important aspects of applying the learning rule in a reinforcement learning context is studied, especially from the circuit designers' point of view. Pitfalls of potential noise mixing and correlated spikes are identified and properly addressed. To feature a low-power learning architecture, techniques such as down-sampling data for certain learning blocks, injecting quantization noise as noisy residues in neurons, and proper memory partitioning are proposed. A 1-D state-value function learning problem and a 2-D maze walking problem are examined in this paper to illustrate effectiveness of the proposed algorithm and learning rules. A low-power hardware architecture is proposed and examples are implemented with Verilog. Hardware complexity of the proposed algorithm is analyzed, and potential solutions to breaking memory bottleneck when the size of the problem gets large is also discussed.

Cellular nonlinear/neural network (CNN) has been recognized as a powerful massively parallel architecture capable of solving complex engineering problems by performing trillions of analog operations per second. The memristor was theoretically predicted in the late seventies, but it garnered nascent research interest due to the recent much-acclaimed discovery of nanocrossbar memories by engineers at the Hewlett-Packard Laboratory. The memristor is expected to be co-integrated with nanoscale CMOS technology to revolutionize conventional von Neumann as well as neuromorphic computing. In this paper, a compact CNN model based on memristors is presented along with its performance analysis and applications. In the new CNN design, the memristor bridge circuit acts as the synaptic circuit element and substitutes the complex multiplication circuit used in traditional CNN architectures. In addition, the negative differential resistance and nonlinear current-voltage characteristics of the memristor have been leveraged to replace the linear resistor in conventional CNNs. The proposed CNN design has several merits, for example, high density, nonvolatility, and programmability of synaptic weights. The proposed memristor-based CNN design operations for implementing several image processing functions are illustrated through simulation and contrasted with conventional CNNs. Monte-Carlo simulation has been used to demonstrate the behavior of the proposed CNN due to the variations in memristor synaptic weights.

In this paper, a detailed methodology for designing a low-power high-efficiency power amplifier (PA) is presented. The trade-off between high efficiency and low output power is highlighted. An example is described to validate the proposed design method. Simulated peak efficiency up to 50.3% has been achieved with all components on-chip. Furthermore, a tunable power amplifier with efficiency enhanced at output power back-off region is proposed for more efficient operation.

Asynchronous approach for digital systems is a way to resolve increased timing uncertainty with technology scaling since timing issue is eliminated in asynchronous systems. This paper presents a sub-threshold operating asynchronous 8051 microcontroller (A8051) with a novel 16T SRAM cell for improved reliability in asynchronous systems. This A8051, adopting a 4-phase dual-rail protocol, can operate up to 250 mV. A8051 has 67.53 μs as a critical path delay with 91.6 nW power consumption at 250 mV, which is equivalent to 12.88 kHz in synchronous systems. At 1.0 V, the delay of a critical path of A8051 microcontroller is 5.74 ns, which is equivalent to 151.55 MHz, with 8.98 mW power consumption. The proposed 16T SRAM cell is applied in memory blocks. The 16T SRAM structure eliminates charge contentions between devices during read and write operations so that SRAM can be operated fully in static mode, bringing about improved write margin (WM). The WM of this 16T SRAM cell is 1.81 times greater than the conventional 6T SRAM cell and 1.58 times better than 8T SRAM cell. At 250 mV, the SNM of SRAM cell is 12.5 mV under process and mismatch variations. Write delay of the asynchronous SRAM block is 4.02 μs (equivalent to 248.5 kHz) with 5.44 pJ energy dissipation, while read delay is 12.61 μs (equivalent to 79.3 kHz) with 9.08 pJ energy dissipation.

The article introduces a novel approach to color image processing that utilizes multi-peak resonant tunneling diodes for encoding color information in quantized states of the diodes. The Multi-Peak Resonant Tunneling Diodes (MPRTDs) are organized as a two-dimensional array of vertical pillars which are locally connected by programmable passive and active elements with a view to realizing a wide variety of color image processing functions such as quantization, color extraction, image smoothing, edge detection, and line detection. In order to process color information in the input images, two different methods for color representation schemes have been used: one using color mapping and the other using direct RGB representation. Finally, the article uses HSPICE simulation methods for the nestlist of the proposed RTD-based nanoarchitecture in order to verify a candidate of image functions by using the afore-mentioned representation methods.

Multiferroic single-domain nanomagnetics is a promising emerging nanotechnology poised to usher in ultralow energy nanomagnetic nonvolatile logic circuits in numerous medical applications, such as implants and prosthesis, where battery longevity is paramount. This paper evaluates the fundamental mode of signal propagation over ferromagnetically and antiferromagnetically coupled wires and interaction between the magnetic nanoparticles to perform nonvolatile logic functions, such the majority gate that sets its output to 1 when the majority of the inputs is 1. By taking advantage of magnetic nonvolatility, the paper demonstrates nanopipelining signal processing, data propagation performance, and functionality of basic building blocks. Our results indicate that effective nanopipeling can be achieved with clock periods approaching 9 ns and energy dissipation of 20 aJ per nanomagnet switch with the device sizes considered.

Most hardware neural networks have a basic competitive learning rule on top of a more involved processing algorithm. This work highlights two basic learning rules/behavior: winner-take-all (WTA) and spike-timing-dependent plasticity (STDP). It also gives a design example implementing WTA combined with STDP in a position detector. A complementary metal-oxide-semiconductor (CMOS) and a memristor-MOS technology (MMOST) design simulation results are compared on the bases of power, area, and noise handling capabilities. Design and layout were done in 130-nm IBM process for CMOS, and the HSPICE model files for the process were used to simulate the CMOS part of the MMOST design. CMOS consumes area, 55-W max power, and requires a 3-dB SNR. On the other hand, the MMOST design consumes , 15-W max power, and requires a 4.8-dB SNR. There is a potential to improve upon analog computing with the adoption of MMOST designs.

IT is with great pleasure that we introduce this special section on Chips and Architectures for Emerging Technologies and Applications to the audience of the IEEE Transactions on Computers. We are currently witnessing a technology advancement which is making the gap between the present and future much narrower than it has ever been. The purpose of this special section is to showcase highly innovative, creative, and futuristic chip architectures and functionalities that can range from new paradigms in reconfigurable systems architectures, to adaptive, organic, ubiquitous, and biologically inspired computing, to new classes of chip implants, or any other highly innovative human-to-computer interface. This special section includes two papers, which we hope will offer an interesting perspective on the challenges involved in designing integrated circuits and architectures that leverage the capabilities of emerging technologies in novel applications. The first paper, ‘‘Exploring the Potential of Threshold Logic for Cryptography-Related Operations,’’ by Alessandro Cilardo, investigates the application of a non-Boolean computational paradigm to cryptographic applications. More specifically, the author demonstrates the power of linear Threshold Logic functions, which are enabled by new technologies such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), towards performing fundamental cryptographic operations. An architecture for implementing such operations, namely a Montgomery modular reduction and multiplication, is also introduced and its intrinsic superiority to traditional Boolean computational models in demonstrated. The second paper, ‘‘3D Integration of CMOL Structures for FPGA Applications,’’ by Z. Abid, Ming Liu, and Wei Wang, introduces a combination of hybrid CMOS/ nanoelectronic (CMOL) circuits and 3D integration, in order to develop a 3D CMOL technology with particular emphasis on designing Field-Programmable Gate-Array (FPGA) chips. The authors discuss the architecture, 3D integration, defect tolerance and performance aspects of this technology, as well as its breakthrough potential for developing the next generation of FPGAs. We would like to thank the previous editor-in-chief of the IEEE Transactions on Computers, Dr. Fabrizio Lombardi, for suggesting that we organize this special section, the current editor-in-chief Dr. Albert Y. Zomaya, for hosting this section, and all of the editorial staff for the support in the making of the issue. Additionally, we would like to thank the authors of the submitted papers and the numerous reviewers whose contributions made this special section possible.

This paper presents an accurate interconnect thermal model for analyzing the temperature distribution of an on-chip interconnect wire. The model addresses the ambient temperatures and the heat transfer rates of the packaging materials. Particularly, the model considers the effect of the interconnect temperature gradients. The paper employs an equivalent transmission line circuit to obtain the temperature distribution solution from the model. Then an O (n) algorithm is introduced to compute the interconnect temperatures. Experimental results demonstrate the accuracy of the thermal model, by comparisons with the computational fluid dynamics tool FLUENT.

Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 22 nm nodes. During the post-shrinking era, a slew of mesoscopic and nanoscale technologies such as quantum tunneling devices, plasmon based transistors, ionic transport based crossbar structures, nanomagnetic logic, grapheme FET's, self-assembled array of quantum dots, and molecular devices are likely to emerge as commercially viable technologies in order to sustain the demands for exponential economic growth throughout the first quarter of the 21st Century.

The resonant tunneling diode (RTD) has found numerous applications in high-speed digital and analog circuits due to the key advantages associated with its folded back negative differential resistance (NDR) current-voltage (I-V) characteristics as well as its extremely small switching capacitance. Recently, the RTD has also been employed to implement high-speed and compact cellular neural/nonlinear networks (CNNs) by exploiting its quantum tunneling induced nonlinearity and symmetrical I-V characteristics for both positive and negative voltages applied across the anode and cathode terminals of the RTD. This paper proposes an RTD-based CNN architecture and investigates its operation through driving-point-plot analysis, stability and settling time study, and circuit simulation. Full-array simulation of a 128 times 128 RTD-based CNN for several image processing functions is performed using the Quantum Spice simulator designed at the University of Michigan, where the RTD is represented in SPICE simulator by a physics based model derived by solving Schrodinger's and Poisson's equations self-consistently. A comparative study between different CNN implementations reveals that the RTD-based CNN can be designed superior to conventional CMOS technologies in terms of integration density, operating speed, and functionality.

Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This paper presents an efficient thermal-analysis method of O(NlgN) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green's function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green's function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmission-line theory, fully analytical and explicit formulas are derived in this paper for the multilayer Green's function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green's function-based thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure

This paper proposes an efficient numerical technique, called the finite difference quadrature (FDQ) method, to model the transmission line with radiated electromagnetic (EM) wave noise coupling. A discrete modeling approach, the FDQ method adapts coarse grid points along the transmission line to compute the finite difference between adjacent grid points. A global approximation scheme is formulated in the form of a weighted sum of quantities beyond the local grid points. Unlike the Gaussian quadrature method that computes numerical integrals by using global approximation framework, the FDQ method uses a global quadrature method to construct the approximation schemes for the computation of, however, numerical finite differences. As a global approximation technique, the FDQ method has superior numerical dispersion to the finite difference (FD) method, and, therefore, needs much sparser grid points than the FD method to achieve comparable accuracy. Equivalent voltage and current sources are derived, exciting the transmission line at the grid points. Equivalent circuit models are consequently derived to represent the transmission line subject to radiated electromagnetic wave noise. The FDQ-based equivalent models can be integrated into a simulator like SPICE.

This paper describes the implementation of a 256-state, rate 14, soft-decision Viterbi decodel: The implementation explores several variables and design considerations of a Viterbi decodel; testing various methods for low power and throughput capability. By designing the Viterbi decoder using three techniques, a progressive active ACS (Add- Compare-Select), prediction matchel; and reduced read traceback, we take the most efJicient techniques and apply them iteratively to the overall design to achieve 12.7 % of dynamic power consumption with 250Mbps of throughput.

On optimizing circuit trajectories, i.e. continuous paths of circuit parameters, the paper presents an auxiliary network approach, which utilizes Pontryagin's minimum principle. Based on a set of circuit element correspondence rules, the introduced approach establishes an auxiliary network for a given circuit to be optimized, and then circuit trajectories are optimized in a process of simulating the given circuit and the auxiliary network. The auxiliary network approach facilitates establishing analytic models in designing high-performance circuits that require fine tuning circuit trajectories. The paper details the theoretical framework of auxiliary network, and provides practical examples of its application in adiabatic circuit design.

This paper derives the multi-layer heat conduction Green’s function, by integrating the eigen-expansion technique and the classic transmission line theories, and presents a logarithmic full-chip thermal analysis algorithm, which is verified by comparisons with a computational fluid dynamics tool (FLUENT). The paper considers Dirichlet’s and general heat convection boundary conditions at chip surfaces. Experimental results show that the algorithm offers superior computing speed, compared to FLUENT and traditional Green’s function based methods. The paper also studies the limitations of the traditional single-layer thermal model.

This paper presents a new mathematical approach to modeling EM wave coupling noise so that it can be easily integrated into chip-level noise analysis tools. The new method employs Chebyshev approximation technique to model the distributed sources arising in the Telegrapher's equations due to EM wave coupling. A uniform plane wave illumination metric is provided to determine the order of approximation. Closed-form formulas for the noise transfer functions' moments are derived. By utilizing the formulated moments, reduced order models can be efficiently obtained to generate the induced noise caused by EM wave illumination. The accuracy of the proposed method is verified by Hspice simulation.

Dynamic CMOS logic circuits are widely employed in high performance VLSI chips in pursuing very high system performance. However, dynamic circuits are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI systems. In this paper, we present a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained.

This paper proposes an efficient numerical approximation technique, called the Finite Difference Quadrature (FDQ) Method, which has been adapted to model transmission lines (TL's) with external EM wave coupling. The finite difference quadrature method can quickly compute finite differences between adjacent grid points by estimating a weighted linear sum of derivatives at a set of points belonging to the domain. Unlike the Gaussian Quadrature method to compute the numerical integral, FDQ method uses global quadrature method to construct the approximation framework, however, to compute the finite difference. A discrete modeling approach, FDQ needs much sparser grid points than the Finite Difference (FD) methods to achieve comparable accuracy. The FDQ modeling technique is successfully employed to efficiently simulate transmission lines with EM interference.

The principle of adiabatic switching in conventional energy-recovery adiabatic circuit is generally explained with the help of a rudimentary RC circuit being driven by a constant current source. However, it is not strictly accurate to approximate a MOS adiabatic circuit by such an elementary model owing to its failure to incorporate the nonlinearity of very deep sub-micron transistors. This paper employs the theory of variational calculus in order to extend the principle of optimality used in this RC model to general MOS adiabatic circuits. Our experimental results include energy dissipation comparison in various adiabatic schemes using optimal power clocking versus other waveforms.

The principle of adiabatic switching in conventional energy-recovery adiabatic circuit is generally explained with the help of a rudimentary RC circuit being driven by a constant current source. However, it is not strictly accurate to approximate a MOS adiabatic circuit by such an elementary model owing to its failure to incorporate the nonlinearity of very deep sub-micron transistors. This paper employs the theory of variational calculus in order to extend the principle of optimality used in this RC model to general MOS adiabatic circuits. Our experimental results include energy dissipation comparison in various adiabatic schemes using optimal power clocking versus other waveforms.

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.

In this paper, we propose an accurate and fast method to estimate the crosstalk noise in the presence of multiple aggressor nets for use in physical design automation tools. Since noise estimation is often part of the inner loop of optimization algorithms, very efficient closed-form solutions are needed. Previous approaches model aggressor nets one at a time, assuming that the coupling capacitance to all quiet aggressor nets are grounded. They also model the load from interconnect branches as a lumped capacitor, the value of which is the sum of interconnect and load capacitances of the branch. Finally, previous works typically use simple lumped 2-4-node circuit templates and employ a so-called dominant pole approximation to solve the template circuit. While these approximations allow for very fast analysis, they may result in significant underestimation of the noise. In this paper, we propose a new and more comprehensive fast noise estimation method. We propose a novel reduction technique for modeling quiet aggressor nets based on the concept of coupling point admittance. We also propose a reduction method to replace tree branches with effective capacitors which models the effect of resistive shielding. Furthermore, we model the simplified single aggressor net crosstalk noise problem using a 6-node template circuit and propose a new double pole approach to solve the template circuit. We have tested the proposed method on noise-prone interconnects from an industrial high-performance processor. Our results show a worst case error of 7.8% and an average error of 2.7%, while allowing for very fast analysis.

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and /spl alpha/-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.

This paper introduces an efficient and passive discrete modeling technique for estimating signal propagation delays through on-chip long interconnects that are represented as distributed RLC transmission lines. The proposed delay model is based on a less frequently used numerical approximation technique, called the differential quadrature method (DQM). The DQM can compute the partial derivative of a function at any arbitrary point located within a prespecified closed domain of the function by quickly estimating the weighted linear sum of values of the function at a relatively small set of well-chosen grid points within the domain. By using the fifth-order DQM, a new approximation framework is constructed in this paper for discretizing the distributed RLC interconnect and thereafter modeling its delay. Due to high efficiency of DQM approximation, the proposed framework requires only few grid points to achieve good accuracy. The presented equivalent-circuit model appears like the ones derived by the finite difference (FD) method. However, it has higher accuracy and less internal nodes than generated by the FD-based modeling. The fifth-order DQM modeling technique is shown to preserve passivity. It has linear forms that are compatible with the passive order-reduction algorithm for linear network. Numerical experiments show that the proposed modeling approach leads to high accuracy as well as high efficiency.

Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in high-performance circuit design with a view to minimizing the delay of a FET network. Currently, in a long series-connected FET chain, the dimensions of the transistors are decreased from bottom transistor to the top transistor in a manner where the width of transistors is tapered linearly or exponentially. However, it has not been mathematically proved whether either of these tapering schemes yields optimal results in terms of minimization of switching delays of the network. In this paper, we rigorously analyze MOS circuits consisting of long FET chains under the widely used Elmore delay model and derive the optimality of transistor tapering by employing variational calculus. Specifically, we demonstrate that neither linear nor exponential tapering alone minimizes the discharge time of the FET chain. Instead, a composition of exponential and constant tapering actually optimizes the delay of the network. We have also corroborated our analytical results by performing extensive simulation of FET networks and showing that both analytical and simulation results are always consistent.

In this paper, we study the simultaneous switching noise problem by using an application-specific modeling method. A simple yet accurate MOSFET model is proposed in order to derive closed-form formulas for simultaneous switching noise voltage waveforms. We first derive a simple formula assuming that the inductances are the only parasitics. Through HSPICE simulation, we show that the new formula is more accurate than previous results based on the same assumption. We then study the effect of the parasitic capacitances of ground bonding wires and pads. We show that the maximum simultaneous switching noise should be calculated using four different formulas depending on the value of the parasitic capacitances and the slope of the input signal. The proposed formulas, modeling both parasitic inductances and capacitances, are within 3% of HSPICE simulation results.

This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximation technique, the efficient frameworks are constructed to transform the frequency-domain Telegrapher's equations into compact linear algebraic equations. The dominant poles and residues can be extracted by directly solving the linear equations. The closed-form formulas are derived to compute the low-order dominant poles. Due to high accuracy of the global approximation, the extracted poles can accurately represent the exact admittance matrices in a wide frequency range. By using the recursive convolution technique, the pole-residue models can be represented by companion models, which have linear complexity with respect to the computational time. The presented modeling approaches are shown to preserve passivity. Numerical experiments of transient simulation show that the presented modeling approaches lead to higher efficiency, while maintaining; comparable accuracy.

The high-order compact finite difference (HCFD) method is adapted for interconnect modeling. Based on the compact finite difference method, the HCFD method employs the Chebyshev polynomials to construct the approximation framework for interconnect discretization, and leads to improved equivalent-circuit models. The HCFD-based modeling requires far fewer intervening grid points for building an accurate discrete model of the transmission line than other numerical methods like traditional Finite Difference (FD) method. It is believed that given the number of state variables, the presented method gives more accurate results than other known passive discrete modeling methods. The theoretical proof shows that HCFD-based modeling preserves the passivity.

This paper describes a fast method to estimate crosstalk noise in the presence of multiple aggressor nets for use in physical design automation tools. Since noise estimation is often part of the inner-loop of optimization algorithms, very efficient closed-form solutions are needed. Previous approaches have typically used simple lumped 3-4 node circuit templates. One aggressor net is modeled at a time assuming that the coupling capacitances to all quiet aggressor nets are grounded. They also model the load from interconnect branches as a lumped capacitor and use a dominant pole approximation to solve the template circuit. While these approximations allow for very fast analysis, they result in significant underestimation of the noise. In this paper, we propose a new and more comprehensive fast noise estimation model. We use a 6 node template circuit and propose a novel reduction technique for modeling quiet aggressor nets based on the concept of coupling point admittance. We also propose a reduction method to replace tree branches with effective capacitors which models the effect of resistive shielding. Finally, we propose a new double pole approach to solve the template circuit. We tested the proposed method on noise-prone interconnects from an industrial high performance processor. Our results show a worst-case error of 7.8% and an average error of 2.7%, while allowing for very fast analysis.

This paper introduces a new transmission line modeling approach that employs an efficient numerical approximation technique called the differential quadrature method (DQM). The transmission line has been discretized and the approximation framework is constructed by using the fifth order differential quadrature method; consequently an improved discrete equivalent-circuit model is developed in the paper. The DQM-based modeling requires far fewer intervening grid points for building an accurate discrete model of the transmission line than numerical methods like FD requires. It introduces far less state variables than FD-based models; therefore, it has higher efficiency. The DQM technique can be integrated in a circuit simulator since it preserves the passivity.

This paper describes the incorporation of an accurate physics-based model of the resonant tunneling diode (RTD) into Berkeley SPICE version 3F5 and addresses the related direct current (dc) and transient convergence problems caused by the negative differential resistance (NDR) and the exponential nature of the device characteristics. To circumvent the de convergence problems, a new continuation technique using artificial parameter embedding and a current limiting algorithm are proposed. The studies made in this paper have shown that these techniques are superior to the in-built continuation methods of SPICE, such as Gmin-stepping and Source-stepping, for a large number of circuits of varying sizes. To improve transient convergence performance, the following three algorithms are added to SPICE: a modified forced-convergence algorithm, a new time-step adjustment algorithm, and a modified device voltage prediction algorithm.

In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

In this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit.

A novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented.

Resonant tunnelling diode based logic circuits offer significant advantages for low power, ultra-high-speed applications. In this work, a low-power resonant interband tunneling diode (RITD)-based logic technology capable of operating at clock rates of at least 12 GHz is reported. The circuits are fabricated using InAs/AlSb/GaSb RITDs. Fanout of at least two at a clock rate of 10 GHz is also reported for two AND gates in a two-stage pipelined configuration. Simulation results for an RITD/HFET circuit based on measured characteristics of InAs/AlSb/GaSb RITDs and InAs-channel HFETs for a simple inverting Schmitt trigger are presented to demonstrate the advantages of an integrated RITD/HFET technology. This circuit architecture demonstrates proper operation with power supply voltages as low as 0.5 V. In addition, well defined logic levels and abrupt logic transitions are achieved, despite the limited transconductance and large output conductance typical of InAs-channel HFETs.

A novel quantum-MOS sense amplifier circuit consisting of resonant tunneling diodes (RTDs) as pull-up devices and NMOS transistors is discussed in this paper. Compared to the conventional sense amplifier circuits using CMOS technology, the proposed QMOS sense amplifier exhibits about 20% higher sensing speed. The cross-coupled QMOS latch, which is at the heart of the sense amplifier circuit, has metastable and unstable states which are closely related to the I-V characteristics of the RTDs. The stability analysis has been made by using phase-plot diagram and determining how RTD parameters relate to circuit speed. Robustness of the sense amplifier has been discussed.

Threshold gates consisting of RTDs in conjunction, with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and power dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.

Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates.

The resonant tunneling diode (RTD) has been widely studied because of its importance in the field of nanoelectronic science and technology and its potential applications in very high speed/functionality devices and circuits. Even though much progress has been made in this regard, additional work is needed to realize the full potential of RTD's. As research on RTD's continues, we will try in this tutorial review to provide the reader with an overall and succinct picture of where we stand in this exciting field or research and to address the following questions: What makes RTD's so attractive? To what extent can RTD's be modeled for design purposes? What are the required and achievable device properties in terms of digital logic applications? To address these issues, we review the device operational principles, various modeling approaches, and major device properties. Comparisons among the various RTD physical models and major features of RTD's, resonant interband tunneling diodes, and Esaki tunnel diodes are presented. The tutorial and analysis provided in this paper may help the reader in becoming familiar with current research efforts, as well as to examine the important aspects in further RTD developments and their circuit applications.

The paper describes a signed digit full adder (SDFA) circuit consisting of resonant tunneling diodes (RTDs) and metal oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple valued logic literal circuit that utilizes the folded back I-V (or negative differential resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state of the art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs based RTDs connected externally to the MOSFET circuit.

This paper presents a new, layout-based approach to board-level shorts diagnosis for bussed drivers, with the goal of early repair of interconnect shorts so as to minimize (a) fault masking during opens testing and (b) driver abuse. This approach leads to an early diagnosis of more than 96% of shorts and simplifies the subsequent rest for opens considerably. Besides, this approach improves the production yield and field survivability of boards.

This paper lays foundations for an approach to on-chip row/column allocation that exploits certain properties offered by laterally connected networks of simple threshold devices. As a sample application, it is demonstrated how electronic implementations of these networks can be used as the basis for effective memory array repair systems that require little hardware overhead.

Quantum electronic devices such as resonant tunneling diodes and transistors are now beginning to be used in ultrafast and compact circuit designs. These devices exhibit negative differential resistance (NDR) and/or negative transconductance in their I-V characteristics and have active dimensions of a few nanometers. Since the conventional drift-diffusion approximation is not valid for simulation of device behavior at this microscopic scale, quantum simulation models based on the Schrodinger equation are required to accurately predict the behavior of the device. However, these models are too slow for circuit simulation. This paper describes a modeling scheme that maintains the accuracy of the quantum simulation while achieving satisfactory speed for circuit simulation, and is applicable to a wide range of two and three terminal resonant tunneling devices and may also be extended to future scaled-down MOS and bipolar devices. A self-consistent solution of the Poisson and the Schrodinger equations for various bias points is used to build up tables of conductances, capacitances and other parameters. Table-lookup methods are then used during circuit simulation. Convergence techniques have been developed to overcome the problems caused by the NDR characteristics and the lookup-table model in simulation. While implementation details are presented for a resonant tunneling transistor (RTT), models for several other quantum electronic devices have also been implemented in NDR-SPICE.>

Most current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The author presents a systematic study of soft-error related problems and discusses methodologies for correcting single-bit and double-bit memory-cell upsets by using on-chip error-correcting-code (ECC) circuits. By modifying the product code, an effective coding scheme has been designed that can be integrated within a DRAM chip to correct double-bit errors. It is demonstrated that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead are calculated and compared with those of memory chips without any ECC and chips with single-error-correcting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiple-bit errors is analyzed.>

It is shown how to represent the objective function of the memory repair problem as a neural-network energy function, and how to exploit the neural network's convergence property for deriving optimal repair solutions. Two algorithms have been developed using a neural network, and their performances are compared with that of the repair most (RM) algorithm. For randomly generated defect patterns, a proposed algorithm with a hill-climbing capability successfully repaired memory arrays in 98% cases, as opposed to RMs 20% cases. It is demonstrated how, by using very small silicon overhead, one can implement this algorithm in hardware within a VLSI chip for built in self repair (BISR) of memory arrays. The proposed auto-repair approach is shown to improve the VLSI chip yield by a significant factor, and it can also improve the life span of the chip by automatically restructuring its memory arrays in the event of sporadic cell failures during the field use.>

The authors introduce two types of neural networks that can be integrated into array-type very-large-scale integration/wafer-scale integration (VLSI/WSI) chips, allowing them to restructure themselves automatically so that, in the presence of multiple random faults, the array circuits can perform their computations correctly. In the first implementation, the neural network is interconnected and programmed so that it can execute a maximum matching algorithm and thereby substitute appropriate fault-free spare elements for the faulty components. The second implementation rearranges the surviving fault-free processors to restore the logical structure, and it can adjust its interconnection complexity based on the quality of solution (i.e., performance) desired. These two approaches are compared with the traditional reconfiguration algorithms, and by simulation it is shown that the neural network techniques provide superior performance (i.e., higher survivability rates). It is also shown that the intrinsic fault-tolerant nature of neural networks provides a degradable reconfiguration control even in the presence of faulty neural network components.>

The authors point out that a typical computer-aided design environment consists of a number of workstations connected together by a high-speed local area network. A placement program that makes use of this distributed computing environment to achieve linear speedup without sacrificing the quality of the results obtained by the serial version of the program is presented. The placement program is based on the genetic algorithm, which is a heuristic search method inspired by biological evolution models. The parallel implementation has other desirable features such as the ability to operate in a heterogeneous network environment and dynamic and static load balancing. The implementation of the placement program and detailed experimental studies of the behavior of the algorithm with various parameter settings, network capabilities, and communication patterns are described.>

Gallium arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of gallium arsenide high electron mobility transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All defects and errors are mapped into equivalent circuit modifications and the resulting circuits are analyzed and simulated to observe the fault effects. Certain complex pattern-sensitive faults described in the testing literature are not observed at all, while certain other faults which have not been previously studied, are observed. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAMs can be tested.>

The authors present the issues involved in the design of a special-purpose processing array system, called HAM, which accelerates computationally intensive wire routing tasks. It is especially suited for double-sided surface-mounted boards, which require complex three-dimensional search operations over multiple wiring planes. The novel features of the design include a hexagonal interconnection scheme to improve workload distributions during multilayer concurrent search operations and the VLSI custom design of the processors. Particular emphasis has been placed on the demands of maze routing. A cell-address propagation scheme, which is quite different from the traditional grid-coordinate approach, is discussed. It provides rapid lookup of pertinent routing information and can be extended to any distributed memory multiprocessor system. A global pipelining scheme of cell updates and expands is discussed. Experimental results are presented relating the speedup to various criteria for two different modes of parallel wave propagation.>

As VLSI chips are integrating multimillion transistors, a large number of subcircuits such as memory and logic arrays are becoming inaccessible for external testing, diagnosis and self-repair. In the past, several researchers proposed highly efficient constant-time testable algorithms for iterative logic arrays of square and hexagonal topologies. Such test procedures can be generated internally within VLSI chips using very little extra chip area to test embedded arithmetic and logic arrays, and thereby bad chips can be automatically eliminated on the production line. Even though the BIST hardware improves the chip reliability and production quality control, the problem of achieving high production yield for high-density VLSI chips remains an elusive goal to semiconductor manufacturers. This research explores the concept of built-in self-repair as a natural extension to built-in self-test techniques for yield and circuit life-time (chip survivability) improvement. A novel redundant interconnection. design for hexagonal arrays, which incorporates additional communication paths and spare processor elements, is proposed.

A host-driven reconfiguration scheme, called HEX-REPAIR, is proposed for hexagonal processor arrays characterized by a large number of relatively simple cells. Such arrays have been shown to be the most efficient for many digital signal processing applications, such as matrix multiplication, and for some classes of filtering operations. Reconfiguration for these arrays is made difficult by the asymmetric nature of the interconnection network and the need for keeping the switching overheads at a minimum. The algorithm presented meets these requirements. In addition, it has excellent fault-coverage characteristics, even in the presence of multiple faults, and can accommodate multiple rows/columns of spare cells. The restructured array is transparent to users and no modification is required in any application program using the array.>

Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.

The feasibility of implementing electronic neural networks as intelligent hardware for memory array repair is demonstrated. In particular, it is shown that the neural network control possesses a robust and degradable computing capability under various fault conditions. A yield analysis performed on 64K DRAMs shows that the yield can be improved from as low as 20% to near 99% owing to the self-repair design, with an overhead of no more than 7%. Simulation shows that the neural net algorithms are superior to the Repair Most algorithm.>

The genetic algorithm applies transformations on the chromosonal representation of the physical layout. The algorithm works on a set of configurations constituting a constant-size population. The transformations are performed through crossover operators that generate a new configuration assimilating the characteristics of a pair of configurations existing in the current population. Mutation and inversion operators are also used to increase the diversity of the population, and to avoid premature convergence at local optima. Due to the simultaneous optimization of a large population of configurations, there is a logical concurrency in the search of the solution space which makes the genetic algorithm an extremely efficient optimizer. Three efficient crossover techniques are compared, and the algorithm parameters are optimized for the cell-placement problem by using a meta-genetic process. The resulting algorithm was tested against TimberWolf 3.3 on five industrial circuits consisting of 100-800 cells. The results indicate that a placement comparable in quality can be obtained in about the same execution time as TimberWolf, but the genetic algorithm needs to explore 20-50 times fewer configurations than does TimberWolf.>

A novel hardware accelerator comprised of several fast processors interconnected in the form of a hexagonal mesh with wraparound connections is proposed. The novelty of the proposed architecture stems from the fact that it is suitable not only for single-layer routing, but also for routing in parallel on multiple layers. A hexagonal machine of dimension square root kG, with about 3kG processors, can handle a k-layer grid consisting of kG/sup 2/ grid points at about the same speed as a full-grid machine with kG/sup 2/ processors. A technique for measuring the performance of a hardware accelerator in terms of the average delay incurred over a full-grid machine is suggested. This has been formalized in the case of the hexagonal architecture, and is presented for various nets and mesh dimensions. The results have been accurately verified by extensive simulation done in C++ language. It is demonstrated that the hexagonal mesh, by virtue of its additional links for expansion, is resilient to about 10% of failure in the links and processing elements. A detailed design for a chip implementation of the hexagonal machine is discussed.>

A neural network model is proposed for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the C.M. Fiduccia and R.M. Mattheyses (1982) algorithm. The proposed approach can be implemented in hardware to accelerate time-consuming partitioning procedures.>

This paper proposes a neural network model for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of a circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with that achieved by Fiduccia and Mattheyses algorithm.

The authors investigate a C-wrapped hexagonal mesh architecture (called HAM, for hexagonal array machine) for the physical implementation of the Lee algorithm. They show the high promise of such a machine in handling routing on single as well as on multiple layers. The mapping corresponding to a C-wrapped hexagonal interconnection of N processing elements (PEs) results in an interprocessor cycle length of N. This is much superior to the N/2 results obtained by other researchers. Consequently, fewer conflicts arise during wave-front expansion and a good quality routing can be achieved in a much shorter period. The authors show that a hexagonal mesh with 3 kG PEs can do routing on k-layer grids with kG/sup 2/ grid points at speeds comparable to the full grid machine.>

A design strategy is presented for efficient and comprehensive parallel testing of high-density, MOS random-access memories (RAMs). Parallel test algorithms for RAMs have been developed on the basis of this design-for-testability approach for a broad class of pattern-sensitive faults. Two algorithms which are significantly more efficient than previous approaches are examined. The first algorithm detects the static and dynamic pattern-sensitive faults over a neighborhood of five cells. The second algorithm tests the symmetric pattern-sensitive faults over a neighborhood of nine cells. It tests an n-bit RAM organized as a square root n* square root n array in 97 square root n memory cycles. The design-for-testability approach modifies the existing RAM architecture very little, so that it can be implemented very easily. The additional overhead is only about 2 square root n transistors. The low overhead allows high reliability, and the additional circuit for each bit line can fit within the 3 lambda -to-6 lambda pitch width in a high-density, single-transistor dynamic RAM. Although the algorithm is designed to detect pattern-sensitive faults, the modified architecture can be readily used to speed up other conventional algorithms of linear complexity by a factor of O( square root n).>

An error-correcting code is described which can correct up to two soft errors on each work line within a DRAM (dynamic random-access memory) chip. Three dimensional DRAM chips with trench-type capacitors are vulnerable to double-bit soft errors when an alpha particle strikes at the intervening space between two vertical capacitors setting off a plasma discharge between them. The author presents a systematic study of soft-error related problems, and discusses the methodologies to correct the double-bit memory-cells upsets by using on-chip ECC (error-correcting code) circuits. A comprehensive study is made to estimate the improvement in soft-error rate (SER) and mean time between failure (MTBF) by the proposed ECC technique. The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed using combinational enumeration.>

A design strategy is presented for efficient and comprehensive testing when the address, data, and bit lines are not externally controllable or observable. Three algorithms are developed for testing common functional faults in content-addressable memories. One provides a novel method for detecting pattern-sensitive faults over a neighborhood size of nine and thereby tests a w-word content addressable memory in 33w+2b+64 operations, where b is the number of bits in a word. The algorithm is significantly more efficient than other embedded procedures for testing pattern-sensitive faults. Two additional simple algorithms are given for testing embedded content-addressable memories for stuck-at and adjacent-cell coupling faults.>

This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of Ο(√n). The overall reduction in testing time is considerable for large size memories.

This correspondence evaluates three types of static interconnection networks for VLSI implementation. The criteria of evaluation have been selected from three orthogonal aspects-physical (chip area and dissipation), computational speed (message delay and message density) and cost (chip yield, operational reliability and layout cost). The main feature of this paper is to augment the selection criteria for the interconnection networks from the classical AT2 metric and to provide results pertaining to realistic VLSI implementation.