In current cryogenic temperature sensor (cryo-TS) systems, the sensing front-end and readout circuits typically operate in cryogenic and room-temperature environments, respectively. This paper proposes a scheme to integrate both the front-end devices and readout circuits of cryo-TS within the cryogenic environment to achieve lower noise, digital fan-out of temperature information, and cost reduction. We employed the silicon-germanium (SiGe) heterojunction bipolar transistors (HBT), which demonstrated excellent linearity and current gain even at cryogenic temperatures, as the sensing front end of the cryo-TS and a Zoom-ADC as its readout circuits. A redundancy bit is introduced in the cryogenic readout ADC to avoid temperature misjudgment. The design methodology and key considerations for implementing cryogenic readout analog circuits are presented. Implemented in a 65 nm CMOS process, the cryo-TS achieved a 1-point-trimmed (at 40 K) inaccuracy of ±0.54 K ($\boldsymbol {3\sigma }$) from 4 K to 70 K under a supply current of 22.13$\mu A$.

Due to the convenience and electrostatic discharge (ESD)-free features, wireless power transfer (WPT) technology has become essential for mobile devices. Conventional WPT solutions use symmetrical inductive couplers with complex structures to enhance misalignment tolerance, while using a large transmitter (TX) coil with a small receiver (RX) coil can increase distance but results in lower power density. On the contrary, we employ in this paper small TX coil and large RX coil for a better tradeoff between power transfer efficiency (PTE), output power and robustness. With detailed analyses, we prove that the small TX large RX configuration outperforms the conventional large TX coil and small RX coil solution and derives the necessary conditions with design procedures for achieving optimal PTE and desired output power. An experimental setup is built to validate the analyses, revealing that the small TX large RX configuration achieves better PTE under the higher output power conditions. Specifically, the system with small TX large RX configuration attains a PTE of 98.7% at an output of 31.29W with an airgap of 10mm.

This paper reports an ultra-low voltage (ULV) relaxation oscillator (RxO) suitable for self-powered devices, designed with a pair of asymmetric swing-boosted (ASB) RC networks. This work enhances low-voltage operational capabilities and improves frequency stability and jitter performance. The RxO features a unique single amplifier configuration incorporated with a customized feedback mechanism that effectively compares the output voltages from the RC networks, substantially reducing jitter due to flicker noise. Additionally, we implement a Duty-Cycling Circuit (DCC) based on a DLL architecture to turn on the amplifier before the desired detection point, providing ample guard time and thereby reducing power consumption, which is essential for ultra-low power applications. The RxO also features a Replica Temperature Compensation Circuit (RTCC) to mitigate circuit delay. Fabricated in 65-nm CMOS, the RxO operates at 2.35 MHz with a minimal supply voltage of 0.5 V, achieving a period jitter of 390 ppm and line sensitivity of 17.4%, and an energy efficiency of 5.82 pJ/cycle. The device demonstrates significant improvements over existing ULV designs, achieving up to 60% reduction in power consumption while maintaining lower jitter levels.

This article presents a millimeter-wave (mm-Wave) quad-core oscillator utilizing a circular transformer and dual-path synchronization technique to achieve low phase noise (PN). We analyze the mechanism of the PN degradation induced by frequency mismatch between individual cores in the conventional quad-core oscillator utilizing a circular inductor, which reveals that the frequency mismatch between the non-adjacent cores will induce an off-resonance issue, which could significantly degrade the PN. This PN degradation induced by the off-resonance is acerbated in the quad-core oscillator utilizing a circular transformer. Based on the analysis, a dual-path synchronization technique is proposed to eliminate the off-resonance issue by providing a direct synchronization path for either two cores in a circular-coupled quad-core oscillator. The proposed technique can be applied to both inductor- and transformer-based circular-coupled oscillators, preventing PN degradation due to the frequency mismatch. Fabricated in 65-nm CMOS, our quad-core oscillator prototype measures a frequency tuning range of 18.2%, from 22.4 to 26.8 GHz. At the 25.8 GHz carrier frequency, the oscillator achieves a low PN of$\!-\!138$dBc/Hz at 10 MHz offset while consuming 19.7 mW, corresponding to an excellent FoM of 193.3 dBc/Hz.

Transformer models excel at natural language processing tasks but are challenging to deploy on edge devices due to high memory and computation demands. To address this, we proposed an energy- and area-efficient transformer accelerator. We identify ‘0’ bits in positive and ‘1’ bits in negative 2’s complement activation values as bipolar sparsity. This form of sparsity shares a larger proportion than the traditional bit-level sparsity in transformer models. We propose a bipolar sparsity compressor (BSC) together with a bipolar processing element (BPE) to detect and skip the bipolar sparsity in a bit-group (BG) level during the inference. It reduces a large proportion of ineffective computations and improves throughput. The significant sparsity scheduling (SSS) dynamically adjusts broadcast settings based on BG-level sparsity ratios, balancing the sparsity skipping and memory access. Furthermore, an importance approximate gating (IAG) filters out unimportant tokens/heads during the attention computation by reusing sparsity information from the BSC, further reducing processing latency and energy consumption. Implemented in a 28nm process, the proposed accelerator achieves$7.62\times $and$12.43\times $throughput improvements on RoBERTa-B and GPT2-xl, respectively. The area efficiency reaches up to 3.51 TOPS/mm2due to skipping a large proportion of bipolar sparsity, reaching$4.83\times$and$5.85\times $higher compared with the state-of-the-art approximate computing accelerator and the computing in memory accelerator on the benchmark model.

Electric vehicles (EVs) have gained significant adoption due to their advantages over conventional vehicles. The Photovoltaic Inductive Wireless Power Transfer (PV-IWPT) system combines wireless charging technology with photovoltaic panels to provide clean, solar-powered EV charging. However, varying distances between the ground and EV chassis create inconsistent coupling coefficients, causing fluctuating optimal load conditions for the IWPT converter and making it challenging to maintain peak efficiency without manual recalibration. This paper introduces a Ground-to-Chassis distance adaptive control approach for PV-IWPT systems that simultaneously achieve Maximum Power Point Tracking (MPPT) for solar harvesting and Maximum Efficiency Point Tracking (MEPT) for power transfer across different ground-to-chassis distances. The system automatically adapts to positional variations without requiring hardware adjustments. We validate our approach through theoretical analysis and experimental verification using a 500-W test platform under multiple distance configurations and solar shading conditions, demonstrating its practical viability for real-world applications.

Thyristor-controlled LC-coupling hybrid active power filter (TCLC-HAPF) offers low DC-link voltage and a wide reactive power compensation range, making it a promising solution for power quality compensation in medium-voltage power systems. Recently, conventional finite-set model predictive control (FS-MPC) was proposed to control the TCLC-HAPF. It requires state prediction and enumeration/rolling optimization for obtaining optimal inverter voltage vector, which is computationally intensive. This paper proposes a finite-set simplified model predictive control (FS-SMPC) that eliminates the prediction and enumeration processes, therefore reducing computational burden. Simulation results are provided to verify the feasibility and effectiveness of the proposed FS-SMPC.

This work proposes a single-point linear-regression-assisted trimming method for a MOSFET-based voltage reference to reduce operation verification complexity. By obtaining the correlation between the input features at a unique temperature and the output voltages across the operating temperature range from layout-aware Monte-Carlo simulations, we can build the linear regression model to predict the profile of the voltages across the temperature range based on eight input features. Hence, we can apply the appropriate trimming code on the circuits, avoiding time-consuming temperature characterization. We design the voltage reference in 65nm CMOS and obtained 8,000 sets of simulation data to train the regression model. Validated through simulation, we reduce the temperature coefficient of the voltage reference to 64.7ppm/°C using the proposed scheme, 26% lower than that of the conventional 2-point trimming, evincing the efficiency and accuracy of the linear-regression-assisted trimming.

This article presents a four-phase adaptive on-time (AOT) controlled buck converter with an ultra-fast load-transient response. A dynamic-frequency clock generator is proposed to generate and auto-synchronize three duty signals with 90°, 180°, and 270° phase shifts based on an already-generated duty signal. Interleaving angles between phases are always kept constant even when the switching frequency varies. Unlike the traditional pulse distribution scheme in constant on-time (COT) multiphase buck converters, the generated pulses no longer need to be sequentially distributed to different phases, but synchronized to one phase instead. Therefore, a much faster load-transient response can be achieved. A transient-enhancement scheme is also proposed to remove the speed limitations introduced by the error amplifier (EA) during load transient. The fast response merits of the AOT controller can thereby be fully taken advantage of while a relatively constant operating frequency is maintained under different input and load conditions. Simulated in a 180-nm BCD process, the proposed converter shows a fast load-transient response with 102-mV output voltage droop and 754-ns settling time for a 6A/1ns rapid load current step, where a 22-μF decoupling capacitor with a relatively large equivalent series resistance (ESR) of 15 mΩ is used. Besides, this work achieves a peak efficiency of 89.7% for 5V-to-1.4V conversion, while the efficiency is maintained at >75% over a wide load range from 1 A to 10 A.

This paper proposes an inductor-first two-inductor two-flying-capacitor (2L2C) multi-path hybrid DC-DC Converter. The proposed converter operates with a switching frequency of 2MHz, an input voltage range of 3 V to 5 V, and an output range between 0.8 V and 1.2 V using only 2-V NMOS power transistors. This hybrid DC-DC topology enables continuous input current and thus alleviates electromagnetic interference (EMI) issues. The two inductors operate in an interleaved manner, reducing the output current ripple. The switched-capacitor network decreases the average inductor current. This work is simulated in a 180-nm BCD process. Both inductors are 470nH with 29-mΩ DCR, while both flying capacitors are 10μF with 10-mΩ ESR. We obtain a peak efficiency of 96.89% at 400 mA load for a 4V-to-1V conversion.

This paper presents a 12V-input 1.8V-0.8V-output multiple-output hybrid buck (MOHB) DC-DC converter with a shared flying-capacitor (CF0) and real-time CF0voltage calibration, while the main control loop uses a pulse-width modulation (PWM) control scheme. With the proposed time-interleaving operation scheme, the MOHB converter has no cross regulation during load transient. The real-time CF0voltage calibration ensures that the voltage across CF0 equals VIN/2. The MOHB converter is designed with four outputs and simulated in an 180nm BCD process. Each output employs a 1μH power inductor with 19mΩ DCR and one 4.7μF flying capacitor. With 12V input, one output equals to 1.8V and other outputs equal to 1V, the peak efficiency 95.2%.

This paper introduces an ultra-low-power 32kHz pulse injection crystal oscillator (PIXO) using a reference-free stacked inverter chain to generate the delay signal for energy injection. If the power consumption of both the pulse driver and the inverter-based delay generation circuits is considered, analysis reveals that the closer the injection happens at the peak and valley of the output waveform, the lower the system power efficiency. The proposed stacked logic gates can generate an injection pulse that is 48° away from the zero-crossing point of the output waveform without resorting to the process- and temperature-sensitive pico-ampere-level current reference and duty-cycle-correction loop for injection timing control. The proposed PIXO can properly operate across −40°C to 120°C at five process corners (TT/SS/SF/FS/FF). Implemented in a 65nm CMOS technology, at a 0.6V voltage supply, post-layout simulations verify that the PIXO achieves 1.2nW power consumption at a 32kHz injection rate at 25°C. Thanks to its digital-intensive architecture, the PIXO occupies only 0.0069mm2active area.

Switched-capacitor-inductor dual-path hybrid DC-DC converter can achieve high power density and efficiency, with reduced inductor voltage and current stresses and thus reduced inductor conduction loss and volume. However, it suffers from a large output ripple due to the hard-charging of the switched-capacitor (SC). To take advantage of recent in-substrate or on-chip high-density capacitor technologies, this paper proposes a multiphase interleaving operation for the dual-path SC hybrid converter, increasing the equivalent switching frequency and reducing the amplitude of the current ripple. It achieves a significant output ripple reduction within negligible efficiency degradation. The analysis and simulation results prove that the proposed scheme is a better method for reducing output ripple than increasing operating frequency or reducing power transistor size in the hard-charging path.

Low-Power fully-integrated oscillators are the cornerstone of Internet-Of-Things devices due to their compactness, high energy-efficiency, and scalability. This paper presents a relaxation oscillator featuring double capacitor-charging headroom by applying chopping on the capacitor. Such an increase in the charging headroom soothes the frequency instability attributable to the comparator and logic gate’s delay, culminating in a more stable frequency output amid voltage and temperature variations. We designed and fabricated two 0.4V relaxation oscillators (803kHz and 428kHz) in the TSMC 65nm process. The measured temperature coefficients are 164 and 106 ppm/°C (averaged from 10 samples) across −20 to 120°C for the 803kHz and 428kHz relaxation oscillators, and the line sensitivities are 15.8%/V and 14.4%/V across 0.35 to 0.5V. Such results are improved by >1.8× and >11× compared with the reference oscillator with regular charging headroom. The oscillators’ long-term stabilities are 150 and 110 ppm with a 0.1s gating interval.

This paper presents a miniature magnetic resonance imaging (MRI) platform specifically designed for imaging small-volume samples (~1μL), making it particularly suitable for real-time and on-site biochemical sample monitoring. This innovative system employs an MRI application-specific integrated circuit (ASIC) for excitation and detecting the nuclear magnetic resonance (NMR) signal. To cope with the small-volume sensing, the platform features a customized frontend probe, which includes a miniaturized saddle coil and a PDMS-molded sample well to contain the microlitre-volume sample under observation. Our proof-of-concept measurements on small-volume samples demonstrate an MRI image resolution of 150 × 150 × 250μm3. These results highlight the system’s applicability and potential for future biological analysis, offering a promising tool for researchers in the field.

This article presents a resonant switched-capacitor (SC) parallel inductor (ReSC-PL) hybrid buck converter with reduced inductor current for high and wide voltage conversion ratio (VCR). The proposed ReSC-PL buck converter lowers down the switching node voltage with${V} _{\text {IN}}$-related flying capacitors and reduces the inductor current${I} _{\text {L}}$with${V} _{\text {OUT}}$-related flying capacitors. Therefore, it can always effectively reduce${I} _{\text {L}}$to a value below$0.5\sim 0.67$of the output current${I} _{\text {O}}$for high VCRs ranging from 10 to 20. In addition, by utilizing the parasitic inductor, this design effectively reduces the glitches on the output and forms a resonant SC operation to further improve the conversion efficiency. This work, fabricated in 180-nm Bipolar-CMOS-DMOS (BCD), occupies an area of 8.88 mm2. Measurement results show that the proposed ReSC-PL buck obtains a peak efficiency of 91.8% and a peak current density of 350 A/cm3 with a power inductor as small as$2.5\times 2\times 1.2$mm3, with 12-V input and 0.6-V to 1.2-V output, and 5-A maximum output current.

Cryo-CMOS IC for quantum applications, proposed for tens of years, are designed to control quantum processors operating at cryogenic temperatures (CTs). The reference circuits play a significant role in quantum controllers, providing a relatively stable biasing for analog and radio frequency (RF) circuit blocks. Based on a literature review, we discovered that achieving high-accuracy reference voltage or current at CTs is challenging due to the unstable temperature characteristics of complementary metal-oxide-semiconductor (CMOS), bipolar junction transistor (BJT), or resistors in the general CMOS process at CTs. Therefore, certain specialized device structures, such as dynamic threshold MOS (DTMOS), can be employed within the bulk CMOS process. Alternatively, BJT and other devices found in specific processes, such as silicon-germanium (SiGe) and fully depleted silicon on insulator (FD-SOI) CMOS, can achieve adaptive temperature compensation. This paper provides a succinct overview of several fundamental structures and common research hot spots about the reference voltage circuits, and then assesses their suitability for CT circuit design, considering the reliability of devices in bulk CMOS, FD-SOI CMOS, and SiGe process. Finally, the paper summarizes the types of cryo-temperature reference circuits and offers an overview and comparison of them.

Conventional noise-shaping (NS) SAR ADCs require a high-quality power supply provided by the power management system consisting of a DC-DC converter and a low dropout (LDO) regulator. However, the LDO’s dropout voltage limits the power system’s efficiency. To enhance efficiency, this paper proposes removing the LDO. Nevertheless, the voltage ripple generated by the DC-DC converter will directly inject into the ADC, causing two issues: 1) ripple modulation with signal, generates modulation tones that affect the linearity, and 2) ripple modulation with shaped-quantization-noise, folding into baseband and increasing in-band noise. To mitigate these errors, we propose a proper frequency management scheme based on oversampling and a low-pass filter (LPF) integrated into the noise transfer function (NTF) of the NS-SAR. This paper implements a 2-channel time-interleaved (TI) NS-SAR ADC with 2nd-order NS and 2nd-order LPF. The prototype, fabricated in a 28nm CMOS process, operates with 1V provided by a boost DC-DC converter with 0.55V input. It achieves an 80-dB-SNDR over a 3-MHz-BW, operating at a sampling rate of 330MS/s with the DC-DC converter switching frequency of 145MHz. The total system consumes 3.59mW, with the ADC itself consuming 3.02mW, and exhibits a Schreier FoM (FoMS) of 170 dB. By removing LDO, the total system efficiency reaches 84.1%.

Enhancing the energy efficiency for the residual block is crucial for an energy-efficient deep neural network accelerator. This paper presents a multi-clock pointwise-pointwise (MCPW2) technique to process the adjacent PW convolution layers across residual blocks, reducing up to 75.0% DRAM access for the intermediate feature maps while securing >88.1% processing element (PE) utilization. Moreover, we introduce a dual-precision packing (DPP) DSP array to compute multiple 4/8-bit multiplications in a shared DSP, improving the accuracy by 1.5% (ImageNet) using low-precision residual distillation (RD) with adaptive-resolution quantization. The DPP DSP and adaptive-resolution RD boost the DSP efficiency up to$4.0\times $, reduce DRAM access by 50.0%, and improve the throughput by$\gt 2.7\times $. We also propose a dynamic accumulator/multiplier (A/M) DSP reconfiguration scheme to dynamically adjust the level of parallelism along the input/output channel dimensions. It also increases the PE utilization by$1.8\times $for the depthwise (DW) convolution layers with 33% less hardware resource overhead. Implemented on Xilinx VC709, the proposed accelerator achieves PE utilization of >93.0%, a DSP efficiency gain of$\gt 2.9\times $, and a throughput improvement on benchmarked networks of$4.9\times $while exhibiting an energy efficiency of 97.8 GOPs/W and a normalized throughput of 1.18 GOPS/DSP.

This paper presents a lightweight background calibration for the distortion of the analog-to-digital converter (ADC)’s input buffer. The buffer’s nonlinearity is calibrated on-chip by the Harmonic-Compensated Diode Load (HC-DL), whose bias voltage is determined by the calibration algorithm facilitated by dither injection at the input of the buffer. A two-step ADC is exploited to demonstrate the calibration, where the coarse-fine ADC gain mismatch and sampling skew at the 1ststep are calibrated by monitoring the occupation of the correction range (OCR) at the 2ndstep. Verified in a 12b 1 GS/s pipe-SAR ADC in 28 nm CMOS, the SNDR and SFDR at Nyquist input are 60.96 dB/76.8 dB, respectively and the SFDR keeps >75 dB over PVT.

This paper presents a type-II sampling phase-locked loop (SPLL) that accelerates the locking process by exploiting a time-to-digital converter (TDC) based automatic frequency and phase calibration (AFPC) technique. The proposed AFPC accelerates the frequency acquisition by using a type-I loop to map the quantized phase error to the switched-capacitor (SC) control word of the voltage-controlled oscillator (VCO). The subsequent phase error after frequency locking is swiftly reduced within one TDC resolution by adjusting the division ratio of the multi-modulus divider (MMD) with little hardware expenditure. The proposed AFPC can guarantee a fast-locking time at different initial frequencies, which is insensitive to the variation of TDC resolution. This paper also contributes to a design strategy for the AFPC loop, e.g., the required frequency step of the SC and the TDC resolution, based on the analysis of the lock-in range of the SPLL. Fabricated in 28-nm CMOS with a core area of 0.15 mm$^{\mathbf {2}}$, the 6.0-to-6.9GHz SPLL prototype using a reference (REF) clock of 100 MHz achieves a locking time of$0.62~\mu $s ($62{T} _{\mathbf {REF}}$) at an 880-MHz hopping frequency. At 6.5 GHz, the SPLL consumes 4.6 mW and measures an RMS jitter and REF spur of 99 fs and –71.6 dBc, respectively, corresponding to a jitter figure-of-merit (FoM$_{\mathbf {jitter}}$) of –253.5 dB.

The article introduces an antenna-envelope detector (ED) co-designed wake-up receiver (WuRX) that can automatically detect the frequency-hopping sequence from 840 to 970 MHz. Prototyped in 65nm CMOS, the WuRX supports three modes: 1) low-power mode that achieves −68 dBm sensitivity with 9.9nW power consumption, 2) Q-enhanced mode that provides 22 dB rejection to an on-off-keying (OOK) modulated pseudo-random-bit-sequence blocker at 10 MHz offset and 41 dB rejection to a continuous-wave one at 10 MHz offset, with a power consumption of$39.6~\mu $W and 3) 2-stage wake-up mode that combines the advantages of both the low-power mode and Q-enhanced mode, with a power consumption of 33.7 nW. These characteristics are achieved by exploiting 1) an antenna-ED interface where the Q-factor of the antenna is equal to the Q-factor of the capacitor to ensure a conjugate matching condition for the maximum available power transfer from the antenna to the ED, 2) a frequency tuner connected to the antenna-ED interface calibrated by a frequency-locked loop, and 3) a Q-booster reconfigured from the frequency tuner for boosting the passive gain and narrowing the bandwidth of the interface.

This article reports a globally systolic and locally parallel (GSLP) convolutional NN (CNN) and Transformer accelerator based on the scalable and reconfigurable (SR) embedded dynamic random-access memory (eDRAM) compute-in-memory (CIM) macro. It features: 1) a GSLP architecture employs systolic CIM macros with the reconfigurable inter-CIM network to support flexible dataflow, including weight stationary (WS), output stationary (OS), and Row stationary (RS); 2) an SR-CIM macro features reconfigurable weight/input/output memory ratio to maximize the related data reuse in different dataflow; 3) a high-density 3T eDRAM-CIM cell to further improve the density of the accelerator; 4) an area-efficient in-memory accumulator (IMA) to save the area and power overhead of the digital accumulation in each CIM macro. Prototyped in 28-nm CMOS process, the proposed GSLP-CIM accelerator exhibits a 4b peak throughput density of 0.16 TOPS/mm2 and a 4b peak compute energy efficiency of 3.55 TOPS/W. Specifically, evaluated with ResNet-50@ImageNet and ViT-B@ImageNet, this work reaches the system throughput of 24.5 and 5.66 inferences per second (IPS), the system throughput density of 19.3 IPS/mm2 and 4.46 IPS/mm2, the system compute energy efficiency of 423.9 inferences per watt (IPW) and 97.6 IPW, respectively.

This work presents a high energy-efficiency mixed-signal multiply-and-accumulate (MAC) macro in charge-domain for machine learning (ML) systems. It involves crucial features aimed at enhancing energy efficiency, throughput, and area efficiency, namely: 1) a parallel-serial (ParSer) scheme to augment the throughput by parallel input channels and reduce the power via serial analog accumulation rather than digital summation; 2) the weight-independent parallel digital-to-analog converter (DAC) sampling (WIPDS) to cancel weight nonlinearity during sampling and allow for resource-efficient DAC, significantly saving power and area; 3) a high energy-efficiency dynamic amplifier (DA) introduced to improve drivability and counteract attenuation of the serial accumulation, thereby attaining the desired accuracy with relaxed the afterward analog-to-digital converter (ADC) resolution and consequently reducing power consumption; 4) an optimized SAR ADC to reach higher energy efficiency. Fabricated in 28-nm CMOS technology, the prototype exhibits a peak energy and area efficiency of 362 TOPS/W and 3.23 TOPS/mm$^{2}$, respectively.

This work presents an always-on CNN processor featuring compute-in-memory (CIM) and layer-fusion (LF) techniques. It demonstrates an end-to-end neural network (NN) inference while eliminating memory accesses for both the weight and inter-layer activation, thus significantly saving associated energy. The analog LF-CIM processor combines charge- and time-domain multiply-accumulate (MAC) arrays in a fusional manner, avoiding the need for the interfacial analog-to-digital and digital-to-analog converters; it also supports a highly sparsity-adaptive network and exhibits low-voltage-supplied tolerance to circuit noise and variations, which facilitates an energy-efficient and robust CNN processor, simultaneously. Furthermore, the full-precision activation originating from the LF reduces the NN parameters and operations, while the inference accuracy is improved by the presented ensemble NN. The prototype processor is fabricated in a 28-nm CMOS process, demonstrating a fully on-chip MNIST inference with 97.9% accuracy. It operates at 3,508 frames per second while consuming$11.6~\mu $W at a 0.5-V supply; the achieved efficiency of 3.32 nJ/frame is over 50-fold than the state-of-the-art end-to-end MNIST accelerators.

Gallium-Nitride (GaN) high electronic mobility transistor (HEMT) enables faster switching frequency for buck converters. Therefore, high dV/dt immunity and small deadtime of the switching node become important indicators for GaN-based buck converter. This paper presents a high switching frequency GaN gate driver with an asymmetrical noise current clamping technique for the floating level shifter for 5000V/ns dV/dt noise immunity in simulation and over 60V/ns immunity in measurement. Meanwhile, the proposed deadtime generator achieves adaptive deadtime control without a down level shifter nor fast comparator for sensing operation state of the buck. The proposed driver was implemented in a$0.18\mu $m BCD process, used in a GaN-based buck converter for verification. It achieves 7.45ns and 1.1ns deadtime for the VSWtrailing and leading edge, respectively. The buck converter obtains 86.5% peak efficiency for 12V-5V conversion, with 10MHz switching frequency.

This brief presents an output-capacitorless low-dropout (OCL-LDO) regulator based on flipped-voltage-follower (FVF) and dual pMOS pass transistors. An adaptive-compensation buffer (ACB) dynamically regulates the operation of the pass transistors. Specifically, when the load current falls below 5 mA, only the smaller pass transistor is activated; otherwise, both pass transistors are engaged, thereby simultaneously mitigating the minimum load current requirement for FVF architecture and extending the load current ranging from 0 to 30 mA while maintaining stability without an external load capacitor. At 1.15-V supply voltage and 0-mA load current, the quiescent current is$6~\mu $A. The output voltage is 1.0 V with a dropout voltage of 0.15 V. Measurements show that with a load current stepping from 0 to 30 mA at an edge time of 100 ns, the output voltage undershoot is 0.2 V with a recovery time of 200 ns while achieving a load regulation of 0.23 mV/V. Our OCL-LDO is fabricated in a 180-nm CMOS with an active area of 0.031 mm2.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

This paper proposes a radio-frequency (RF) cross-connected (CC) rectifier with LC source degeneration (CCLC). The LC network resonates at twice of the working RF frequency, shaping the drain-source and gate-source voltages of the rectifying transistors of the CC rectifier. As a result, the proposed scheme reduces the transistors’ reverse current and the shoot-through current, and thus the root mean square current of the switches, improving the power conversion efficiency (PCE). Meanwhile, it has a better input impedance matching over a wide input power range from the voltage reshaping. Subsequently, we implement the CCLC topology in both one-stage and two-stage CC rectifiers. To reduce the silicon area, we design coupled inductors for the two LC networks of the two-stage CCLC rectifier. We fabricated the rectifiers using a 65-nm CMOS process. The measured PCE of the one-stage and two-stage rectifiers are 67.6% and 61.2%, respectively. The proposed scheme has a wider dynamic range than previous works.

Compute-in-memory (CIM) is a promising approach for realizing energy-efficient deep neural network (DNN) accelerators. Previous CIM works focusing on uniform quantization (UQ) demonstrated a higher Multiply-accumulate (MAC) precision requirement to maintain DNN inferencing accuracy, resulting lower energy efficiency. The nonuniform quantization (NUQ) has proved to require lower precision than UQ, while the existing implementations are based on high precision digital lookup table (LUT) (e.g., 16-bit), leading to large energy and area overhead for multiplier. This work presents CLUT-CIM fabricated under 28-nm CMOS featuring: 1) a capacitance LUT (CLUT)-based NUQ MAC circuit with thermometer coding scheme for weight and input activation that avoids digital LUT and reduces the energy and area overhead; 2) a signed-channel training (SCT) method that reduces the switching activity of computation to improve the energy efficiency; 3) a dual-port 6T-SRAM array to enable simultaneously weight updating and CIM operations, enhancing the memory utilization and CIM throughput. Under 3-bit NUQ precision, the peak energy efficiency is 114.3 TOPS/W, and peak throughput density is 31.78 TOPS/mm2.

This work presents a 0.4-V supply, 12-nW reverse bandgap voltage reference (BGR) with single BJT and indirect curvature compensation. To achieve sub-0.5V operation, the proposed BGR employs the reverse BGR based complementary-to-absolute-temperature (CTAT) voltage generator, which does not suffer from the settling error and thus reducing the biasing current for the BJT. The reduction in BJT biasing current can reduce the power consumption, thus relieving the burden on the$2\times $charge pump as well, in which the minimum supply voltage of the proposed BGR decreases down to 0.4 V. In this paper, we employ a differential pair proportional-to-absolute-temperature (PTAT) voltage generator to provide a sufficiently large PTAT voltage. To suppress the temperature coefficient (TC) under limited power and voltage budgets, we propose using a nA level PTAT plus nonlinear current to bias both the BJT and PTAT voltage generator. This approach provides an indirect voltage curvature compensation. The proposed reverse BGR fabricated in 65 nm CMOS, occupies an active area of 0.0470 mm2. Measurement results from 8 chips show an average reference voltage of 487.4 mV under 0.4 V supply, with an average TC of 28.4 ppm/°C over a temperature range from -40°C to 100°C, while consuming only 12 nW power.

This paper presents a single-inductor multiple-output (SIMO) DC-DC converter with fixed-frequency victim-last charge control. This scheme switches the load-transient channel (victim) to the last of the charging sequence, addressing the inherent cross-regulation issue in conventional charge control SIMO. We first analyze why the conventional fixed-frequency charge control has such an issue. Then, we present the working principle of the proposed scheme. After that, we propose a charge-error calibration technique that minimizes the side effects caused by victim-last control, ensuring a smooth order switching of the original last channel. We implemented and fabricated the proposed SIMO DC-DC converter in a 0.18-$\mu $m BCD process. Measurement results show that we are able to reduce the cross-regulation to 0.057mV/mA with a 225-mA load step under fixed switching frequency. The measured peak efficiency is 84.1%.

In this paper, we propose a fully symmetrical obfuscated-interconnection PUF (SOI PUF), which containsndelay stages with each stage having 4kobfuscated interconnections for resisting machine learning (ML)-based modeling attacks. All the delay stages contribute tokPUF primitives while achieving a 20× increase in the number of possible interconnections with the same hardware resources over similar prior arts. The SOI PUF mathematical model also theoretically demonstrates the large number of nonlinear matrix multiplications for resisting ML-based modeling attacks. We further exploit parallel weak PUF cells and propose the challenge-obfuscated SOI PUF (cSOI PUF), which can effectively prevent adversaries from bypassing unknown interconnections through reverse engineering (RE) attacks. The proposed SOI PUF and cSOI PUFs are evaluated by both software simulation and FPGA measurements. Without requiring a largekas in the existing PUF architectures, the simulation results demonstrate that the proposed SOI and cSOI PUFs can achieve a ~50% prediction accuracy fork≥ 3, even when facing ML attacks using 5-hidden-layer Artificial Neural Network (ANN) with 40M training CRPs. Furthermore, the proposed (64,2/4/6/8)-SOI PUF and (64,2/4/6/8)-cSOI PUF implemented using Xilinx Artix-7 FPGA can both achieve a measured reliability and uniformity of >94% and ~50%, respectively. Depending on the value ofk, the uniqueness ranges from 29.1% to 42.7% for SOI PUFs, and further improves to ~50% for cSOI PUFs. The resilience against Reliability-based modeling attacks, Probably Approximately Correct (PAC) attacks and Reverse-Engineering-based modeling attacks will also be discussed.

This paper presents an 8-to-10GHz CMOS voltage-controlled oscillator (VCO) with common-mode (CM) resonance. It features a nested 8-shape inductor-based CM resonator with intrinsic differential$2^{\text{nd}}$harmonic extraction. The mutual coupling of the main tank and CM resonator is negligible due to the reversal magnetic field, which avoids the additional chip area occupation of the explicit CM inductor. The VCO prototyped in 65-nm CMOS scores a −136.7-dBc/Hz PN with 10-MHz offset at 9.97 GHz, consuming 4 mW of power with a standard supply voltage of 1-V. The achieved peak Figure-of-Merit (FOM) is 190.6 dBc/Hz at 10-MHz offsets. Over a 22.9% tuning range, the VCO upholds a consistent FOM of >188.5 dBc at a 10-MHz offset. The core area is 0.116 mm2,

Smart meter monitors electricity consumption through modern metering devices connected to the Internet via Internet of Things (IoT) technology, which can provide intelligent and fast applications on-site such as arc fault protection based on nonintrusive monitoring load classification with fast safety responses for varying electric loads. Traditional three, four, and five layers of the IoT architecture cannot support such fast responses under loading variation. This article aims to propose six layers of IoT Cloud-Edge Infrastructure equipped with a reconfigurable mixed-signal controller as a smart meter platform for adaptation to different environments and, for example, deal with fast arc fault detection corresponding to different load characteristics. Such an architecture can reduce the processing time for safety, reduce bandwidth for communication, improve arc detection accuracy under different loading environments, and lower the overall computation cost.

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the physical unclonable function (PUF) security while consuming the same hardware resources as the conventional XOR arbiter PUF (XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 field-programmable gate array, both the proposed (64,4)- and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)- and (64,8)-OIPUF by$\geq 68\times $and$\geq 48\times $at up to 100 °C, respectively. Evaluated using the logistic regression (LR), artificial neural network (ANN), and covariance matrix adaptation-evolution strategy (CMA-ES) machine learning (ML) algorithms, the proposed (64,4)- and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M challenge–response pairs as training set, respectively, demonstrating a significant improvement over similar prior arts.

This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to overcome the SAR ADC’s speed bottleneck. Benefiting from this technique, the sampling rate of the prototype 10b single channel 1b/cycle SAR ADC reaches 600 and 700 MS/s at 0.9 and 0.95 V supply voltage, while consuming 1.49 and 2.02 mW in 28 nm CMOS, respectively. Moreover, the 10b ADC achieves the SNDR of 56.39 and 56.42-dB at a Nyquist rate input frequency of 600 and 700 MS/s, leading to a Walden FoM of 4.6 and 5.3 fJ/conversion-step, respectively.

This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a transformer-based rich-harmonic shaping voltage-controlled oscillator, the proposed S-PLL at 3.78 GHz exhibits an integrated jitter of 39.6 fsRMS (1 kHz to 100 MHz), and the jitter-power figure-of-merit scores −260.2 dB. The reference (REF) spur is −70.96 dBc due to the embedded REF-feedthrough suppression technique.

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ($I_{\mathrm {L,DC}}$) compared to the existing single-inductor two-flying-capacitor ($1L$-$2C_{\mathrm {F}}$) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200$\text{m}\Omega $.

This paper presents a hybrid single-inductor bipolar triple-output (SIBTO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays. Generating the bipolar rails$V_{\mathrm {OP}}$and$V_{\mathrm {ON}}$for the pixel array and the analog rail AVDD for the source driver with a single inductor greatly reduces the system size and cost. This work adopts the floating negative output topology for an ultra-clean positive output. In addition, we propose a push-pull charge balancer to compensate and regulate the$V_{\mathrm {OP}}$, improving the line and load regulation with continuous currents and acceptable power consumption. This work also proposed a slow-comparator based ordered power distributive control (SC-OPDC) to regulate the AVDD with a pulse-skipping scheme to reduce the power loss. The designed power transistor buffers with adaptive deadtime control improve power conversion efficiency and decrease the required minimum load current of AVDD. The proposed SIBTO converter, implemented in 0.18-$\mu \text{m}$BCD process, operates at 1.67 MHz. It achieves a peak efficiency of 94.1% at 0.88 W output and a maximum output power of 3.67 W with an efficiency of 87%. The maximum output voltage ripples are 5 mV, 17 mV, and 7.5 mV for$V_{\mathrm {OP}}$,$V_{\mathrm {ON}}$, and AVDD, respectively.

Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of < 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only < 0.76% with no additional external components.

This paper presents the theory and implementation of a balanced dual-core inverse-class-F (class-F$^{\mathrm{ -1}}$) voltage-controlled oscillator (VCO). The class-F$^{\mathrm{ -1}}$topology supports high-quality-factor (high-$Q$) differential switched-capacitors (SCs) for both fundamental and 2$^{\mathrm{ nd}}$-harmonic frequency tuning, which is beneficial for improving the phase noise (PN). However, the unequal parasitic capacitors from the NMOS and PMOS negative${g}$textsubscript m transistors make it impossible to minimize their flicker noise upconversions simultaneously, especially at high operating frequencies. The mechanism of this effect is analyzed qualitatively with the model of coupled oscillators and verified using the impulse-sensitivity function (ISF) approach. To address this issue, we propose a dual-core class-F$^{\mathrm{ -1}}$VCO that leverages a balanced coupling scheme to minimize the flicker noise upconversions of NMOS and PMOS transistors simultaneously and still keep the advantage of tuning the 2$^{\mathrm{ nd}}$-harmonic frequency with differential SCs offered by the class-F$^{\mathrm{ -1}}$topology. Additionally, the symmetrical circuit topology aids in improving the differential output balancing. Prototyped in a 28-nm CMOS process without ultra-thick metal, the balanced dual-core class-F$^{\mathrm{ -1}}$VCO dissipates 19.7-mW and achieves a PN of$\!-\!113.9/\!-\!135.8$-dBc/Hz at 1/10-MHz offset from an 18.23-GHz carrier. Tuned from 15.22 to 18.23-GHz, the proposed VCO exhibits superior figure-of-merits (FoMs) at 1/10-MHz offset from 185.3/187.0 to 186.2/188.1-dBc/Hz.

This paper presents the design challenges and advanced circuit techniques of integrated gate drivers for non-isolated buck converters using gallium nitride (GaN) devices to achieve fast switching and high conversion efficiency. Focusing on the essential tradeoff considerations, we first explain the detailed circuit-level issues of realizing normal and safe operations regarding integration feasibility, device safety, operation reliability, and power-stage loss alleviation when driving a GaN switch. Accordingly, we review the state-of-the-art techniques for improving various aspects of the performance, including on-chip bootstrapping enhancement, over-voltage and false-switching prevention, electromagnetic interference (EMI) noise suppression, and adaptive driving optimization. We further highlight the feature advantage of distinct techniques in specific performance/function aspects, aiming to bring GaN driver design insights and providing technical references regarding the technical superiority and limitations of improving the overall converter performance.

This paper presents a high-efficiency continuous-output-current buck-boost (COCBB) converter with a single buck-boost mode operation. The proposed COCBB comprises one flying capacitor ($\mathbf {C}_{\mathbf {F}}$), one power inductor ($\mathbf {L}$), and five power switches ($\mathbf {S}_{\mathbf {1}}$to$\mathbf {S}_{\mathbf {5}}$). With the help of a flying capacitor, the proposed COCBB converter allows its power inductor to continuously deliver output current while achieving a wide conversion ratio range of$\mathbf {D/(1-D)}$, without right-half-plane-zero (RHPZ). With the continuous output current delivery, the circuit exhibits a small output voltage ripple, good transient response and high efficiency. We employ a double clock timing (DCT) control method to obtain a smooth controller-mode transition between the DCT control and pulse-width-modulation (PWM) control for different load conditions. Fabricated in$0.18\mu \text{m}$CMOS, the prototype chip regulates an output voltage of 1.6 V from a 1.4 V to 1.8 V input range and revealing an undershoot/overshoot of 90/30 mV under the load transient steps between$100\mu \text{A}$and 900mA. The measured output ripple is only 10 mV with a loading current of 400 mA. Also, the converter manifests a peak efficiency and a current density of 95.5% and 0.46 A/mm2, respectively.

This paper presents a segmented curvature-compensated bandgap voltage reference (BGR) with low temperature coefficient (TC) and power consumption across a wide temperature range. In this work, we achieve temperature segmentation by comparing voltage instead of current, as in the conventional method, significantly reducing power consumption. Furthermore, we examine the trade-off between TC and power consumption, focusing on optimizing the number of temperature segments. In the core circuit, we utilize a regulated cascode current mirror to minimize channel length modulation induced error existing in the current-based BGR topology. We also introduce a replica structure to prevent oscillation and design comparators with the hysteresis characteristic to address noise influence. The proposed BGR, implemented in 65 nm CMOS, occupies an active area of 0.058 mm2. Measurement results of 6 chips show that the achieved reference voltage of 431.3 mV under 1 V supply has the best TC of 8.7 ppm/°C over a temperature range of −40 °C to 90 °C, consuming 740 nW at 20 °C.

This paper reports a reference-less frequency- detector-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring wide frequency acquisition. We use a current-starved ring oscillator controlled by a 5-bit resistive digital-to-analog converter to maintain quarter-rate operation, supporting a capture range of 110.4%. By the virtue of a deliberate-current-mismatch charge pump pair, we form the single-sided capture scheme in the frequency detection characteristic, eliminating the power-hungry circuits in the high-speed clock and data paths. Employing a hybrid control circuit, the proposed BBCDR automates frequency acquisition and phase tracking in the overall 32 bands. Prototyped in a 65-nm CMOS, the BBCDR covers a wide data rate from 10.8 to 37.4 Gb/s, achieving an acquisition speed of 4.63 [(Gb/s)/$\mu \text{s}$] and an energy efficiency of 1.3 pJ/bit.

A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by >14 dB within the 1st Nyquist zone, and >8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within$1\times 10 ^{5}$iterations.

High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.

This article presents a fully integrated tri-band RF energy harvesting system (RFEH) in 65-nm CMOS technology. The system is designed to harvest ambient RF energies at 900 MHz, 1.9 GHz, and 2.4 GHz through a tri-band impedance matching network (IMN), cross-coupled differential-drive (CCDD) rectifier, and an output voltage monitoring circuit to limit the rectified output voltage to 3.3 V. The system achieves a power conversion efficiency (PCE) of over 30 % across all three frequency bands with a peak of 42.8 %. Furthermore, the system exhibits a peak sensitivity of -20 dBm at an output DC voltage of 1$V$output.

This paper presents a hardware-reuse strong physical unclonable function (PUF) based on the intrinsic transfer paths (TPs) of a conventional digital multiplier to achieve a strong modeling attack resilience. With the multiplier input employed as the PUF challenge and the path delay as the entropy source, all the possible valid propagation paths from distinct input/output pairs can serve as PUF primitives. We can quantize the path delay using a time-to-digital converter (TDC), and select the suitable TDC output bits as the PUF response. We further propose a lightweight dynamic obfuscation algorithm (DOA) and a secure mutual authentication protocol to counteract modeling attacks. The proposed strong PUF using a 32×32 multiplier as implemented in the Xilinx ZYNQ-7000 SoC features a total of 2048 intrinsic PUF primitives, while achieving a response stream (RS) with an average of 1024 responses per TDC output bit per challenge. WithBit(5) andBit(6) of the TDC output selected for PUF response generation, they demonstrate a measured reliability and uniqueness of up to 98.31% and 49.34%, respectively, with their excellent randomness performance as validated by the NIST SP800-22 tests. Under machine learning (ML)-based modeling attack with artificial neural network (ANN), the measured prediction accuracy of bothBit(5) andBit(6) can still be maintained at ~50% with a total of >200 million CRPs as the training set.

This brief reports a dual-topology CMOS rectifier with an extended power dynamic range (PDR) for radio frequency (RF)-based hybrid energy harvesting (RF-HEH) systems. By leveraging both the cross-coupled differential drive (CCDD) and the Dickson topologies with high forward conduction and low reverse leakage, we obtain an extension of the rectifier’s PDR by adaptively disabling the CCDD counterpart and enabling the Dickson counterpart to dominate the rectifier’s performance during high-power operation. Apart from that, we formulate a rectifier-performance index (RPI), which accounts for the power conversion efficiency (PCE), the PDR, the sensitivity, and the load resistance of the rectifier to provide an adequate performance benchmark with the state-of-the-art rectifiers. Fabricated in a 130-nm CMOS, the proposed dual-topology rectifier measures a wide PDR of 19.5 dB with a peak PCE of 78.4% for a 100-$\text{k}\Omega $load operating at 900 MHz. Besides, our prototype records the highest RPI of 19.2 compared to the recent arts operating at GSM900.

This brief proposes a 900-MHz novel CMOS-reconfigurable stack rectifier (RSR) implemented in a three-stage cross-coupled differential rectifier (CCDR) for battery-assist Internet-of-Things (IoT)/wireless sensor network (WSN) applications. A three-mode RSR is incorporated for an extended dynamic range (DR) input power level with a 100-$\text{k}\Omega $load, fabricated in the 130-nm CMOS. The realized RSR achieves a wide DR power conversion efficiency (PCE) by reducing the ON-resistance (${R} _{\mathrm{\scriptscriptstyle ON}}$) in the low-power zone (LPZ) achieved by reducing the threshold voltage (${V} _{\text {th}}$) of the device and alternately increasing${V} _{\text {th}}$in the high-power zone (HPZ) by implementing the proposed reconfigurable stack transistor technique along with the multithreshold voltage (MTV) technique. The circuit observes a measured result of 47.91% in peak PCE at an input power of −14 dBm by driving a 100-$\text{k}\Omega $load. The proposed circuit also achieved 22.8 and 16.3 dB of DR with a PCE over 20% and 30%, respectively. Compared to other state-of-the-art designs, our work exhibits better DR and PCE.

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). Incorporating a transformer-based harmonic-rich shaping voltage-controlled oscillator (VCO), the proposed S-PLL prototyped in a 65-nm CMOS, operates at 3.6 GHz and scores an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, it also exhibits a jitter-power figure-of-merit (FOM) of −258.7 dB. The measured reference (REF) spur is −80.34 dBc at$f_{\mathrm {REF}}$and −75.17 dBc at$2f_{\mathrm {REF}}$, respectively.

This paper proposes a hybrid boost converter for $\gt100V$ LED lighting applications. The proposed boost converter uses one flying capacitor to reduce the switch voltage stress, average inductor current, and inductor current ripple, and also to prolong the duty cycle (D) for the same voltage conversion ratio (M). Therefore, the proposed topology has reduced switching, conduction, and core losses, exhibiting also an enhanced step-up capability. Hence, the proposed boost converter considerably improves the power conversion efficiency (PCE), with M=(2–D)/(1–D). Besides, the proposed boost converter automatically sets the voltage on the flying capacitor to VOUT– $\mathrm{V}_{IN}$. Here, we simulate both the conventional and the proposed boost converters in Cadence Spectre with commercial device models. The proposed boost converter improves the peak PCE from 96.8% to 97.4%, with ${V}_{IN}=24V, V_{OUT} =103.5V$, and IOUT=1 A. That is equivalent to 18.75% total loss reduction.

This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

This paper presents a fast transient response flipped voltage follower (FVF) low-dropout regulator (LDO) for high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs), enabled by a direct-coupled auxiliary loop (DC-AL) with replica load. The proposed auxiliary loop consists of an additional power MOS directly controlled by a replica load, which imitates the response of the main loop but scaled down for low power and compact area. This low die cost solution enables a fast transient response from the LDO that well suits a high-speed SAR ADC. The concept, verified in a 12bit VCM-based SAR ADC in 65nm CMOS, operates at 100 MS/s under a 1.2 V supply. The simulation results demonstrate that the DC-AL scheme improves the worst-case DNL and INL from 2.05/-1 LSB and 1.91/-1.83 LSB to 0.43/-0.46 LSB and 0.56/-0.52 LSB, respectively. The LDO with the DC-AL as the reference buffer consumes 0.65 mW with only 0.5 pF of decoupling capacitance, while the DC-AL spends only 0.08 mW.

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200$\mu \text{W}$low-phase-noise inverse-class-F (class-F−1) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868fsrmsjitter in a fractional-N channel when consuming only 529$\mu \text{W}$, corresponding to a figure-of-merit (FoM) of −244dB.

Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the$\Delta \!\Sigma $loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.

This paper presents a supply-noise-robust PLL that achieves low-jitter performance within full-spectrum supply interference. A digital-regulated supply noise cancellation (DSNC) scheme suppresses the large amplitude supply noise within an adequate range for a supply-noise-insensitive (SNI) VCO. It ensures that the low pushing factor SNI-VCO only induces a decent amount of phase noise falling within the effective correction range of the phase noise cancellation (PNC). A sample-and-isolate-based (S/I)-PNC cascaded at the VCO output enables a wider correction range for a fine supply noise and phase noise suppression. Fabricated in 28-nm CMOS with an area of 0.088 mm2, the proposed PLL consumes 6.65 mW from a 1 V supply at 4 GHz output. With 20 mVpp supply interference, the prototype obtains a maximum >37 dB output spur reduction at 5 MHz and maintains ≤1.6 ps RMS jitter in the worst case. The suppression performance degrades less than 10% within −20 °C to 80 °C operation temperature.

Being an indispensable technique in the standard laboratory, Nuclear Magnetic Resonance (NMR) is a versatile method to non-invasively observe the atomic and molecular information of the samples containing non-zero spin nuclei. Yet, the bulky and costly hardware for NMR impedes their broad distributions outside the laboratory for on-demand and on-line usage. In recent years, with the advance in microelectronics, NMR systems equipped with customized silicon chips emerged to achieve system miniaturization with performance enhancement, and pioneer novel applications that were not feasible before using discrete NMR electronics. This article overviews the hardware for NMR from the system-level perspective, and examines the latest developments using integrated circuits over the past decade. Also, we present in detail the design considerations of the transmitter and receiver that are the cornerstone of micro-NMR systems.

This paper presents a millimeter-wave NMOS-PMOS-complementary (CMOS) VCO with a multi-resonantResistor-Inductor-Capacitor-Mutual Inductance(RLCM) tank. It features an 8-port multi-tap inductor with the switched-capacitor arrays to generate and align the 1$^{{\text {st}}}$, 2$^{{\text {nd}}}$and 3$^{{\text {rd}}}$harmonic resonances; all exhibit high impedance and high intrinsic quality factor to improve the absolute phase noise (PN) at both the flicker and thermal regions. The inductor of the RLCM tank introduces a metal resistor technique to fully prevent the mode-ambiguity issue during the VCO startup. Meanwhile, we first propose a detailed analysis of the upper and lower bound of the metal resistor, which is verified by the theoretical analysis, and circuit simulation. Prototyped in 65-nm CMOS technology, the VCO scores a PN@1MHzdown to −111.41 dBc/Hz with a power consumption of 11.1 mW at 1 V; it corresponds to a FOM@1MHzup to 189.4 dBc/Hz over a 15.2% tuning range (24.62 to 28.66 GHz), while exhibiting a low 1/$\text{f}^{3}$PN corner between 480 to 730 kHz.

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that requireCR$D \ge0.5$control does not allow$D$to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows$D < 0.5$without overstress or imbalance issues, thus extending theCRrange and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3CRCRexpressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively.

The Hybrid DC-DC converter, especially with multiple inductors targeting high current delivery, has the advantages of high efficiency and power density with a large voltage conversion ratio (VCR), due to the combination of the benefits of both switched-capacitor-based and inductor-based buck converters. However, a higher number of inductors means that the energizing time for each inductor has more limitations, resulting in a relatively narrower VCR range. To reduce the conduction loss and extend the voltage conversion ratio scope, this paper presents a symmetrical double step-down (SDSD) converter with a VCR range up to 1/3, regulating an output voltage interval of 0.5 V-0.8 V from a 2.7 V-4.2 V Lithium-ion battery. This converter, implemented in 65 nm CMOS, occupies a core active area of 1.53 mm2. This work obtains 86.5% peak efficiency and 326 mA/mm2 maximum current density, with an effective switching frequency of 3 MHz.

This paper presents an entropy-source-preselection-based strong PUF (ESP-PUF). Through the presented entropy-source-preselection scheme, we will convert first the input challenge bits of the ESP-PUF into the entropy selection signals through the front-end selection network, realized based on an XOR tree. Then the entropy selection signals serve as the power-on indicator to randomly select the back-end entropy sources to generate the raw responses. Utilizing this preselection scheme, we can fulfill both ultra-low power and strong resilience to machine learning (ML) attacks. An effective randomness-enhancement block amplifies the randomness of the raw responses thus alleviating their bias. Moreover, we propose an obfuscation-based protection mechanism to further protect the root challenge-response pairs (CRPs) of the entropy sources and enhance the resilience to ML attacks. Fabricated in 65nm CMOS LP technology, the proposed ESP-PUF shows a high energy efficiency of 0.46pJ/bit. Meanwhile, it demonstrates an average bit-error rate (BER) of 5.83% in the worst-case for the temperature range of −20°C to 120°C and a supply voltage variation of ±10%. The proposed CRPs filtering method can suppress the worst-case BER to a value$< 6.7\times 10 ^{-6}$, presenting high stability. The proposed ESP-PUF occupies an active area of 0.0122 mm2. After training for 1M CRPs samples, the prediction accuracy of the adopted ML algorithms is still ~50%, confirming a strong resilience of the proposed ESP-PUF.

This paper presents a weak PUF-assisted strong PUF that combines the metrics between weak and strong PUFs. Unlike the conventional strong PUFs that rely on the nonlinear combination of a large number of entropy cells for high modeling attacks resilience, the presented strong PUF utilizes unique key streams to bitwise encrypt the raw responses from the conventional strong PUF to facilitate an inherent immunity to modeling attacks thus fulfilling high-level security. A device-specific pseudo-random number generator (P-RNG) configured by a dedicated weak PUF array generates a unique key stream (K). Since the weak PUFs are inherently immune to machine learning or deep learning-based modeling attacks, the final encrypted responses of the proposed strong PUF are also inherently immune to modeling attacks. Moreover, we propose a two-to-one (2-to-1) selection scheme and the digitally-controlled-delay-line (DCDL)-based stability checker to suppress the bit-error-rate (BER) of the weak PUF array and improve the efficiency of the spatial majority voting (SMV)-based error correction scheme, thus achieving high stability for our proposed strong PUF. Fabricated in 65nm CMOS GP technology, the proposed weak PUF-assisted strong PUF shows a high energy efficiency of 3.05 pJ/bit at a 2M bit rate. Meanwhile, it demonstrates an ultra-low average worst-case BER of$8.9 \times 10^{-11}$for the temperature range of −20°C to 120°C and a supply voltage variation of ±10% with the proposed stabilization schemes. The proposed strong PUF occupies a core area of 0.075mm2.

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the$\text{V}_{\mathrm {OUT}}$error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2-$\mu \text{V}$/mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.

This paper describes a low-power multiband blocker-tolerant receiver (RX) with three steps of filtering among two transconductance (Gm) stages. To consistently achieve low noise figure (NF) and high linearity over a wide range of operating frequency, a single-Gm low-noise amplifier (LNA) heads the RX with embedded N-path filtering, and feed-forward out-of-band (OB) blocker cancellation to surmount the tradeoff between the passband bandwidth (BW) and OB rejection without sacrificing the power budget. A filtering-by-aliasing (FA) block embeds another single-Gm baseband (BB) amplifier to allow a steep roll-off lowpass response with a clock-rate-defined passband BW. Prototyped in 28-nm CMOS, the RX achieves a 3.1-dB NF and a 5.4-dBm OB-IIP3 at 2 GHz, while consuming only 22 mW, measured at a gain of 22 dB. The tunable passband BW is 2.5 to 20 MHz, and the RF-to-BB composite filtering slope is 20 to 50 dB/10 MHz at 1.75xBW offset. The RX occupies a 0.24 mm2active area.

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved$2\times $charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica$V_{\mathrm {EB}}$generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.3mV/V or 0.66%/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a$3\sigma / \mu $variation of 1.37% before trimming, while 0.25% after applying one-point trimming at 20°C.

This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of${D}$/(1$+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz.

This paper proposes a 3rdorder continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2ndorder noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1storder NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band phase noise and RMS jitter. The proposed gain-boosting RSPD converts the phase error to the voltage error and utilizes a passive switched-capacitor voltage multiplier to amplify the sampled voltage error, which effectively increases the gain of the RSPD. The boosted RSPD gain helps suppress the phase noise contributed from the gm cell. To prevent the transistors in the gain-boosting RSPD and gm cell from breakdown, the gain-boosting function is only activated during the locked state when the phase and voltage errors are small. The switching between the gain-boosting and normal modes is realized automatically by monitoring the sampled voltage and comparing it with a pre-defined threshold window. Fabricated in 65-nm CMOS, the type-II RS-PLL measures an RMS jitter of 54 fs at 6.75 GHz and consumes 7.1 mW, corresponding to a jitter figure-of-merit (FoMjitter) of −256.8 dB. The measured reference spur is −62.6 dBc, and the active area is 0.25 mm2.

This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of$6845\mu \text{m}^{2}$. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across$1.06\sim 1.55V$and$- 30\sim 125^{\circ }\text{C}$, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using$80\times 80\times 80$artificial neural network (ANN) with 1M CPRs as training set.

This brief presents a novel circuit architecture for a Dickson-based reconfigurable rectifier with wide power dynamic range (PDR). Besides, a novel figure of merit (FoM) concerning the reconfigurable rectifiers is formulated to provide a more comprehensive assessment of the rectifier’s performance. The proposed reconfigurable design improves the operating range of the rectifier by adaptively switching between the six-stage configuration during low-power operation and the 12-stage configuration during high-power operation. Fabricated in 130-nm CMOS, the proposed reconfigurable rectifier measures a PDR of 14 dB with a peak power conversion efficiency (PCE) of 34.93% for 1-$\text{M}\Omega $load operating at 900 MHz. Relative to the recently published reconfigurable rectifiers, our design records the highest FoM of 36.98 dB/mm2, with minimum harvesting downtime.

This article describes a fully integrated CMOS radio frequency energy-harvesting (RFEH) front end. It features an on-chip stacked step-up transformer integrated with a cross-coupled differential drive (CCDD) rectifier to enhance the input sensitivity. The transformer also serves as an on-chip balun for the CCDD rectifier. The CCDD rectifier innovates a gate-biasing technique and realizes coupling capacitors at the end of each stage to increase the subsequent stage biasing. Here, our RFEH front end operating at 900 MHz achieves an improved sensitivity of −20 and −19.2 dBm at the 1-V output for no-load and a 1-$\text{M}\Omega $load, respectively.

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms(1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only$90~\mu \text{W}$associated with the FLL.

This paper presents a transformer-based harmonic- rich-shaping voltage-controlled oscillator (VCO). Its active core features noise suppression and circulation to improve the phase noise (PN) performance, and its 2:2 transformer allows a very short common-mode (CM) return path without sacrificing the tank's quality factor. The proof-of-concept prototype is a 3.52GHz VCO in 65-nm CMOS. It scores a -151-dBc/Hz PN at 10MHz offset, and consumes 6.77 mW of power at a 0.7-V supply. The achieved Figure-of-Merit (FOM) is 187.8/192.3/193.7 dBc/Hz at 0.1/1/10-MHz offsets, with a 1/f3PN corner of 220 kHz. Over a 22.1% tuning range, the VCO upholds a consistent FOM of >193.3 dBc at 10-MHz offset, and a 1/f3PN corner of2.

This paper presents a discrete-time multi-stage noise shaping (MASH) delta-sigma modulator (DSM) with second-order digital noise coupling for wideband highresolution applications. By directly injecting the output of the second loop into the quantizer input of the first loop while choosing an appropriate signal transfer function of the second loop, a second-order digital noise coupling can be easily constructed without almost imposing any hardware complexity. With the help of the second-order digital noise coupling, the inherent quantization noise leakage in the MASH topology is significantly mitigated, thus resulting in less DC gain requirement for the integrators. Mathematical analysis and further simulation results are presented to demonstrate the effectiveness of the proposed MASH structure.

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rdNyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor ( 3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of -63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of -241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO's phase noise (PN), leading to an in-band PN of -116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2.

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is <; 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes.

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50$\text{k}\Omega $load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a$\sim 1.6\times $improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme.

Nowadays, automated guided vehicle (AGV) has been a key role of manufacturing and logistics, required to work with high automation. It is essential to guarantee the charging reliability of AGV for all-day work. However, in wireless battery charging applications, to utilize load-independent-current and load-independent-voltage transfer characteristics for constant current (CC) and constant voltage (CV) outputs respectively, existing inductive power transfer (IPT) converters either hopping the operating frequencies or switching the hybrid compensation topologies, resulting in necessity of state-of-charge detection and feedback control for the operating frequency hopping or the compensation topology switching. To improve the charging reliability of AGV by eliminating these active controls, this paper proposes an IPT converter with inherent CC-to-CV transition ability that can comply with the required charging profile of the batteries. Unity-power-factor design is also considered to minimize the voltage-ampere rating. This solution is passive, and control is unnecessary, so donating great reliability in automated guided vehicle. Experimental results are presented to verify the methodology and the performance.

This paper describes a low complexity illumination-invariant motion vector detection algorithm based on logarithmic edge detection and edge difference without periodic threshold adjustment. A logarithmic edge detector is employed to achieve accurate object movement over a wide illumination range. The threshold for edge detection is determined by one-time background logarithmic gradient extraction. Finally, the difference of the logarithmic edge of 3 consecutive frames is employed in a frame difference-based motion template model to obtain the motion vector. Experimental results show that the proposed algorithm achieves a motion vector detection accuracy of ~90% over an illumination level change of 80%.

This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N2average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively.

In this paper, we present a novel multiple-stage amplifier chain based strong physical unclonable function (PUF) with low power and energy consumption. Based on the proposed two-dimensional subthreshold amplifier array, 12 different amplifiers can be selected through the analog multiplexer at each column. As a result, a 12-stage amplifier chain can be formed by applying different challenges to the aforesaid analog multiplexers with a linear feedback shift register (LFSR). Due to the inevitable process variation, the output voltage of the amplifier chain's last stage varies depending on the various combinations of the selected amplifiers, whose number features an exponential relationship with the size of the adopted amplifier array. By using 65nm standard CMOS process, the proposed strong PUF implementation is validated with high reliability and randomness. According to our extensive simulation results, the averaged bit error rate (BER) per 10°C and BER per 0.1V are calculated to be 3.15% and 3.85% for the operating temperature range of -20°C~120°C and supply voltage range of 0.9V~1.4V, respectively. Meanwhile, the proposed strong PUF's high randomness is also verified by passing both the NIST and auto-correlation function (ACF) test suites. Moreover, featuring an excellent uniqueness of 49.54%, the overall power consumption is simulated to be 0.128μW at the throughput of 0.02Mb/s, which corresponds to an energy consumption as low as 6.4pJ/bit.

This article proposes two linearization techniques in improving the third-order input intercept point (IIP3) of a balun-low-noise amplifier (LNA) mixer. First, the intrinsic third-order intermodulation (IM3) product of the inductively source degenerated (ISD) transconductor from the second-order derivative transconductance component (g"m) is reduced by tailoring toward the optimum biasing point at the moderate-inversion region. Second, the generated IM3 current by the first-order derivative transconductance (g'm) due to the interaction with the feedback component in the ISD transconductor is attenuated by second-harmonic injection via the bulk of the ISD transconductor. Furthermore, a transformer-based gate inductor and a transformer-based balun are applied to improve the input impedance matching and produce a balanced differential input signal. Measured results in 0.13-μm CMOS show a high IIP3 of +16 dBm and a conversion gain (CG) of 22 dB at 2.4 GHz. The double-sideband (DSB) noise figure (NF) is 7.2 dB, and the power consumption is 3.15 mW at 1.2 V.

This article reports a novel differential-folded mixer with multiple-feedback techniques for performance enhancement. Specifically, we introduce the capacitor cross-coupled (CCC) common-gate (CG) transconductance stage to improve the noise figure (NF) at low power by boosting the effective transconductance, while enhancing the linearity via suppressing the second-order harmonic distortion. Typically, the created loop gain of the CCC can raise the third-order intermodulation (IM3) distortion, penalizing the input-referred third-order intercept point (IIP3). Here, we propose a positive and a second capacitive feedback into the CCC CG transconductor, not only to suppress the IM3 distortion current but also adds in design flexibility to the input transistors. Furthermore, the positive feedback also improves the input impedance matching, conversion gain, and NF through a flexible design criterion. Prototyped in a 0.13-μm process, the proposed mixer operating at 900 MHz dissipates 4 mW at 1 V. The measured double sideband (DSB) NF is 8.5 dB, the conversion gain (GC) is 18.4 dB and the IIP3 is +12.5 dBm.

This paper presents an input correlated swap-sampling (ICSS) technique, which correlates the initial voltage of the sampling capacitor with the incoming input signal before the sampling phase; therefore, significantly reducing the power dissipation of the input driver. The concept can be easily implemented in a two-step conventional SAR ADC that costs a negligible circuit overhead and extra power consumption. According to theoretical analysis, the proposed ICSS scheme saves up to 77.8% or 12.3% power of the input driver when compared to conventional or recently reported works, respectively. The ICSS approach has been verified in a 12 bits SAR ADC in 28 nm CMOS, operating at 25 MS/s under 0.9 V supply. The simulation results demonstrate that the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.3dB @ Nyquist frequency, leading to a FoM of 3.4 fJ/conv.step.

This paper provides an in-depth analysis of the third-order bang-bang clock and data recovery (BBCDR) circuit, which accurately predicts its operating characteristics, namely, the jitter transfer function (JTF), the jitter tolerance (JTOL), and the jitter generation (JGEN). By formulating the time-domain waveforms, we introduce a characterizing method and also derive the closed-form equations and their simplified versions under specific conditions, which are related with the second-order loop filter (LF). Our framework is consistent with the conclusions of the prior works. Also, we discuss through the time-domain behavior, the sinking area of the JTOL and other specific phenomenon appearing in the third-order BBCDR loop. We verify all above prediction by system-level simulations with the MATLAB/simulink model.

This brief presents a time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) with an improved variance-based time-skew estimation technique, where we introduce a window detector (WD) based on a SAR ADC. It brings low hardware overhead and 104times faster convergence speed when compared to the prior variance-based time-skew calibration. Postlayout simulation results of a 10-bit, 2-GS/s TI-ADC in 28-nm CMOS process verify the effectiveness of the proposed calibration. The results indicate that the signal noise and distortion ratio/spurious free dynamic range of the ADC improved from 41.9/48.6 to 53.2/63.3 dB after calibration. The total area and power are 0.105 mm2and 14.9 mW, respectively, where the WD occupies 0.0015 mm2and 0.55 mW.

In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the automatic sizing of radio frequency integrated circuit blocks, where an all-inclusive test bench formulation enhanced with an additional measurement processing system enables the optimization of “everything at once” toward its true optimal tradeoffs. VCOs embedded in the state-of-the-art multistandard transceivers must comply with extremely high performance and ultralow power requirements for modern cellular and Internet of Things applications. However, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches, and/or analysis must be considered simultaneously. Here, the dual-mode design and optimization conducted provided 287 design solutions with figures of merit above 192 dBc/Hz, where the power consumption varies from 0.134 to 1.333 mW, the phase noise at 10 MHz from -133.89 to -142.51 dBc/Hz, and the frequency pushing from 2 to 500 MHz/V, on the worst case of the tuning range. These results pushed this circuit design to its performance limits on a 65-nm CMOS technology, reducing 49% of the power consumption of the original design while also showing its potential for ultralow power with more than 93% reduction. In addition, worst case corner criteria were also performed on the top of the worst case tuning range optimization, taking the problem to a human-untrea table LXVI-D performance space.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

Nowadays, with global development in Internet of Things (IoTs), electricity, water, and gas information readings should be done in a convenient way. However, existing smart electric meters (SM) mainly focus on the information of financial transactions (the energy bill), whereas little effort has been done to promote the instrumentation dimension of the metering infrastructure. In this paper, we propose and develop a power quality indexes (PQIs) measurement system platform with remote alarm notification for electrical systems. Compared with the existing state-of-the-art, the proposed platform requires less development and maintenance cost, exhibiting higher flexibility. In this system we include the main power quality indexes, including root-mean-square (RMS) value, active power P, reactive power Q, apparent power S, power factor (PF), fundamental power factor (PF1) and total harmonic distortion (THD). To acquire those power quality indexes, we use a anticonjugate decomposition cascaded delayed signal cancellation (ACD-CDSC) technique. At last, we provide the experimental results of PQIs in a single-phase system to verify the effectiveness of the measurement platform with remote alarm notification in comparison with the Fluke power quality analyzer.

This paper presents a dual-loop digital low-dropout regulator (DLDO) with asynchronous-flash (AF) binary coarse tuning for fast transient response. In steady state, the DLDO operates with a unary-weighted low power fine-tune loop to improve the regulation accuracy. Besides, a freeze mode is also employed to further reduce the power budget and to eliminate the limit cycle oscillation phenomenon. When a load-transient is detected, the proposed AF bidirectional shift register will direct the binary-weighted power switches for coarse and fast tuning. The prototype is fabricated in a 28nm bulk CMOS process. With VIN=0.5V and 50mV dropout, the AF-DLDO can deliver 33mA output current and consume only 10.5μA quiescent current. We measured 102mV voltage undershoot for a 30mA/20ns load step, showing a 0.11ps FOM.

Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (-30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.

This paper presents a single-stage wireless charger using a current-mode active rectifier with accurate output current regulation for efficient wireless charging. As we know, the rectifier processes an AC input voltage/current and a pulsing output current which are difficult to be accurately sensed on chip with small area and power overheads. The proposed current sensing technique uses a replica sensing stage in parallel with the main power stage. It consists of two small cross-connected sensing PMOS transistors, a small filtering capacitor, and a dynamic replica load. In addition, by adaptively tuning the delay of the power NMOS driving signal, the charging current is regulated precisely. This single-stage wireless charger operates at 6.78MHz, and is designed in a 0.35μm CMOS process. Simulation results show a minimum 97.5% current regulation accuracy over a 10× (from 100mA to 1A) output-current range. The peak efficiency of 94% is achieved with 4.2W output power.

A 3-level boost (3LB) converter has the characteristics of higher voltage conversion efficiency, lower inductor current ripples, output voltage ripples and voltage stresses on switches when compared with the conventional boost converters in continuous conduction mode (CCM). When the 3LB is integrated on a chip, we cannot avoid its discontinuous conduction mode (DCM) operation due to a small inductance and load variation. In this paper we'll present and discuss the design and control of a 3LB converter in DCM operation, implemented in a 65-nm CMOS process. Transistor level simulation results show that it operates at 100 MHz with a 5nH inductor, a 4nF output capacitor and a 2.5nF fly capacitor achieving an output conversion range of 1.5 V to 2.1V from a 1.2 V input supply, with a peak efficiency of 83.2%@90mW, a load transient response of 141mV and 1.64ns/mA for undershoot, 136mV and 1.93ns/mA for overshoot, and a voltage ripple less than 60/85mV when ILoad =40/80mA with a typical and the maximum output voltage ripple of less than 90mV in the worst corner.

This brief reports a passive noise-shaping (PNS) scheme for successive approximation register (SAR) analog-to-digital converter (ADC) based on the two-step integration with passive gain and comparator gain techniques. The analysis shows that the proposed method achieves a better noise-shaping (NS) efficiency than prior arts, which enhances the noise attenuation by 14 dB. A design example is provided which further adopts the delta-sampling technique to relieve the conversion efficiency loss due to the oversampling in the NS SAR ADC. The efficiency of the proposed PNS scheme and the performance of the ADC are verified by simulation achieving a 13.2 effective number of bits with a 10-b ADC architecture and eight conversion cycles for a signal bandwidth of 2 MHz sampled at 100 MS/s. The calculated Schreier figure of merit (FoM) and Walden FoM are 176.8 dB and 16 fJ/conv.-step, respectively.

This paper presents the DC analysis of the Negative Output Elementary Luo Converter (NOELC), which includes the continuous-conduction mode (CCM) voltage gain and the boundary condition between the CCM and the discontinuous-conduction mode (DCM). The main features of the NOELC are the high gain with small ripple and the reverse output. Additionally, we address the parameters design of the NOELC and propose an output voltage ripple estimation method. Through MATLAB Simulink simulation, we further demonstrate that the parameters design and the output voltage estimation method can achieve more accurate results when compared with those from the conventional one.

For ultra-low-power radios, the long startup time of the crystal oscillator dominates their on-off latency and limits their power efficiency. This paper describes the design of a 65nm CMOS 16MHz crystal oscillator, featuring a momentary detuning scheme to accelerate the startup transient. Specifically, during the startup phase, the bias current (266μA) and loading capacitors (8.5pF each) are enlarged concurrently such that the equivalent negative resistance of the oscillation loop can be momentarily enhanced, resulting in 74-fold reduction of the startup time (37ms → 0.5ms), while consuming just 53.2nJ at 0.4V. Also, a time-based controller automatically drives the oscillator into the steady state, which entails a smaller bias current (12μA) to sustain the oscillation, and smaller loading capacitors (5pF) to recover the proper oscillating frequency. The simulated phase noise exhibits -128.2dBc/Hz at 1kHz offset, resulting in a FoM of 265.5dBc/Hz.

In this paper, a piecewise bipolar junction transistor (BJT) process spread compensation scheme is presented. By exploiting the strong correlation between the BJT saturation current and the piecewise base recombination current, the process spread and proportional-to-absolute-temperature (PTAT) drift of the base-emitter voltage (Vbe) can be reduced over a wide temperature range. Fabricated in standard 0.18-μm CMOS, the chip prototype achieves a measured Vbe standard deviation (STD) of 1.1 mV (1.8 mV) from -30 to 60 °C (-30 to 120 °C) over 12 samples, corresponding to a 2.9X (1.8X) improvement when compared to the measured Vbe STD of 3.24 mV at 25 °C from 15 standalone BJT samples with constant external bias current using the same process.

A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back end. This architecture achieves high speed, while preventing the interleaving spurs. In addition, the design considerations and calibration techniques for gain and offset are also introduced. A histogram stage gain error (HSGE) calibration is implemented to correct the conversion nonlinearities in the digital domain. Measurement results on a 65-nm CMOS prototype show an signal-to-noise distortion ratio (SNDR) of 55.9 dB at dc input and a figure of merit (FoM) of 32 fJ/conversion step at 1.2 V supply.

This paper discusses the use of a low gain amplifier and a passive switched-capacitor (SC) network to enable the SC integrator function. The method is applied to a delta-sigma modulator to achieve high resolution as proved by the 65-nm CMOS technology test vehicle. Compared with the conventional operational amplifier (op-amp)-based SC integrator, this solution utilizes a low-gain open-loop amplifier to drive a passive SC integrator with positive feedback. Since the open-loop amplifier requires a low dc gain and implements an embedded current adder, the power consumption is very low. Power reduction for single bit is obtained by using passive feedforward with built-in adder to assist the first amplifier. The low swing obtained at the output of the active blocks relaxes the slew rate requirement and enhances the linearity. Implemented in 65-nm digital CMOS technology with an active area of 0.1 mm2, the test chip achieves a dynamic range of 91 dB, peak signal-to-noise ratio of 88.4 dB, peak signal-to-noise-plus-distortion ratio of 88.2 dB, and a spurious free dynamic range of 106 dB while consuming 73.6 μW in a 25-kHz signal bandwidth at 1 V supply, yielding a FoMWaldenof 70 fJ/conv-step and FoMSchreierof 176 dB.

This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18-μm CMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. With a power consumption of 147-375 nW at 0.45 V, the proposed ECG processor exhibits a wide compression ratio ranging from 2.89 to 26.91, corresponding to a percentage-RMS-distortion from 0% to 3.11%.

This brief presents a 7-bit 700-MS/s four-way time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A partial Vcm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. Compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. In addition, the impacts of such a reduction on the comparator offset, noise, and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in a 65-nm CMOS technology occupies an active area of 0.025 mm2. The measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio of 40 dB at Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden FoM of 48 fJ/conversion step.

This paper proposes a hardware-efficient time-domain scheme to digitally compensate the I/Q imbalance and LO feedthrough (LOFT) of a sub-GHz wideband transmitter for the IEEE 802.11af WLAN. A simple envelope detector is the only analog part. The parameters are updated by Least-Mean-Square and estimated efficiently in time domain by using COordinate Rotation DIgital Computer (CORDIC), saving the training time and power consumption. The measured wideband image-rejection ratio (IRR) and LO-leakage-rejection ratio (LRR) are improved from 18.9 to 41.3 dB, and 20.4 to 37.9 dB, respectively.

This paper describes a power-efficient processor for extracting the timing of QRS complex from digitized ECG, based on the hardware-efficient architecture of quadratic spline wavelet transform (QSWT) and maxima modulus pair recognition (MMPR). The processor succeeds in saving the wireless system's power by 6×.

This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-μm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V.

This paper proposes a dual-layer patterned floating shield (DL-PFS) technique for Silicon-based on-chip spiral inductors. By optimally utilizing the two lowest metal layer strips to shield the inductor from the substrate, electromagnetic (EM) simulations show 40% improvement of the Q factor when compared with the conventional approach. Designed and simulated in 0.13-μm CMOS, the DL-PFS inductor in a class-B VCO achieves 6.6-dB lower phase noise, and 34% power savings. The VCO also exhibits 9.7-to-10.93 GHz tunability, and -123-dBc/Hz phase noise at a 3 MHz offset. The power consumption is 1.64 mW at 0.6 V, leading to a state-of-the-art FoM of 190.5 dBc/Hz.

This brief reports a 120 MS/s 12-bit successive approximation register analog-to-digital converter (ADC). The conversion nonlinearity in a bridge digital-to-analog converter is analyzed, and its corresponding histogram-based ratio mismatch (HBRM) calibration is presented in detail. Verified by behavioral simulations as well as measured results, the solution improves both the dynamic performance and the static performance of the ADC. The measurement results demonstrate that the HBRM calibration effectively improves the signal-to-noise distortion ratio from 56.9 to 63.7 dB at dc input, with a sampling frequency of 120 MS/s.

This brief presents a uniform quantization theory (UQT)-based digital-to-analog converter (DAC) linearity calibration for a successive approximation register (SAR) analog-to-digital converter. According to the uniform quantization noise property, the nonlinearity due to the parasitics in an LSB array of the split-DAC structure is estimated and corrected in the digital domain. The calibration requires that the characteristic of the input signal must fulfill the prerogative of the quantization theory. The advantages lie in its low design complexity with no additional analog circuit modification. The proposed calibration is verified by both behavioral simulations and measured results in an SAR ADC. The measurements are based on a prototype implemented with large nonlinear split-DACs, which demonstrate that the UQT-based linearity calibration can effectively improve the Signal to Noise and Distortion (SNDR) from 56.9 to 63.3 dB at dc input with a sampling frequency of 120 MS/s.

Ultralow-energy biomedical applications have urged the development of a subthreshold VLSI logic family in standard CMOS. This brief proposes an unbalanced pull-up/down network, together with an inverse narrow-width technique, to improve the operating speed of the individual logic cell. Effective logical efforts save both power and die area in the process of device sizing and topology optimization. Three experimental 14-tap 8-bit finite impulse response filters optimized for ultralow-voltage operation were fabricated in 0.18-μm CMOS. Measurements show that the optimized 0.45 and 0.6 V libraries achieve minimum energy operations at 100 kHz, with a figure-of-merit of 0.365 (at 0.31 V) and 0.4632 (at 0.39 V), respectively. They correspond to 35.96% and 18.74% improvements, and the overall performances are well comparable with the state of the art.

The die size of multistandard wireless transceivers in ultrascaled CMOS is dominated by the baseband low-pass filters (LPFs), which typically count on passive-RC components to define the time constant. To break this area constraint, this paper revisits the active switched-capacitor (SC) LPF for its united benefits of clock-rate-defined bandwidth, accurate cutoff frequency, and small die size due to capacitor-ratio-based sizing and no spare elements. The key challenges of active-SC LPFs are the speed- and linearity-to-power tradeoffs, which are addressed by two circuit techniques: 1) switched-current assisting (SCA) and 2) precharging (PC). The SCA accelerates the charging speed of the integration capacitor, while the PC improves the linearity when charging the load capacitor. Three prototypes (first order, biquad, and fifth-order Butterworth) fabricated in a 65-nm CMOS process validate the feasibility of the proposed SCA and PC techniques.

A novel current mode Capacitor Based Sine-Shaped (CBSS) Digital-to-Analog Converter (DAC) for Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators, enabling smooth zero current transitions and greatly reducing the clock jitter noise, is described. The circuit is switched capacitor based and uses a cosine-wave voltage reference instead of constant current. The output is a sine-shaped waveform with precise zero transitions. Locking the reference cosine-wave voltage and the clock employed for data sampling ensures a virtual immunity to clock jitter. The use of a cosine-wave as reference and a constant capacitance loading the reference generator facilitates impedance matching thus making the scheme suitable for very high sampling rate. Moreover, the good matching between capacitors determines the accuracy of the integrators' time constant and multi-bit linearity of the proposed DAC. The feature of the method has been verified with behavioral simulations and tested in a second order ΣΔ modulator.

Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1ststage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency, DC gain, dc offset and noise performances. Optimized in 0.18μm CMOS via a low-power design procedure, the amplifier achieves >90dB DC gain, 4.5MHz unity-gain frequency and 57.2° phase margin at a 100pF capacitive load. The average slew rate and 1% settling time are 2.68V/μs and 0.239μs, respectively. The amplifier draws 22μA at a 1.2V supply.

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and Vcm-based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using Vcm-based switching.

This paper describes an ultra-low-voltage low-power 8-phase voltage-controlled oscillator (VCO) for 10GHz beam-forming satellite receivers. It is composed by four 0.5V current-reuse LC-VCO cells inter-locked by direct-back-gate coupling, featuring independent sizing of coupling strength and frequency tuning, while avoiding the risk of forward bias the substrate p-n junctions. Optimized in 65nm CMOS, the 8-phase VCO draws only 2mW. The phase noise at 1MHz offset is -114dBc/Hz to -110dBc/Hz over a 32.5% tuning range from 8.55 to 11.88GHz. These results correspond to a high-and-stable FOM within -188 to -189.5dBc/Hz.

In this paper, a new VCO-assisted VCO-based sigma-delta (ΣΔ) modulator is proposed to improve the linearity of the VCO-based quantizer. The assistant network in the digital feedforward path reduces the input swing of the VCO-based quantizer in the main path, and then adds it together through the digital cancellation path to keep the same signal before and after quantization. Moreover, the merit of the auxiliary VCO increases the tolerance to DAC mismatches because of its intrinsic DEM function, which also simplifies the digital circuit part. A first order continuous-time (CT) ΣΔ modulator with the proposed structure is designed and simulated in a 65nm CMOS process. The performance of the modulator can reach 76.6dB/82.4dB SNDR/SNR with second order noise shaping and 84dB DR within a 10MHz bandwidth and a sampling frequency of 1.4GHz, consuming 9.4mW of power.

This paper describes a neural recording front end for both Local Field Potential (LFP) and Spike Potential (SP) recordings, which range from 0.1 Hz ~ 200 Hz and 200 Hz ~ 10 kHz, respectively. Based on the capacitively-coupled chopper instrumentation amplifier (CCIA) topology, a ripple reduction loop (RRL) is used to suppress the chopping ripple. A DC servo loop (DSL) that utilizes pseudo-feedback to achieve a very small unity gain bandwidth with reduced capacitor size while consuming only 12 nA is proposed. The proposed CCIA is implemented in a standard 0.18 μm CMOS process. Simulation results show that with a total power consumption of 1.525 μA from a 1.2 V supply, a NEF of 2.73 (LFP) and 2.6 (SP) can be achieved.

This paper presents a monotonic multi-switching technique that is implemented in a 8b SAR ADC. The proposed switching reduces 1/2 total DAC capacitance and achieves more than 80% switching energy saving when compared to the most advanced VCM-based or merged capacitor switching methods. Besides, conversion redundancies are added to compensate the errors resulting from insufficient DAC settling and reference noise. The proposed 8-bit SAR ADC operates at 100MS/s with 0.6V supply in 65nm CMOS. The simulation results show that the design achieves 48.8dB SNDR with only 0.524mW power. The Figure-of-Merit (FoM) is 23.35fJ/conversion-step.

A novel structure of VCO-based quantizer for CT ΣΔ modulator is presented which can significantly improve the VCO linearity. Compared to the traditional methods, the proposed structure uses only one VCO in the system and it also maintains the intrinsic Dynamic Element Matching (DEM) function of the VCO-based quantizer. A first order CT ΣΔ modulator with the proposed quantizer is designed and simulated in a 65nm CMOS process. The DAC of the ΣΔ modulator is optimized, which can also save half of the DAC cells. The performance of the modulator can reach 69/67 dB SNR/SNDR and a dynamic range of 78 dB with a bandwidth of 10MHz at 1V supply voltage.

This paper describes a software-defined-radio (SDR) balun low-noise amplifier (LNA) with no explicit bias circuit, inductor or ac-coupling network. It relies on a triple-stage inverter-based amplifier with resistive feedback to maximize the bandwidth and realize single-to-differential conversion. RC degeneration applied at the last gain stage enhances both linearity and output gain-phase balancing. Optimized in 65-nm CMOS the balun-LNA covers the 0.02-to-6-GHz band with S11>;-11 dB, voltage gain of 21.2-dB and noise figure below 3.2-dB. The in-band IIP2 (IIP3) is +36 to +51 dBm (-5.6 to -5.3 dBm). The power consumption is 7.9 mW at 1.2 V.

This paper describes a high-voltage-enabling circuit technique for enhancing the gain precision and linearity of OpAmp-based analog circuits. Without resorting from specialized devices, a 2xVDD-enabled recycling folded cascode (RFC) OpAmp optimized in IV GP 65-nm CMOS achieves, when compared with its 1xVDDcounterpart, 25-dB higher open-loop DC gain and 30-dB higher IM3 (in closed loop), under a similar power budget. These joint improvements save the need of a 2ndstage in the OpAmp when high precision and high linearity are the priorities. A voltage-conscious bias scheme and gate-drain-source engineering ensure that all devices are consistently operated within the reliability limits.

This paper presents a technique to enhance the output balancing precision of a low-noise amplifier (LNA) against balun imbalance. By utilizing two capacitive-cross-coupling common-gate amplifiers in cascode, wideband output balancing, high voltage gain and low noise figure (NF) can be concurrently achieved. A 2.4 GHz LNA design example optimized in a 0.13 μm CMOS process shows that the tolerable balun's gain and phase imbalances are up to 2 dB and 10°, respectively. With just 3.6 mW of power, the NF is 2.6 dB at a voltage gain of 30 dB.

This paper proposes a differential switched-capacitor (SC) biquad filter exploiting a hybrid structure. The 1stactive core is an operational amplifier (OpAmp) whereas the 2ndis an improved comparator-based circuit (CBC). The advantages of this new structure are justified by the reductions of power and transistor sizes. Optimized in a 65-nm CMOS process, when compared with a typical dual-OpAmp design, the proposed filter saves 19% power and 18% transistor area. The filter clocked at 40 MHz achieves 61.7-dB IM2 and 62.5-dB IM3 while drawing 2.23 mA from a 1.2-V supply. This hybrid SC biquad can gain further momentum for filters that request numerous biquads in cascade to attain higher selectivity.

A voltage feedback charge compensation technique is presented to prevent the conversion nonlinearity due to the parasitic effect of split capacitive DAC structure in successive approximation register (SAR) ADCs. The charge compensation is achieved by using an open loop amplifier that performs voltage feedback to the DAC array via a compensation capacitor, which is easy to be implemented with very low power dissipation. The technique is utilized in the design of a 10b 80MS/s SAR ADC in 65-nm CMOS technology. The simulation results show that the proposed charge compensation technique can improve the Effective Number of Bits (ENOB) from 8.3bits to 9.6bits and differential/integral nonlinearity from 3LSB/1.65LSB to 0.45LSB/0.74LSB respectively with only 300 uW power dissipation in the proposed charge compensation circuitry.

This paper describes a 90 nm CMOS low-noise low-power biopotential signal readout front-end (RFE). The front-stage instrumentation amplifier (IA) features a chopper; an AC-coupler and a novel chopper notch filter for minimizing the DC-offset; transistors' flicker noise and 50 Hz powerline interference concurrently. A noise-aware transistor selection (thin- and thick-oxide) in the IA enables a flexible tradeoff between noise and input impedance performances. The 2ndstage is a spike filter clocked by a parallel use of two non-overlapping clock generators, effectively tracking and suppressing the chopper spikes. The last stage is a gain-bandwidth-controllable amplifier for boosting the gain and alleviating different bio-potential signal measurements through simple digital controls. Simulation results showed that the RFE is capable of tolerating a differential electrode offset up to plusmn50 mV, while achieving 140 dB CMRR and 51.4 nV/radicHz inputreferred noise density. The notch at 50 Hz achieves 41dB rejection. The entire RFE consumes 16.55 to 35.5 muA at 3V.

An octave-phase local-oscillator (LO) generator for 170-to-860-MHz mobile-TV tuners is described. It is intended to incorporate with a polyphase mixer scheme for rejecting the 3rdand 5thharmonics of the LO that is critical for wideband reception. The circuit is structured by a cascade of 7 inverter-based phase correctors to generate a set of LO signals with octave phases in an open-loop formation, resulting in 4times relaxation of the synthesizer's operating frequency when comparing with the conventional closed-loop form that requires the use of a div-by-4 frequency divider. Optimized in a 90-nm CMOS process, the achieved phase precisions are plusmn0.8deg in VHF III (170 to 245 MHz) band and UHF (470 to 860 MHz) band while drawing 2.3 to 5.1 mA from a 1-V supply.

An ultra-wideband low-noise amplifier (LNA) covering the full mobile TV bands (170-to-1700 MHz) is presented. It features an ESD-protected open-source-input structure to interface the off-chip balun, such that a rail-to-rail input swing and an inductorless broadband input impedance matching can be achieved concurrently, while providing better linearity and inducing less noise. In the amplification core, double- current reuse and single-stage wideband thermal noise cancellation techniques are proposed. Optimized in a 90-nm CMOS process, the LNA achieves 20.6-dB voltage gain, 2.4-to-2.7 dB noise figure and + 10.8 dBm IIP3, while consuming 9.6 mW of power at 1.2 V. |S11| ≪ −10 dB is achieved up to 1.9 GHz without needing any external resonant network. Human Body Model ESD zapping tests of ± 4 kV at the RF pins cause no failure of any device.

A power scalable 6-bit 1.2GS/s flash Analog-to-Digital Converter (ADC) is designed in 90nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is −0.9/+0.7 LSB and the INL is −0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pJ/conversion-step at Nyquist from 1.2V power supply.

This paper presents an improved front-end digitizer for pipeline/two-step ADC. It achieves a high linearity by replacing the front-end stage's sub-ADC from the flash type that involves synchronous operation of several comparators, to the one that uses successive approximation (SA). This shift not only frees the ADC from an extra front-end sample-and-hold circuit, but also guarantees an inherent monotonicity because of no comparator mismatch (since the SA-ADC involves just one comparator in recursive operation). Two examples of a 100-MHz 3.5-bit/stage pipeline ADC and an 11-bit 30-MHz two-step ADC, validate the feasibility of such a digitizer.

A dual-mode single-loop multibit (3 bits) sigma-delta modulator (SDM) with reduced number of op-amps is proposed for satisfying the GSM/WCDMA standard. Such architecture is based in a simplified analog structure that not only features low distortion but also provides an aggressive and significantly enlarged noise shaping bandwidth with low over-sampling ratio (OSR). In addition, the resolution of comparators in the quantizer is relaxed to reduce the power consumption. Simulations in system- and transistor-level simulations prove a dynamic range of 88dB & 60dB in GSM & WCDMA respectively.

This paper presents a novel high-order bandpass semi-MASH sigma-delta modulator (4-2+2-...-2+2mb) with f/sub s//4 center frequency. The proposed topology employs a semi-MASH technique with a 4-2/sup L/mb topology to achieve an expandable and extendable high-order bandpass noise-shaping. To illustrate the architecture's behavior an 8xOSR 12-order 1.5-bit semi-MASH sigma-delta modulator is designed achieving 88 dB SNQR (signal-to-quantization-error ratio) at -1dB overloading point (90% of the modulator full-scale). A double-sampling mismatch-free single-opamp double-delay resonator is also proposed for the semi-MASH sub-stages to improve the overall design performance.

A 1.056 GS/s, 5-bit/6-bit switchable flash analog-to-digital converter (ADC) is designed in 0.18-/spl mu/m CMOS, which is suitable to be used in an OFDM-UWB transceiver. A resolution switchable structure is proposed to optimize power consumption according to the dynamic requirement of the application. Two-stage interpolation and averaging techniques are employed to average the offset of the preamplifiers. Monte Carlo simulation results show that the proposed ADC achieves 4.2b/5.0b ENOB in 5-bit/6-bit working modes with a 413-MHz input signal. The mean value of DNL and INL is 0.32 and 0.56 LSB for 5-bit mode, while 0.47 and 0.62 LSB for 6-bit mode. The analog part consumes 36 mW and 98 mW from a 1.8-V supply in 5-bit and 6-bit operation mode, respectively.

The proliferation of multiple WLANs and the continuous scaling of CMOS have created the need for low-voltage multistandard WLAN receivers. Instead of approaching a complicated SoC, a 3D-stack SiP appears as a promising alternative to meet those requirements in conjunction with the obvious goals of low power and low cost. This paper, focused on the SiP implementation of a WLAN receiver, presents the design and test strategies underlying its analog-baseband portion to accomplish: low-voltage operation; 802.11a/b/g compliance; high routability in 3D stacking; and net-response testability of the functional blocks.

Abstract- This paper proposes a novel finite-gain nonlinearity in MDACs of pipelined ADCs or poles and zeros compensation technique that can be applied to low-voltage deviations in SC filters or sigma-delta modulators, unless the high-speed reset- and switched-opamp circuits. The proposed produced finite-gain error can be compensated, with, for example, technique utilizes an Auxiliary Differential-Difference traditional Correlated Double Sampling (CDS) techniques [8,9]. Amplifier (A-DDA) that senses and corrects the finite-gain However this cannot be applied in a low-voltage environment due error from the virtual ground of the main opamp (with the to (a) limitations caused by the floating switch problems and (b) the effective gain in the order of jA2), thus allowing the use of fact that the opamp is switched off or reset in one clock phase, high-speed single-stage low-gain opamps (instead of usual low- which implies that it would not be idle and cannot be used to speed two-stage amplifier with large power consumption) to compensate the gain error. To overcome these drawbacks a low-achieve high-speed operation. Simulations of a reset-opamp 10- voltage finite-gain compensation technique can be used [4], but it bit 100 MHz pipelined ADC in 1.2-V supply voltage are has also a restriction of narrow-band operation (typically a bandpass presented using 0.18pm CMOS, with the Signal-to-Noise-and- sigma-delta modulator) that limits the signal band to be located only Distortion Ratio (SNDR) improved from 46.77 dB to 58.51 dB narrowly atf/4. and thus verifying the effectiveness of the proposed circuit. In this paper a novel low-voltage finite-gain-compensation technique is proposed. It utilizes an Auxiliary Differential-

Traditional jitter-noise analysis which mainly focuses on the clock jitter errors for impulse-sampled signals cannot accurately model the sampled-data systems that practically include nonuniform sample-and-hold effects. This paper presents a comprehensive and robust analysis of the imperfections of nonuniformly sampled-and-held signals due to clock jitter. Both the general signal to overall jitter noise ratio, and also the spurious free dynamic range subjected to narrow in-band noise tone are derived in closed-forms. Finally, a practical analysis of the timing-skew effects in designing a 21.4 MHz IF sampled-data filter for radio applications is addressed to illustrate the effectiveness of the derived formula.

This paper proposes an interactive architecture compiler for SC multirate circuits that allows the automated design from frequency specifications to building block implementation, here applied to the design and synthesis of multistage SC decimators. The compiler provides a library of different topologies that comprises a few independent multi-decimation building blocks. New building blocks defined by the users are also available for design of a specific stage. A design example of a 7th order SC decimator illustrates the efficient synthesis of the corresponding resulting circuits that achieve the required anti-aliasing amplitude responses with respect to the speed requirements of the operational amplifiers and also the minimum capacitance spread and total capacitor area.

This paper proposes a 4-fold multistage Switched-Capacitor (SC) interpolation filter with 5 MHz passband and 54 MHz output sampling rate for NTSC/PAL digital video signal processing systems. The circuit implements an impulse sampled halfband interpolation with 23- and 7-tap FIR filtering in 1stand 2nd-stage respectively for achieving a linear-phase response. A novel area-efficient technique including symmetrical-coefficient-sharing and spread-reduction is proposed in this transversal SC circuit embedding minimized mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation. This filter is designed with optimized speed of the analog components in 0.35 /spl mu/m CMOS technology and expected to consume about 2 mm/sup 2/ active area and 90 mW at 3.0 V supply.