This article presents a 1:4 single-ended binary-tree demultiplexer. The entire design, including true single-phase clock (TSPC) flip-flops, latches, and frequency divider, is composed of gated inverter blocks. The causes of voltage dip formation in flip-flops are analyzed and effectively eliminated. The setup time, hold time, and delay criteria of individual components are investigated and optimized over a variety of back-gate bias schemes as well as different supply voltages. Finally, a timing constraint is derived for the top-level demultiplexer architecture. The demultiplexer operates across a wide range of inputs from 1.6 to 60 Gb/s providing a selection of potential supply voltages ranging from 0.6 to 1.2 V. The chip’s power dissipation is mainly due to the dynamic power of the switching inverters and is self-adjustable on the basis of the input data rate. The circuit is designed and fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology with a chip area of 0.033mm2.

Even when following a well-structured top-down design methodology, system designers regularly face obstacles and pitfalls posed by speed/accuracy tradeoffs in modeling and simulation of complex hardware and software systems. Across the abstraction levels, modeling details grow exponentially, while simulation speed decreases by multiple orders of magnitude. To quantify these effects, we systematically generate, simulate, and evaluate grid-based systems-on-chip in a top-down open-source based tool flow. We map two parallel software applications onto a scalable grid of RISC-V processors and successively refine and validate the models at lower abstraction levels, namely TLM, ISS, RTL, and FPGA. Our comprehensive experimental evaluation over five abstraction levels quantifies the speed-accuracy tradeoffs in simulator build and run times. In addition to its educational value, our work can guide the system designer on an efficient path to a cycle-accurate software simulation on fully constructed hardware.

This paper presents a demonstrator chip for an industrial audio event detection application developed as part of the Scale4Edge project. The project aims at enabling a comprehensive RISC-V based ecosystem to efficiently assemble well-tailored edge devices. The chip is manufactured in Globalfoundries' 22FDX technology and contains a RISC-V CPU with custom Instruction-Set-Architecture Extensions (ISAX) for fast AI and DSP processing, a low power neural network accelerator, and a scalable PLL to fulfill real-time processing requirements. By automated integration of these specialized hardware components, we achieve a speedup of ×2.15 while reducing the power by 27% compared to the unp[ntimized solution.

This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned demonstrators, which will be used in their evaluation.

Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.

With ever increasing complexity of software and increased competition in the market, it is very important to minimize the production to market delivery time. Early phase detection of serious errors in the design and program can be done with automated approaches which save time. Memory leaks are the most important memory related problems which are severe threats to software applications. We propose a novel hybrid automated source code annotated memory leak detection approach for soft real time embedded system software with no garbage collection. We utilize our source code annotation tool to detect the potential memory leak candidates, which are further analyzed in our hybrid leak detection approach. The control flow graph of the source code generated with our annotation tool provides information of all execution paths, where the basic blocks are annotated with specific marks. Our hybrid method combines static and dynamic approaches. Static phase of the hybrid approach detect the potential leak candidates from the control flow graph. Dynamic phase filters false positives from the static phase results and provide results on the actual leaks. In early design stages where a real execution environment and complete executable software are unavailable, a simulation environment and a virtual platform are necessary. Virtual platforms provide flexibility to change the target architecture to be tested. Our proposed dynamic phase of the approach runs on the virtual memory model platform we implemented in SystemC at an abstract level using Transaction Level Modeling. The software under test is run on top of this model. This makes our approach faster and provides early results. Our approach can be easily deployed across a variety of architectures as it is compiler independent and does not implement any architecture specific features. Moreover the automated approach provides an efficient methodology to determine potential leaks in early phases of software development.

In this article, we present a virtual platform driven methodology for model-based design of dependable SW targeting cyber-physical systems. Our methodology covers an eight levels spanning flow for smooth refinement of discrete/continuous application models towards the implementation of distributed SW stacks providing flexibility w.r.t. early integration of object/binary code. For this, we propose multiple virtual platform abstraction levels supporting SW synthesis from high level MoCs. By continuous interfacing with a model of the physical environment in-the-loop we enable to holistically consider mutual impacts of the SW and its environment. In order to assess and improve SW dependability we investigate the injection of faults and their effects into both the environment model and the SW under test. We present a mapping of the proposed methodology to a completely SystemC-based framework by employing several SystemC extensions, such as AMS/TDF, QEMU, and abstract models of RTOS, HAL and middleware. Finally, we present experimental results from an automotive case study: a fault- tolerant fuel injection control system for which we consider two fault injection use cases: (i) robustness/stress testing and (ii) mutation testing. Our results were derived by prototypic integration of our SystemC framework with a commercial Simulink- based tool chain for AUTOSAR-compliant SW development and deployment.

This article presents the HeroeS virtual platform driven methodology for embedded multi-core and real-time SW design. The methodology's focus is on early integration, testing and performance estimation of heterogeneous SW stacks, i.e., SW components and layers at mixed abstraction levels and/or targeting different instruction sets. We take into account current system-level methodologies such as Transaction Level Modeling (TLM) and Real-Time Operating System (RTOS) modeling. For this, a SystemC virtual platform framework is presented combining state of the art simulation techniques according to the proposed methodology. This includes host-compiled target SW abstraction, abstract RTOS and Hardware Abstraction Layer (HAL) models in SystemC, extended QEMU user and system mode emulation and TLM 2.0 bus models. Efficient but yet accurate performance estimates can be provided through static and dynamic annotation. We apply binary mutation testing, i.e, a test assessment and improvement approach for instruction level SW testing. Our approach was investigated by prototypical integration into a commercial AUTOSAR environment. Experimental results were obtained by an automotive case study: a fault-tolerant fuel injection control system, which is part of an in-car network.

The modeling and analysis of Cyber-Physical Systems (CPS) is one of the key challenges in complex system design as heterogeneous components are combined and their close interaction with the physical environment has to be considered. This article presents a methodology and an open toolset for the virtual prototyping of CPS. The focus of the methodology is the virtual prototyping of the embedded software combined with the prototyping of the physical environment in order to capture the complete closed control loop of the software over the hardware via sensors/actors with the physical objects. The methodology is based on the application of integrated open source tools and standard languages, i.e., C/C++, SystemC, and the Open Dynamics Engine, which are combined to a powerful simulation framework. Key activities of the methodology are outlined by the example of an electric two-wheel vehicle.

This work proposes an advanced methodology based on an open source virtual prototyping framework for verification of complex Heterogeneous Embedded Systems (HES). It supports early rapid modelling of complex HES through smooth refinements, an open interface based on IP-XACT extensions for secure composition of HES components, and automatic testbench generation over different abstraction levels.

This paper presents a novel mutation based testing method through binary mutation. For this, a table of mutants is derived by control flow analysis of a disassembled binary under test. Mutations are injected at runtime by dynamic translation. Thus, our approach neither relies on source code nor a certain compiler. As instrumentation is avoided, testing results correspond to the original binary. In addition to high-level language faults, the proposed approach captures target specific faults related to compiling and linking. We investigated the software of an automotive case study. For this, a taxonomy of mutation operators for the ARM instruction set is proposed. Our experimental results prove 100% accuracy w.r.t. confidence metrics provided by conventional testing methods while avoiding significant mutant compilation overhead. Further speed up is achieved by an efficient binary mutation testing framework that relies on extending the open source software emulator QEMU.

This paper presents the XEMU framework for mutation based testing of embedded software binaries. We apply an extension of the QEMU software emulator, which injects mutations at run-time by dynamic code translation without affecting the binary software under test. The injection is based on a mutation table, which is generated by control flow graph (CFG) analysis of the disassembled code prior to its execution without presuming access to source code. We introduce our approach by the example of the ARM instruction set architecture for which a mutation taxonomy is presented. In addition to extending the testing scope to target specific low level faults, XEMU addresses the reduction of the mutants creation, execution, and detection overheads. Moreover, we reduce testing efforts by applying binary CFG analysis and constraint-based test generation for improved test quality. The experimental results of a car motor management software show significant improvements over conventional source code based approaches while providing 100% accuracy in terms of the computed test quality metrics.

The energy efficiency becomes one of the most important concerns in mobile electronic systems design with mandatory requirements for low energy consumption, long battery life and low heat dissipation. Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS or DVS) are two widely applied system level techniques to conserve system-wide power consumption. In the context of hard real-time systems, however, DPM and DVS have to be used with great caution in terms of timing constraints. In this article, we study the combined application of DPM and DVS for component oriented systems with hard real-time tasks and propose a simulated annealing based optimization algorithm and its online execution with constant complexity at each scheduling point. Additionally, our approach considers multiple low power states (sleep states) with non-negligible switching overhead. The experimental results show that our approach can achieve almost an optimal solution.

In this paper we present an approach for the configuration and reconfiguration of FlexRay networks to increase their fault tolerance. To guarantee a correct and deterministic system behavior, the FlexRay specification does not allow a reconfiguration of the schedapproachule during run time. To avoid the necessity of a complete bus restart in case of a node failure, we propose a reconfiguration using redundant slots in the schedule and/or combine messages in existing frames and slots, to compensate node failures and increase robustness. Our approach supports the developer to increase the fault tolerance of the system during the design phase. It is a heuristic, which, additionally to a determined initial configuration, calculates possible reconfigurations for the remaining nodes of the FlexRay network in case of a node failure, to keep the system working properly. An evaluation by means of realistic safety-critical automotive real-time systems revealed that it determines valid reconfigurations for up to 80% of possible individual node failures. In summary, our approach offers major support for the developer of FlexRay networks since the results provide helpful feedback about reconfiguration capabilities. In an iterative design process these information can be used to determine and optimize valid reconfigurations.

HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.

Mutation analysis is a powerful tool for white-box testing of the verification environment in order to produce dependable and higher quality software products. However, due to high computational costs and the focus on high-level software languages such as Java mutation analysis is not yet widely used in commercial design flows targeting embedded (software) systems. Here the industry is modeling both hardware and related software parts at higher levels of abstraction, called virtual prototypes, to accelerate parallel development and shorten time-to-market. In this paper we propose a mutation testing verification flow for SystemC based virtual prototypes that may not rely on source code only but on annotated basic blocks and enables mutant creation at assembler level to heavily reduce execution costs and equivalence mutants likelihood.

Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.

Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.

Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.

UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.

Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.

Due to the rapidly increasing software content in embedded systems, hardware-dependent software (HdS) has become a critical topic in system design. In this paper, we provide a brief overview on the topic of HdS, discuss the issues and complexities involved in the design of HdS, and motivate the need for special attention to HdS in research and development.

IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.

Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.

This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog (Chandra and Chakrabarty, 2001) test bench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) (Chakrabarty et al., 2000) extending CTM/ES for random test generation as well as for functional coverage and property specification

TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.

UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.

Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.

The interconnection of software components is a key to enabling collaborative work. However, technology differences and security barriers like firewalls often hinder establishing collaborative infrastructures between enterprises or even within a single enterprise. We introduce a peer-to-peer based network infrastructure that transparently overcomes these problems using relay and routing mechanisms as well as different underlying transport protocols. We discuss the application of this technology to interconnect Web services.

This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.

This paper proposes a methodology for an executable UML 2.0 subset based on State Transition Diagrams (STDs) and Sequence Diagrams (SD) that covers interrupts, exceptions, and timeouts. In this a UML Virtual Machine (UVM) as the run-time environment for complete executable specifications based on that executable UML subset. Such specifications are compiled to binary programs consisting of data structures (STDs) and bytecode (SDs).

The design of embedded systems is often based on the development of a detailed formal system specification. Considerable effort is spent to ensure the correctness of this specification. However, the actual implementation of the specification and later maintenance is usually done using traditional programming and more often diverges from the specification. To overcome this, it is desirable to derive the implementation directly from the specification. We present an approach for model-based development of embedded systems applying a well-defined UML 2.0 subset with precise execution semantics. Our approach is fully object-oriented, accounts for important aspects like real-time behavior including timeouts, and interrupts. Through the seamless integration of UML sequence diagrams with state diagrams, executable systems can be completely described. The direct execution of such models on a UML virtual machine (UVM) avoids a separate implementation step and increases portability

We present a framework, which combines model checking and theorem prover based refinement for real-time systems design focusing on the refinement of non deterministic to timed deterministic finite state machines. Our verification flow starts from a cycle accurate finite state machine for the RAVEN model checker. We present a translation, which transforms the model into efficient B language code. After refining the RAVEN model and annotating it, the time accurate model is also translated to B so that the B theorem prover can verify the refined model almost automatically. The approach is introduced by the example of a mobile phone echo cancellation unit.

We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.