Indoor Device-Free Localisation (DFL) systems are receiving increasing attention to replace traditional active ones in some applications, such as those that support independent living for vulnerable people who are not able to carry sensors. These systems analyse the influence in the channel transmission response of certain emitted signals when interacting with the human body in order to locate it. Whereas the most widespread DFL systems make use of radio-frequency signals through Radar, WiFi or BLE (Bluetooth Low Energy) sensors, this work focuses on those that use acoustic signals, at ultrasound (US) frequencies, to estimate the position of the person. The emitted acoustic signals are altered by reflections, absorptions and frequency shifts (Doppler effect), derived from the medium and other elements existing in the environment, which are interesting to study in order to develop DFL systems. For this purpose, this work proposes a simulator that models all the phenomena that compose the channel response for the recreation of a real environment. In addition, a preliminary analysis of an ultrasonic positioning system that makes use of ultrasound reflections from the person’s head is presented. The proposed tool is useful to develop new ultrasonic DFL systems that take advantage of the acoustic properties with the aim of obtaining preliminary results previously to address a real prototype.

EEG is the gold standard for seizure detection in the newborn infant, but EEG interpretation in the preterm group is particularly challenging; trained experts are scarce and the task of interpreting EEG in real-time is arduous. Preterm infants are reported to have a higher incidence of seizures compared to term infants. Preterm EEG morphology differs from that of term infants, which implies that seizure detection algorithms trained on term EEG may not be appropriate. The task of developing preterm specific algorithms becomes extra-challenging given the limited amount of annotated preterm EEG data available. This paper explores novel deep learning (DL) architectures for the task of neonatal seizure detection in preterm infants. The study tests and compares several approaches to address the problem: training on data from full-term infants; training on data from preterm infants; training on age-specific preterm data and transfer learning. The system performance is assessed on a large database of continuous EEG recordings of 575[Formula: see text]h in duration. It is shown that the accuracy of a validated term-trained EEG seizure detection algorithm, based on a support vector machine classifier, when tested on preterm infants falls well short of the performance achieved for full-term infants. An AUC of 88.3% was obtained when tested on preterm EEG as compared to 96.6% obtained when tested on term EEG. When re-trained on preterm EEG, the performance marginally increases to 89.7%. An alternative DL approach shows a more stable trend when tested on the preterm cohort, starting with an AUC of 93.3% for the term-trained algorithm and reaching 95.0% by transfer learning from the term model using available preterm data. The proposed DL approach avoids time-consuming explicit feature engineering and leverages the existence of the term seizure detection model, resulting in accurate predictions with a minimum amount of annotated preterm data.

This work proposes an Android-based platform to warn the medical staff of the onset of allergy reactions during a provocation test in a hospital. The portable system carries out the analysis of the heart rate variability for the early detection of allergic reactions in patients undergoing allergy provocation tests at hospitals. The proposal is composed of an ECG (electrocardiogram) acquisition system and an Android device (Smartphone, Tablet) that monitors and evaluates the results in real time, increasing the safety of allergic tests. At present, food and drug allergic tests are a major problem for patients because of their long duration and intrusion. However, the authors have designed an algorithm for detecting allergy reactions that have focused on reducing the time of the tests and the number of doses. This algorithm runs on an Android platform, and it is able to provide alarms for the medical staff if there is an allergy reaction. The proposed monitoring system is very suitable for the health monitoring during the provocation tests.

Technologies for automated detection of neonatal seizures are gradually moving towards cot-side implementation. The aim of this paper is to present different ways to visualize the output of a neonatal seizure detection system and analyse their influence on performance in a clinical environment. Three different ways to visualize the detector output are considered: a binary output, a probabilistic trace, and a spatio-temporal colormap of seizure observability. As an alternative to visual aids, audified neonatal EEG is also considered. Additionally, a survey on the usefulness and accuracy of the presented methods has been performed among clinical personnel. The main advantages and disadvantages of the presented methods are discussed. The connection between information visualization and different methods to compute conventional metrics is established. The results of the visualization methods along with the system validation results indicate that the developed neonatal seizure detector with its current level of performance would unambiguously be of benefit to clinicians as a decision support system. The results of the survey suggest that a suitable way to visualize the output of neonatal seizure detection systems in a clinical environment is a combination of a binary output and a probabilistic trace. The main healthcare benefits of the tool are outlined. The decision support system with the chosen visualization interface is currently undergoing pre-market European multi-centre clinical investigation to support its regulatory approval and clinical adoption.

Brain injury at the time of birth could lead to severe neurological dysfunction at an older age. Grading the brain injury in the early hours after birth could help doctors determine a prompt and reliable treatment. This work presents an automated neonatal EEG grading system based on a cross-disciplinary method of using Support Vector Machine and supervectors, initially developed for speaker identification. The EEG is classified into one of the four grades of neonatal brain injury. The preliminary results show promising performance and are an improvement on the previously published results.

Detection of seizures in neonatal EEG signal represents a formidable challenge for clinicians in the neonatal intensive care unit (NICU). Seizure morphology is known to evolve both temporally and spatially with a similar evolution also observed in the frequency domain. The modulation frequency analysis which is widely used in speech processing is used here to extract the frequency-localized spectral dynamics of the neonatal EEG and investigate their discriminative capabilities in the context of neonatal seizure detection. This study suggests that the spectral dynamics of neonatal EEG are more informative than short-term spectral characteristics. It is shown that the seizure-relevant components of the modulation spectrogram are found in the vicinity of 0.4Hz. Modulation frequency analysis represents a new insight into the EEG signal which can uncover the underlying time-structural organization of the neonatal EEG signal and therefore improve clinical understanding of the dynamic processes involved.

Automated analysis and grading of the neonatal EEG has a potential to assist clinical decision making for neonates with hypoxic-ischemic encephalopathy. This paper proposes a method to grade the degree of abnormality in hour-long segments of neonatal EEG. The HMM-based speaker diarization approach is employed to segment and cluster the neonatal EEG into homogeneous states. Several features are proposed to characterize the resultant state sequence to provide a single measure for a complete hour-long EEG recording. These features aim at capturing both the statistics of the state durations (e.g. average state duration, average number of segments), and any patterns contained in the sequentiality of the obtained states (e.g. permutation entropy, entropy rate). Statistical analysis indicates that the proposed features contain discriminative information for the task of automated neonatal EEG grading. Unlike other studies, the developed framework of the EEG ‘diarization’ provides an easy and intuitive interpretation of the computed features, which is a clinically important aspect.

This paper investigates the fully automated computer-based detection of allergic reaction in oral food challenges using pediatric ECG signals. Nonallergic background is modeled using a mixture of Gaussians during oral food challenges, and the model likelihoods are used to determine whether a subject is allergic to a food type. The system performance is assessed on the dataset of 24 children (15 allergic and 9 nonallergic) totaling 34 h of data. The proposed detector correctly classified all nonallergic subjects (100% specificity) and 12 allergic subjects (80% sensitivity) and is capable of detecting allergy on average 17 min earlier than trained clinicians during oral food challenges, the gold standard of allergy diagnosis. Inclusion of the developed allergy classification platform during oral food challenges recorded would result in a 30% reduction of doses administered to allergic subjects. The results of study introduce the possibility to halt challenges earlier which can safely advance the state of clinical art of allergy diagnosis by reducing the overall exposure to the allergens.

Adaptive probabilistic modeling of the EEG background is proposed for seizure detection in neonates with hypoxic ischemic encephalopathy. The decision is made based on the temporal derivative of the seizure probability with respect to the adaptively modeled level of background activity. The robustness of the system to long duration "seizure-like" artifacts, in particular those due to respiration, is improved. The system was developed using statistical leave-one-patient-out performance assessment, on a large clinical dataset, comprising 38 patients of 1479 h total duration. The developed technique was then validated by a single test on a separate totally unseen randomized prospective dataset of 51 neonates totaling 2540 h of duration. By exploiting the proposed adaptation, the ROC area is increased from 93.4% to 96.1% (41% relative improvement). The number of false detections per hour is decreased from 0.42 to 0.24, while maintaining the correct detection of seizure burden at 70%. These results on the unseen data were predicted from the rigorous leave-one-patient-out validation and confirm the validity of our algorithm development process.

This paper examines the effects of compression on EEG signals, in the context of automated detection of epileptic seizures. Specifically, it examines the use of lossy compression on EEG signals in order to reduce the amount of data which has to be transmitted or stored, while having as little impact as possible on the information in the signal relevant to diagnosing epileptic seizures. Two popular compression methods, JPEG2000 and SPIHT, were used. A range of compression levels was selected for both algorithms in order to compress the signals with varying degrees of loss. This compression was applied to the database of epileptiform data provided by the University of Freiburg, Germany. The real-time EEG analysis for event detection automated seizure detection system was used in place of a trained clinician for scoring the reconstructed data. Results demonstrate that compression by a factor of up to 120:1 can be achieved, with minimal loss in seizure detection performance as measured by the area under the receiver operating characteristic curve of the seizure detection system.

A number of automated neonatal seizure detectors have been proposed in recent years. However, there exists a large variability in the morphology of seizure and background patterns, both across patients and over time. This has resulted in relatively poor performance from systems which have been tested over large datasets. Here, the benefits of employing a pattern recognition approach are discussed. Such a system may use numerous features paired with nonlinear classifiers. In particular, two types of nonlinear classifiers are contrasted for the task. Additionally, it is shown that the proposed architecture allows for efficient classifier combination which improves the performance of the algorithm. The resulting automated detector is shown to achieve field leading performance. A particular strength of the proposed algorithm is the performance of the algorithm when very low false detections are required, at 0.25 false detections per hour, the system is able to detect 75.4% of the seizure events.

In this paper we provide a comparison of different modular multipliers suitable for use in an elliptic curve processor, when working with a Mersenne prime modulus. Mersenne primes allow for the use of fast modular reduction techniques. Several multipliers are presented that can be implemented solely in slice logic. A design that makes use of the DSP48E blocks on Virtex 5 FPGAs is also described. The different multipliers are compared for speed, area and power consumption when implemented on a Virtex 5 FPGA.

In this paper, features which are usually employed in automatic speech recognition (ASR) are used for the detection of seizures in newborn EEG. In particular, spectral envelope-based features, composed of spectral powers and their spectral derivatives are compared to the established feature set which has been previously developed for EEG analysis. The results indicate that the ASR features which model the spectral derivatives, either full-band or localized in frequency, yielded a performance improvement, in comparison to spectral-power-based features. Indeed it is shown here that they perform reasonably well in comparison with the conventional EEG feature set. The contribution of the ASR features was analyzed here using the support vector machines (SVM) recursive feature elimination technique. It is shown that the spectral derivative features consistently appear among the top-rank features. The study shows that the ASR features should be given a high priority when dealing with the description of the EEG signal.

The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper gives an area/speed comparison of each design both with and without a hardware interface, thereby giving an overall impression of their performance in resource constrained and resource abundant environments. The implementation results are provided for a Virtex-5 FPGA device. The efficiency of the architectures for the hash functions are compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first work to date to present hardware designs which test for all message digest sizes (224, 256, 384, 512), and also the only work to include the padding as part of the hardware for the SHA-3 hash functions.

Hash functions are widely used in, and form an important part of many cryptographic protocols. Currently, a public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware will form one of the evaluation criteria. In this paper, we focus on five of these candidate algorithms, namely CubeHash, Grostl, Lane, Shabal and Spectral Hash. Using Xilinx Spartan-3 and Virtex-5 FPGAs, we present architectures for each of these hash functions, and explore area-speed trade-offs in each design. The efficiency of various architectures for the five hash functions is compared in terms of throughput per unit area. To the best of the authors' knowledge, this is the first such comparison of these SHA-3 candidates in the literature.

Low Density Parity Check (LDPC) codes over GF(2m,)are an extension of binary LDPC codes. Performances of GF(2m,) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there is a substantial lack of implementations for LDPC codes over GF(2m,)codes. This paper presents a class of quasi-cyclic LDPC codes over GF(2m,). These codes can alleviate the encoding/decoding complexity without excessive loss of performances. It is shown how, from a performance point of view, such codes are better than m times bigger binary codes and as good as (2m,)longer binary codes.

This paper presents an energy-efficient medium access control protocol suitable for communication in a wireless body area network for remote monitoring of physiological signals such as EEG and ECG. The protocol takes advantage of the static nature of the body area network to implement the effective time-division multiple access (TDMA) strategy with very little amount of overhead and almost no idle listening (by static, we refer to the fixed topology of the network investigated). The main goal is to develop energy-efficient and reliable communication protocol to support streaming of large amount of data. TDMA synchronization problems are discussed and solutions are presented. Equations for duty cycle calculation are also derived for power consumption and battery life predictions. The power consumption model was also validated through measurements. Our results show that the protocol is energy efficient for streaming communication as well as sending short bursts of data, and thus can be used for different types of physiological signals with different sample rates. The protocol is implemented on the analog devices ADF7020 RF transceivers.

Elliptic curve cryptography has generated a lot of research interest due to its ability to provide greater security per bit compared to public key systems such as RSA. The designer of an elliptic curve hardware accelerator is faced with many choices at design time, each of which can impact the performance of the accelerator in different ways. There are many examples in the literature of how these design choices can effect the area and/or speed of an elliptic curve hardware accelerator. The effect of design choices on power and energy consumption in elliptic curve hardware has been less well studied. This article studies the effect of design choices on the power and energy consumption of an FPGA-based reconfigurable elliptic curve hardware accelerator. A reconfigurable processor has been used for different system parameters and the power and energy consumption measured. The power and energy results are presented and compared.

Security protocols are frequently accelerated by implementing the underlying cryptographic functions in reconfigurable hardware. However, unprotected hardware implementations are susceptible to side-channel attacks, and Differential Power Analysis (DPA) has been shown to be especially powerful. In this work, we evaluate and compare the effectiveness of common hiding countermeasures against DPA in FPGA-based designs, using the Whirlpool hash function as a case study. In particular, we develop a new design flow called Isolated WDDL (IWDDL). In contrast with previous works, IWDDL isolates the direct and complementary circuit paths, and also provides DPA resistance in the Hamming distance power model. The analysis is supported using actual implementation results.

The use of complementary sets of sequences is especially relevant in multisensorial systems, with simultaneous emissions from different sources and low signal-to-noise ratio (SNR). There exist efficient generation and correlation algorithms that give a reduction in the computational load and complexity of a hardware implementation. In this work a new hardware design approach for an efficient correlator of complementary sets of sequences (CCS) is presented. It is based on utilising reconfigurable logic to gain the required flexibility in terms of correlator parameters. The configuration of the design is carried out at the pre-synthesis stage, so the user can change this configuration according to the requirements of the application

In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.

A method is proposed for automatically choosing independent components (ICs) of interest from neonatal EEG data, with the aim of using them in further analysis to detect seizures. This procedure greatly reduces the amount of information which needs to be processed in the seizure detection system, and reduces the effect of noise and artefacts on its performance. The Fast ICA algorithm is used to generate the ICs, and the complexity of each IC is examined to determine those of interest. The Singular Value Fraction (SVF) measure is used to reduce the number of sources containing artefacts chosen. In the best case, the 12 channel EEG used in these tests is reduced to 2 or 3 sources of interest, In every case, at least 3 sources were removed that consisted of noise. © 2005 IEEE.

A secure communications protocol contains a symmetric key cryptosystem, a hash algorithm and a method for providing digital signatures and key exchange using public key cryptography. This work presents an implementation of these core ciphers on a single FPGA. A novel architecture combining a symmetric-key and message authentication algorithm is proposed, with FIFO memory-blocks used as buffers to allow them run in parallel from the same data source. The generation of digital signatures and key exchange using a modular exponentiator core block is also considered. The complete design is implemented on a PCI prototyping card containing a Xilinx Virtex-2000E FPGA and SRAM memory banks. To optimise the data transfer rate between the SRAMs and the FPGA. The memory interface and encryption cores are partitioned into separate clock domains. Comparisons are then made between theoretical results from timing analysis reports and implemented results on the prototyping card.

This paper presents a review of some existing architectures for the implementation of Montgomery modular multiplication and exponentiation on FPGA (Field Programmable Gate Array). Some new architectures are presented, including a pipelined architecture exploiting the maximum carry chain length of the FPGA which is used to implement the modular exponentiation operation required for RSA encryption and decryption. Speed and area comparisons are performed on the optimised designs. The issues of targeting a design specifically for a reconfigurable device are considered, taking into account the underlying architecture imposed by the target technology.

Parametric, model based, spectral estimation techniques can offer increased frequency resolution over conventional short-term fast Fourier transform methods, overcoming limitations caused by the windowing of sampled, time domain, input data. However, parametric techniques are significantly more computationally demanding than the Fourier based methods and require a wider range of arithmetic functionality; for example, operations such as division and square-root are often necessary. These arithmetic processes exhibit communication bottleneck and their hardware implementation can be inefficient when used in conjunction with multipliers. A programmable, bit-serial, multiplier/divider, which overcomes the bottleneck problems by using a data interleaving scheme, is introduced. This interleaved processor is used to show how the parametric modified covariance spectral estimator can be efficiently routed on a field programmable gate array for real-time applications.

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such CMOS chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.>

The authors examine the problems of testing a motion estimator array using a novel strategy for testing VLSI regular arrays. They present a case study to demonstrate the ability of the strategy to test regular arrays with data restrictions, to test large word level arrays, and to test less regular arrays. The motion estimator array is considered as an array within an array. Each processing element is a bit-sliced array where the bit slice contains three different cells. Each of the constituent cells in the bit slice is exhaustively tested, resulting in a high fault coverage. The vectors which test the processing element (PE) can then be propagated to every PE in the word level array. Since the data buses are 8 b wide, the propagation graphs developed for the bit-level arrays are not suitable for this word level array. A suitable change in notation is presented.>

The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns.>