Adaptive testing (AT) is a software testing approach that uses a feedback mechanism to enhance test effectiveness. Its testing strategy can be adjusted online by using the testing data collected during the software testing process. However, it requires complex parameter estimation which results in excessive computational overhead that may hinder the applicability of AT. In this paper, we propose an approach called AT based on moment estimation (AT-ME) to address this problem. The proposed approach uses moment estimation to serve as the algorithm of parameter estimation, which reduces the complexity of AT-ME. In addition, a dynamic length for testing action is set to limit the number of decisions without influencing the test effectiveness. The proposed approach has been validated on the Siemens test suite, which includes seven real programs. The experiments show that AT-ME can reduce the computational overhead of AT without compromising overall testing efficiency. Results demonstrate that AT-ME is a feasible and effective AT strategy.

Not all vulnerabilities are equal. Some recent studies have shown that only a small fraction of vulnerabilities that have been reported has actually been exploited. Since finding and addressing potential vulnerabilities in a program can take considerable time and effort, recently effort has been made to identify code that is more likely to be vulnerable. This paper tries to identify the attributes of the code containing a vulnerability that makes the code more likely to be exploited. We examine 183 vulnerabilities from the National Vulnerability Database for Linux Kernel and Apache HTTP server. These include eighty-two vulnerabilities that have been found to have an exploit according to the Exploit Database. We characterize the vulnerable functions that have no exploit and the ones that have an exploit using eight metrics. The results show that the difference between a vulnerability that has no exploit and the one that has an exploit can potentially be characterized using the chosen software metrics. However, predicting exploitation of vulnerabilities is more complex than predicting just the presence of vulnerabilities and further research is needed using metrics that consider security domain knowledge for enhancing the predictability of vulnerability exploits.

Evaluating the accuracy of vulnerability security risk metrics is important because incorrectly assessing a vulnerability to be more critical could lead to a waste of limited resources available and ignoring a vulnerability incorrectly assessed as not critical could lead to a breach with a high impact. In this paper, we compare and evaluate the performance of the CVSS Base metrics and Microsoft Rating system. The CVSS Base metrics are the de facto standard that is currently used to measure the severity of individual vulnerabilities. The Microsoft Rating system developed by Microsoft has been used for some of the most widely used systems. Microsoft software vulnerabilities have been assessed by both the Microsoft metrics and the CVSS Base metrics which makes their comparison feasible. The two approaches, the technical analysis approach (Microsoft) and the expert opinions approach (CVSS) differ significantly. To conduct this study, we examine 813 vulnerabilities of Internet Explorer and Windows 7. The two software systems have been selected because they have a rich history of publicly available vulnerabilities, and they differ significantly in functionality and size. The presence of actual exploits is used for evaluating them. The results show that exploitability metrics in either system do not correlate strongly with the existence of exploits, and have a high false positive rate.

Capacitive Leadframe Testing is capable of detecting open solder defects in Printed Circuit Boards (PCB). Principal Component Analysis (PCA)-based approach has been shown to be effective in identifying outlier devices using Capacitive Leadframe Testing measurements. In practice, when a sense plate orientation is shifted or tilted, the resulting measurement variation makes detecting outliers harder. Approaches are introduced to compensate for the `abnormal' measurements due to sense-plate variations. A PCA based technique is developed to estimate the relative amount of tilt and shift in sense plates. Such estimates can be used to compensate for mechanical misalignments. It can also isolate the misalignment related information from the defect related information in the data. The effectiveness of this technique in the presence of the two common forms of mechanical variations is illustrated using experimental measurements from a laboratory setting. The approach is not sensitive to the order of pins, and as such, shows promise for detection of complex but systematic errors introduced by sense plate misalignments.

Vulnerability discovery rates need to be taken into account for evaluating security risks. Accurate projection of these rates is required to estimate the effort needed to develop patches for handling vulnerabilities discovered. Seasonal behaviors of the vulnerability discovery process for a multi-year life-cycle of software products are examined. A careful inspection of the data for several major operating systems, web servers and web browsers suggests presence of a seasonal behavior that is not considered by the vulnerability discovery models. This paper examines the statistical significance of the annual seasonal pattern in the vulnerability discovery rates using the seasonal index approach. The autocorrelation function is used to identify the periodicity. A time series analysis that combines thelonger term trends with cycles caused by seasonality may predict the future pattern more accurately. The analysis of the datasets for eight major operating systems and four web related software systems (Windows NT, XP, 2000, Server 2003, MAC OS X, HPUX, Solaris, Red Hat Linux, IIS, Apache, Internet Explorer and Firefox) shows that there is indeed anannual seasonal pattern. While all the programs exhibit a year-end peak, a higher incidence is also observed during the mid-year months for Microsoft products.

Capacitive Leadframe testing is an effective approach for detecting faults in printed circuit boards. Capacitance measurements, however, are affected by mechanical variations during testing and by tolerances of electrical parameters of components, making it difficult to use threshold based techniques for defect detection. A novel approach is presented for identifying boards that are likely to be outliers. Based on Principal Components Analysis (PCA), this approach treats the set of capacitance measurements of individual connectors or sockets in a holistic manner to overcome the measurement and component parameter variations inherent in test data. The effectiveness of the method is evaluated using measurements on three different boards. Enhancements to the technique to increase the resolution of the method are presented and evaluated.

A vulnerability discovery model describes the variation in the vulnerability discovery rate during the lifetime of a software system and can be used to assess risk and to evaluate possible mitigation approaches. A few vulnerability discovery models have recently been proposed. The AML Logistic model has been found to provide the best fit in several cases. Weibull distribution, which can model an asymmetric pdf, is often used for reliability evaluation in some fields but has not been used for modeling vulnerability discovery. Here we propose a new Weibull distribution based on vulnerability discovery model and compare it with the existing AML Model. The results show that the new model performs well in many cases, and may be considered as an alternative to the AML model.

Prediction of vulnerability discovery rates can be used to assess security risks and to determine the resources needed to develop patches quickly to handle vulnerabilities discovered. An examination of the vulnerability data suggests a seasonal behavior that has not been modeled by the recently proposed vulnerability discovery models. This seasonality has not been identified or examined so far. This study examines whether vulnerability discovery rates for Windows NT, IIS Server and the Internet Explorer exhibit a significant annual seasonal pattern. Actual data has been analyzed using seasonal index and auto correlation function approaches to identify seasonality and to evaluate its statistical significance. The results for the three software systems show that there is indeed a significant annual seasonal pattern.

A number of security vulnerabilities have been reported in the Windows, and Linux operating systems. Both the developers, and users of operating systems have to utilize significant resources to evaluate, and mitigate the risk posed by these vulnerabilities. Vulnerabilities are discovered throughout the life of a software system by both the developers, and external testers. Vulnerability discovery models are needed that describe the vulnerability discovery process for determining readiness for release, future resource allocation for patch development, and evaluating the risk of vulnerability exploitation. Here, we analytically describe six models that have been recently proposed, and evaluate those using actual data for four major operating systems. The applicability of the proposed models, and the significance of the parameters involved are examined. The results show that some of the models tend to capture the discovery process better than others.

We examine the feasibility of quantitatively characterizing the vulnerabilities in the two major HTTP servers. In particular, we investigate the applicability of quantitative empirical models to the vulnerabilities discovery process for these servers. Such models can allow us to predict the number of vulnerabilities that may potentially be present in a server but may not yet have been found. The data on vulnerabilities found in the two servers is mined and analyzed. We explore the applicability of a time-based and an effort-based vulnerability discovery model. The effort-based model requires data of the current market-share of a server. Both models have been successfully used for vulnerabilities in the major operating systems. Our results show that both vulnerabilities discovery models fit the data for the HTTP servers well. We also examine a separate classification schemes for server vulnerabilities that based on the source of error, and then explore the applicability of the quantitative methods to individual classes

The prediction of the number of vulnerabilities in an HTTP server can allow us to evaluate the security risk associated with its use. Vulnerability discovery models have recently been proposed which can be used to estimate the future number of vulnerabilities expected to be discovered. A detailed analysis of the prediction capabilities of two models termed AML and LVD for the vulnerabilities in the two major HTTP servers is presented. Four complete data sets for Apache and US are used, representing an open source and a commercial Web server respectively. Both long term predictions involving several years and short term predictions for the following year are considered. Potential methods for enhancing the prediction accuracy are considered. The results show good predictive capabilities of the AML model when constraints are used for estimating the model parameters. The LVD model works well in some special cases when saturation has not yet set in. The results can be used by both developers to plan the test and maintenance effort needed and by users to assess the potential security risks associated with a specific server

A statistical technique X-IDDQ for extracting defect information from IDDQ data is presented that is effective for detection of defects in ICs. The technique treats the IDDQ measurements in a holistic manner to come up with a statistic X that is highly correlated to the presence of defects. X-IDDQ facilitates binning of ICs and enhances the test process by early identification of faults. The transformation metrics, for evaluating X statistic from IDDQ measurements, obtained using one batch works extremely well for different batches, facilitating its use with manufacturing-line testing.

Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume significant dynamic power during testing because of enhanced switching activity in the internal nodes. Our work focuses on the fact that power minimization is a traveling salesman problem (TSP). We explore application of local search and genetic algorithms to test set reordering and perform a quantitative comparison to previously used deterministic techniques. We also consider reduction of the original test set as a dual-objective optimization problem, where switching activity and fault coverage are the two objective functions.

Security vulnerabilities in servers and operating systems are software defects that represent great risks. Both software developers and users are struggling to contain the risk posed by these vulnerabilities. The vulnerabilities are discovered by both developers and external testers throughout the life-span of a software system. A few models for the vulnerability discovery process have just been published recently. Such models will allow effective resource allocation for patch development and are also needed for evaluating the risk of vulnerability exploitation. Here we examine these models for the vulnerability discovery process. The models are examined both analytically and using actual data on vulnerabilities discovered in three widely-used systems. The applicability of the proposed models and significance of the parameters involved are discussed. The limitations of the proposed models are examined and major research challenges are identified

"Software test-coverage measures" quantify the degree of thoroughness of testing. Tools are now available that measure test-coverage in terms of blocks, branches, computation-uses, predicate-uses, etc. that are covered. This paper models the relations among testing time, coverage, and reliability. An LE (logarithmic-exponential) model is presented that relates testing effort to test coverage (block, branch, computation-use, or predicate-use). The model is based on the hypothesis that the enumerable elements (like branches or blocks) for any coverage measure have various probabilities of being exercised; just like defects have various probabilities of being encountered. This model allows relating a test-coverage measure directly with defect-coverage. The model is fitted to 4 data-sets for programs with real defects. In the model, defect coverage can predict the time to next failure. The LE model can eliminate variables like test-application strategy from consideration. It is suitable for high reliability applications where automatic (or manual) test generation is used to cover enumerables which have not yet been tested. The data-sets used suggest the potential of the proposed model. The model is simple and easily explained, and thus can be suitable for industrial use. The LE model is based on the time-based logarithmic software-reliability growth model. It considers that: at 100% coverage for a given enumerable, all defects might not yet have been found.

Data from several projects show a significant relationship between the size of a module and its defect density. We address implications of this observation. Does the overall defect density of a software project vary with its module size distribution? Even more interesting is the question can we exploit this dependence to reduce the total number of defects? We examine the available data sets and propose a model relating module size and defect density. It takes into account defects that arise due to the interconnections among the modules as well as defects that occur due to the complexity of individual modules. Model parameters are estimated using actual data. We then present a key observation that allows use of this model for not just estimation of the defect density, but also potentially optimizing a design to minimize defects. This observation, supported by several data sets examined, is that the module sizes often follow exponential distribution. We show how the two models used together provide a way of projecting defect density variation. We also consider the possibility of minimizing the defect density by controlling module size distribution.

Ideally the requirements for a software system should be completely and unambiguously determined before design, coding and testing rake place. In practice, often there are changes in the requirements, causing software components to be redesigned, deleted or added. This requirements volatility causes the software to have a higher defect density. In this paper we analytically examine the influence of requirement changes taking place during different times by examining the consequences of software additions, removals and modifications. We take into account interface defects which arise due to errors at the interfaces among software sections. We compare the resulting defect density in the presence of requirement volatility, with the defect density that would have resulted had requirements not changed. The results show that if the requirement changes take place close to the release date, there is a greater impact on defect density. In each case we compute the defect equivalence factor representing the overall impact of requirement volatility.

This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. This strategy results in a higher fault coverage when the number of vectors that are applied is limited. Results on several ISCAS benchmarks show this strategy to be very effective when a high fault coverage needs to be achieved with a limited number of test vectors. The superiority of the antirandom testing approach is even more significant for testing bridging faults.

Here we investigate the underlying basis connecting the software reliability growth models to the software testing and debugging process. This is important for several reasons. First, if the parameters have an interpretation, then they constitute a metric for the software test process and the software under test. Secondly, it may be possible to estimate the parameters even before testing begins. These a priori values can serve as a check for the values computed at the beginning of testing, when the test-data is dominated by short term noise. They can also serve as initial estimates when iterative computations are used. Among the two-parameter models, the exponential model is characterized by its simplicity. Both its parameters have a simple interpretation. However, in some studies it has been found that the logarithmic Poisson model has superior predictive capability. Here we present a new interpretation for the logarithmic model parameters. The problem of a priori parameter estimation is considered using actual data available. Use of the results obtained is illustrated using examples. Variability of the parameters with the testing process is examined.

The implementation of an efficient automatic test generation scheme for black box testing is discussed. It uses checkpoint encoding and antirandom testing schemes. Checkpoint encoding converts test generation to a binary problem. The checkpoints are selected as the boundary and illegal cases in addition to valid cases to probe the input space. Antirandom testing selects each test case such that it is as different as possible from all the previous tests. The implementation is illustrated using benchmark examples that have been used in the literature. Use of random testing both with checkpoint encoding and without is also reported. Comparison and evaluation of the effectiveness of these methods is also presented. Implications of the observations for larger software systems are noted. Overall, antirandom testing gives higher code coverage than encoding random testing, which gives higher code coverage than pure random testing.

Combining the advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents the effects of bridging faults affecting p- or n-parts and input bridging faults of logical nodes affecting p- and n-parts. It is shown that bridging faults can be detected by I/sub DDQ/ monitoring in BiCMOS devices. An input pattern classification scheme is presented for bridging faults. These classes of input patterns are then used to obtain test sets for bridging fault detection.

One of the most important parameters that control reliability growth is the fault exposure ratio (FER) identified by J.D. Musa et al. (1991). It represents the average detectability of the faults in software. Other parameters that control reliability growth are software size and execution speed of the processor which are both easily evaluated. The fault exposure ratio thus presents a key challenge in our quest towards understanding the software testing process and characterizing it analytically. It has been suggested that the fault exposure ratio may depend on the program structure, however the structuredness as measured by decision density may average out and may not vary with program size. In addition FER should be independent of program size. The available data sets suggest that FER varies as testing progresses. This has been attributed partly to the non-randomness of testing. We relate defect density to FER and present a model that can be used to estimate FER. Implications of the model are discussed. This model has three applications. First, it offers the possibility of estimating parameters of reliability growth models even before testing begins. Secondly, it can assist in stabilizing projections during the early phases of testing when the failure intensity may have large short term swings. Finally, since it allows analytical characterization of the testing process, it can be used in expressions describing processes like software test coverage growth.

A new BiCMOS dynamic logic family is presented. The logic gates provide a significant speed-up over existing logic families, such as, CMOS, BiCMOS and dynamic CMOS for the same feature size. The proposed logic family provides high drive capability to drive large loads at higher speeds compared to CMOS domino logic family; there are power advantages due to dynamic operation compared to the conventional fully complementary CMOS and BiCMOS devices. It also has area advantage compared to that of the conventional BiCMOS gates. The proposed high-speed BiCMOS domino family provides speed improvement with existing feature size, using the existing fabrication technology.

In this paper, we propose an approach for linking the isolated research results together and describe a tool supporting the incorporation of the various existing modeling techniques. The new tool, named ROBUST, is based on recent research results validated using actual data. It employs knowledge of static software complexity metrics, dynamic failure data and test coverages for software reliability estimation and prediction at different software development phases.

Random testing is a well known concept that requires that each test is selected randomly regardless of the test previously applied. The paper introduces the concept of antirandom testing. In this testing strategy each test applied is chosen such that its total distance from all previous tests is maximum. Two distance measures are defined. Procedures to construct antirandom sequences are developed. A checkpoint encoding scheme is introduced that allows automatic generation of efficient test cases. Further developments and studies needed are identified.

The waiting time and queue length characteristics of isochronous, synchronous and asynchronous traffic at the gateway between FDDI-II and ATM networks are analyzed. A generalized approach to analyze various classes of traffic separately, is discussed. We first present an overview of our gateway model. Next, a deterministic analysis of isochronous traffic is presented. Synchronous and asynchronous classes of traffic are analyzed with the gateway model used. These results are compared with those generated by our simulator.

Analyzes the effect of input profile selection on software testing using the concept of a fault detectability profile. The optimality of the input profile during testing depends on factors such as the planned testing effort and the fault detectability profile. To achieve ultra-reliable software, it is preferable to select the test input uniformly among the different input domains. On the other hand, if the testing effort is limited due to cost or schedule constraints, one should test only the highly used input domains. Use of an operational profile is also needed for the accurate determination of operational reliability.>

Models the relationship between testing effort, coverage and reliability, and presents a logarithmic model that relates testing effort to test coverage: statement (or block) coverage, branch (or decision) coverage, computation use (c-use) coverage, or predicate use (p-use) coverage. The model is based on the hypothesis that the enumerables (like branches or blocks) for any coverage measure have different detectability, just like the individual defects. This model allows us to relate a test coverage measure directly to the defect coverage. Data sets for programs with real defects are used to validate the model. The results are consistent with the known inclusion relationships among block, branch and p-use coverage measures. We show how the defect density controls the time-to-next-failure. The model can eliminate variables like the test application strategy from consideration. It is suitable for high-reliability applications where automatic (or manual) test generation is used to cover enemerables which have not yet been tested.>

In BiCMOS, transistor stuck-OPEN faults exhibit delay faults in addition to sequential behavior. Stuck-ON faults cause enhanced I/sub DDQ/. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS. The faults in BiCMOS devices cause one or more parts (p-part or n-parts) of the circuit to exhibit a different state (conducting or nonconducting) from the fault-free circuit. An input pattern classification scheme is presented for different faults. These classes of patterns are then used to obtain test sets.>

The measurement and prediction of software reliability require the use of the software reliability growth models (SRGMs). The predictive quality can be measured by the average end-point projection error. In this paper, the effects of two orthogonal classes of approaches to improve prediction capability of a SRM have been examined using a large number of data sets. The first approach is preprocessing of data to filter out short term noise. The second is to overcome the bias inherent in the model. The results show that proper application of these two approaches can be more important than the selection of the model.

Software reliability engineering must develop beyond statistical analysis of data and analytic models which frequently require unrealistic assumptions. We must develop a viable discipline of simulation to aid experimental and industrial application of software reliability engineering. This will require developing standard modeling components, connections, tools, and a body of knowledge to interpret the phenomena that are being modeled. This paper explains how and why simulation models of software reliability can help to characterize the testing and debugging process more accurately. Examples are given to illustrate possible application of software reliability simulation.

The reliability models often assume random testing and statistical independence of faults to keep the analysis tractable. In practice, these assumptions do not hold. This paper presents a reliability modeling approach that considers nonrandom testing. This approach is used to calculate the fault exposure ratio, which characterizes the testing process. The analysis of the experimental data suggests that the fault exposure ratio varies differently in the early and the later stages of testing. The analysis here presents an explanation of this behavior.

BiCMOS devices exhibit sequential behavior under transistor stuck-open (s-open) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-open faults exhibiting sequential behavior need two or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented for single BJT BiCMOS logic gates which uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches or charge sharing among internal nodes. It requires only a single vector instead of the two or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults.>

The fault exposure ratio, K, is an important factor that controls the per-fault hazard rate, and hence, the effectiveness of the testing of software. The authors examine the variations of K with fault density, which declines with testing time. Because faults become harder to find, K should decline if testing is strictly random. However, it is shown that at lower fault densities K tends to increase. This is explained using the hypothesis that real testing is more efficient than strictly random testing especially at the end of the test phase. Data sets from several different projects (in USA and Japan) are analyzed. When the two factors, e.g., shift in the detectability profile and the nonrandomness of testing, are combined the analysis leads to the logarithmic model that is known to have superior predictive capability.>

It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered.>

Recently, neural networks have been applied for software reliability growth prediction. Although the predictive capability of the neural network models are better than some of the well known analytic models, the scaling problem has not been completely addressed yet. With the present neural network models, it is necessary to scale the cumulative faults over a 0.0 to 1.0 range, so the user has to estimate in advance a maximum value for the total number of faults to be detected at the end of the test phase. In practice, such an estimate may not be accurate. Use of an inaccurate value for scaling the cumulative faults can severely affect the predictive capability of neural network models. This paper presents a solution to the scaling problem which uses a clipped linear unit in the output layer. With a clipped linear output unit, the neural networks can predict positive values in any unbounded range. The authors demonstrate the applicability of the proposed network structure with three data sets and compare its predictive accuracy with that of earlier models. Expressions for the failure rate process represented by the models of the proposed network structure are also derived.>

The fault exposure ratio K is an important factor that controls the per-fault hazard rate, and hence the effectiveness of software testing. The paper examines the variations of K with fault density which declines with testing time. Because faults get harder to find, K should decline if testing is strictly random. However, it is shown that at lower fault densities K tends to increase, suggesting that real testing is more efficient than random testing. Data sets from several different projects are analyzed. Models for the two factors controlling K are suggested, which jointly lead to the logarithmic model.>

The logic behavior of single BJT BiCMOS devices under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behaviour of bipolar (TTL) and CMOS logic families is compared with BiCMOS. Effects of bridging faults in BiCMOS devices has been examined for both hard short as well as bridging with a significant resistance.>

The usefulness of connectionist models for software reliability growth prediction is illustrated. The applicability of the connectionist approach is explored using various network models, training regimes, and data representation methods. An empirical comparison is made between this approach and five well-known software reliability growth models using actual data sets from several different software projects. The results presented suggest that connectionist models may adapt well across different data sets and exhibit a better predictive accuracy. The analysis shows that the connectionist approach is capable of developing models of varying complexity.>

Bipolar emitter coupled logic (ECL) devices can now be fabricated at high densities and lower power consumption. With the achievement of low power and high densities, ECL technology is expected to be used widely in high performance digital circuits. This necessitates the need for obtaining optimum gate level models for ECL circuits. A simple technique to obtain a gate level model of an ECL circuit is presented. The gate level models obtained for 1-level and 2-level ECL using the transformation rules presented are the same as the fault models that provide higher coverage of physical failures.>

Software reliability growth models have achieved considerable importance in estimating reliability of software products. The authors explore the use of feed-forward neural networks as a model for software reliability growth prediction. To empirically evaluate the predictive capability of this new approach, data sets from different software projects are used. The neural networks approach exhibits a consistent behavior in prediction and the predictive performance is comparable to that of parametric models.>

Built-in self-test (BIST) technique is now widely applied. How to estimate its testing capabilities is an important problem. BIST detectability is defined as the probability of that a fault set of the circuit-under-test is detected. It depends on the properties of the test at, circuit-under-test, as well as the signature analyser as a data compressor. The detectability of a signature analyzer is evaluated. The random and pseudorandom testing techniques are examined for their BIST detectability and several results are derived.>

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest as logical faults, and would not be detected by traditional IC test techniques. In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to normal parameter variations. A statistical characterisation of the problem is presented. This can be used to determine the optimal size of partitions. A new information compression scheme is presented which can significantly enhance resolution.>

The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.>

A rigorous mathematical analysis is presented to identify error conditions under which aliasing can occur for several common types of serial signature analyzers (SSAs) and parallel signature analyzers (PSAs). The PSAs are faster and require less hardware than the SSAs; however, for PSAs some double errors are a special cause of concern. Such aliasing errors are analyzed and it is shown that PSA pairs can be identified for which these errors are disjoint. Novel reconfigurable PSA designs are presented which use a two-signature scheme to detect all double errors.>

A two-component predictability measure is presented that characterizes the long-term predictability of a software reliability growth model. The first component, average predictability, measures how well a model predicts throughout the testing phase. The second component, average bias, is a measure of the general tendency to overestimate or underestimate the number of faults. Data sets for both large and small projects from diverse sources have been analyzed. The results seem to support the observation that the logarithmic model appears to have good predictability is most cases. However, at very low fault densities, the exponential model may be slightly better. The delayed S-shaped model which in some cases has been shown to have good fit, generally performed poorly.>

CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two pattern tests. Two or multi-pattern sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods for augmenting CMOS gates to test CMOS stuck-open faults, are found to be inadequate in the presence of glitches. A new CMOS testable design is presented. The scheme uses two additional MOSFETs, which convert a CMOS gate to either pseudo nMos or pseudo pMOS gate during testing. The proposed design ensures the detection of stuck-open faults using a single vector during testing

Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch-level modeling under such conditions.>

Bridging faults have been shown to be a major failure mode in VLSI devices. This study examines nMOS and CMOS complex gates in detail for bridging faults. Analysis is carried out using both switch and circuit level models for comparison. It is shown that in most cases, the switch level analysis predicts the correct behavior. A set of conditions are presented, under which the switch level analysis may fail to predict the correct behavior. These conditions can be used for accurate switch level test generation and simulation.

Practical solutions have not been obtained from the previous papers addressing the problem of testing intermittent faults in sequential circuits. Existing methods are only suitable for small sequential circuits. This correspondence presents a new technique to design test-experiments for intermittent faults which can conveniently be used for relatively more complex synchronous sequential circuits.

While significant results are available which allow estimation of reliability measure for systems with permanent faults, no generally applicable results are available for intermittent (transient) faults. Methods are presented here which allow reliability evaluation for systems with both intermittent and permanent faults. Two reliability measures, instantaneous and durational reliabilities, are defined and methods to compute them are given. Computed results for the durational reliability for various redundancy schemes are compared.

A continuous-parameter Markov model for intermittent faults in digital systems is presented. This continuous model is more realistic than discrete-parameter models previously presented by other authors. The results obtained using the proposed model can be reduced to those obtained from the previous models, by using appropriate approximations.