In 1999, the National Science Foundation created the "Computer Science, Engineering, and Mathematics Scholarships" (CSEMS) program to provide funding for institutions to supply scholarships for academically talented and financially needy students to complete an associate, baccalaureate, or graduate degree in computer science, computer technology, engineering, engineering technology, or mathematics. In 2004, the program was renamed to "Scholarships for Science, Technology, Engineering, and Mathematics" (S-STEM) and modified to include students from physical and life sciences. Appalachian State University (ASU) has been the recipient of four CSEMS/S-STEM awards since 2001 and the scholarships have funded 161 students. Nearly all of these students have high levels of financial need and the majority are first generation college students. Overall, the program has retained 87 percent of these students; 12 percent of the scholars completed a bachelor's and then continued on to complete a master's degree or are in the process of doing so. The retention rate has increased as our program has improved. The retention rate of the current cohort of S-STEM students is 92.3 percent; 31 percent of the students in the current program completed a bachelor's degree and are pursuing or have completed a master's degree. These retention numbers are significantly higher than the 31 percent national average reported by the U.S. Department of Education. In addition, these retention numbers are higher than those found at our own institution for all Computer Science and Mathematics majors. This paper discusses the components of our successful program.

This paper investigates the impact of layers of quizzing on student performance on subsequent tests and the final exam. The first layer of quizzes are on-line "pre-quizzes" designed to prepare students for follow-on classroom discussions. The second layer quizzes are short "post-quizzes" that are given during class time after discussing questions about the material covered by pre-quizzes. A study involving fifteen semesters of data and 348 students indicated that students performed better on tests and the final exam with this quizzing strategy compared to a more traditional homework based approach. These results agree with the body of research that indicates that testing enhances learning. Significantly, we found an 8 point pass rate increase on the Computer Systems I final exam and a 10 point pass rate increase on the Systems II final.

Assessment of student learning through tests, or examinations, is one of those necessary evils. No one seems to enjoy it, but everyone admits the necessity of it. Reducing student anxiety and frustration is an important activity to obtain a meaningful assessment of their learning. A common way for teachers to help students prepare is with a review session. This paper describes a structured review technique that actively engages every student in a multisensory way, requires little work on the part of the instructor, and is both entertaining and fun. Most important, this paper describes an empirical study that demonstrates the dramatic efficacy of the technique.

The small instruction set size of the LC-3 as well as its similarities to more powerful instruction sets make it an ideal hypothetical machine for introductory computer science and computer engineering students. Several tools are available for working with this hypothetical machine including simulators, and assemblers for various platforms. We have created an additional tool, LC3uArch, that is useful for debugging LC-3 programs like the existing simulators, but unlike existing simulators also helps student to develop an understanding of the LC-3 microarchitecture. The results of a student survey on the use of LC3uArch indicate our students find LC3uArch a valuable learning tool.

This paper reports on the progress of an NSF funded research project investigating the development practices of students in introductory programming courses. In previous work, we describe our extension of the BlueJ IDE to capture events associated with program development. Here we report on data collected during the Fall 2007 and Spring 2008 semesters on CS 1 students. In particular, we show that our data analysis independently confirms the results obtained in separate studies by Jadud [3, 2]. In addition we use our empirical evidence to discern some higher level "patterns" of beginning student programming behaviors including potential cheating and the impact on success of students starting projects late.

The Information Technology sector is suffering from a dramatic reduction in the number of students studying the field and subsequently entering the IT market. The number of freshmen expressing "interest in CS" has dramatically decreased since 2000 [16] and CS attrition rates are very high (DUE 0633640). As part of an effort funded by the National Science Foundation (DUE 0633640), this paper introduces the ClockIt toolset that we believe can be used to help educators understand and reduce the high attrition rates of CS 1 and CS 2 students. Using ClockIt, we can unobtrusively monitor and log student software development activities allowing us to determine what practices make a student a successful software developer and what practices do not.

In traditional computer science curricula, students view program implementation as the end product and not the means to obtaining some further result. All too often students complete an implementation at the last minute, perform a minimal amount of testing and call the assignment done! This paper discusses an approach we have taken in our courses to have students use and develop programs as part of a scientific inquiry. In addition to causing students to perform more thorough testing, our approach also improves empirical and critical thinking skills.

In an effort to improve the communication skills of students, many universities are requiring computer science educators to include writing and speaking components in their courses. This paper describes an alternative to the classic term paper assignment. A "student conference" approach has been successfully employed in a junior-level computer systems course for five semesters. Each student performs an implementation and experimental study, then writes a research-style technical paper on this work. Students also participate in an anonymous review process, revise their own papers, and make oral presentations of their work. The structure of this conference approach, representative assignments, and observations are presented.

This paper describes the design and implementation of a register allocator that performs the allocation over the Program Dependence Graph (PDG) representation of a routine. The PDG representation has been used successfully as the basis for various scalar optimizations, as well as for detecting and improving parallelization for vector machines, multiple processor machines, and architectures that exhibit instruction level parallelism. Variations of the PDG have also been used for debugging and integrating different versions of a program via program-slicing, and to enable translation of imperative programs for data-flow machines and demand-driven graph reducers. By basing register allocation on the PDG, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations. In addition, the advantages of a hierarchical approach to global register allocation can be attained without constructing an additional structure used solely for register allocation. © 1998 John Wiley & Sons, Ltd.

Compile-time reordering of low level instructions is successful in achieving large increases in performance of programs on fine-grain parallel machines. However, because of the interdependences between instruction scheduling rand register allocation, a lack of cooperation between the schedules and register allocator can result in generating code that contains excess register spills and/or a lower degree of parallelism than actually achievable. This paper describes a strategy for providing cooperation between register allocation and both global and local instruction scheduling. We experimentally compare this strategy with other cooperative and uncooperative scenarios. Our experiments indicate that the greatest speedups are obtained by performing either cooperative or uncooperative global instruction scheduling with cooperative register allocation and local instruction scheduling.

This paper describes RAP, a Register Allocator that allocates registers over the Program Dependence Graph (PDG) representation of a program in a hierarchical manner. The PDG program representation has been used successfully for scalar optimizations, the detection and improvement of parallelism for vector machines, multiple processor machines, and machines that exhibit instruction level parallelism, as well as debugging, the integration of different versions of a program, and translation of imperative programs for data flow machines. By basing register allocation on the PDG, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations. In addition, the advantages of a hierarchical approach to global register allocation can be attained without constructing an additional structure used solely for register allocation. Our experimental results have shown that on average, code allocated registers via RAP executed 2.7% faster than code allocated registers via a standard global register allocator.

Compile-time reordering of machine-level instructions has been very successful at achieving large increases in performance of programs on machines offering fine-grained parallelism. However, because of the interdependences between instruction scheduling and register allocation, it is not clear which of these two phases of the compiler should run first to generate the most efficient final code. The authors describe their investigation into slight modifications to key phases of a successful global register allocator to create a scheduler-sensitive register allocator, which is then followed by an off-the-shelf instruction scheduler. These experimental studies reveal that this approach achieves speedups comparable and increasingly better than previous cooperative approaches with an increasing number of available registers without the complexities of the previous approaches.