This paper explores the critical task of analyzing running postures and recognizing their key roles in enhancing athletic performance and averting injuries. Our approach inte-grates AI technologies, with video pose estimation and kinematic analysis, to offer comprehensive and detailed feedback on a runner's posture and technique. Leveraging MediaPipe, an ad-vanced deep learning framework, we conduct thorough kinematic analyses by tracking essential body landmarks and analyzing four fundamental postures: toe-off, maximal vertical projection, touch-down, and full-support. The classification of these postures is facilitated by a random forest tree classifier, which consistently demonstrates high accuracy, and is validated by experienced coaches. Our system goes beyond simple classification; it provides detailed feedback, highlights distinctions in form and technique, and assists runners and coaches in refining performance. This methodology not only optimizes athletic prowess but also analyzes real-world track running data, as opposed to unnatural data collected by laboratory-based systems.

Patients with drug-resistant focal seizures are usually recommended with surgery for seizure freedom or reduction. The traditional open resection, which is to surgically remove epileptogenic zones, requires open lobectomy that are risky to cause post-surgery complications. Minimal invasive surgery (MIS) approaches, including laser interstitial thermal therapy (LITT) and responsive neurostimulation (RNS), are effective to significantly reduce (or achieve zero) seizures without risk of open resection. Stereo-electroencephalography (SEEG) is a promising technique for pre-surgery evaluation by implanting depth electrodes to collect brain activities. This paper presents a SEEG analyzing method to determine the LITT/RNS targets for patients with focal seizures. A seizure network (graph) model is proposed to characterize the spatial distribution and temporal changes of ictal events. Two network metrics, the outflux and influx values, are defined to characterize the nodal contributions to seizures. A clustering strategy is then proposed to group nodes (a subset of selected SEEG contact points) into several clusters based on outflux/influx values. Retrospective data from six patients with both unilateral and bilateral focal seizures were analyzed. Promising consistency were observed between results of our computational method and clinical decisions.

Over 30% of epilepsy patients are resistant to anti-seizure medication. For these patients, surgery resection remains a promising method to render seizure-free outcome by removing the hypothesized epileptogenic zone (EZ), the areas contributing to seizure generation, onset and early propagation. Stereoelectroencephalography (SEEG), a technique to collect deep brain activities, has become a promising method during pre-surgery evaluation. This paper presents a method to model seizure activities as a network graph using SEEG data collected from a patient with focal seizures. This model characterizes the spatial and temporal progress of ictal events, where network nodes are contact points and edge weights are values of directed transfer function (DTF). A clustering strategy is then employed to group the nodes into different clusters to assist clinicians identify surgery candidate zones. Consistency between our analysis and clinical decision for a case study shows the potential of our method for pre-surgery evaluation.

Real-time classification of Electromyography signals is the most challenging part of controlling a prosthetic hand. Achieving a high classification accuracy of EMG signals in a short delay time is still challenging. Recurrent neural networks (RNNs) are artificial neural network architectures that are appropriate for sequential data such as EMG. In this paper, after extracting features from a hybrid time-frequency domain (discrete Wavelet transform), we utilize a set of recurrent neural network-based architectures to increase the classification accuracy and reduce the prediction delay time. The performances of these architectures are compared and in general outperform other state-of-the-art methods by achieving 96% classification accuracy in 600 msec

Approximately, one third of patients with epilepsy are refractory to medical therapy and thus can be at high risk of injuries and sudden unexpected death. A low-complexity electroencephalography (EEG)-based seizure monitoring algorithm is critically important for daily use, especially for wearable monitoring platforms. This paper presents a personalized EEG feature selection approach, which is the key to achieve a reliable seizure monitoring with a low computational cost. We advocate a two-step, personalized feature selection strategy to enhance monitoring performances for each patient. In the first step, linear discriminant analysis (LDA) is applied to find a few seizure-indicative channels. Then in the second step, least absolute shrinkage and selection operator (LASSO) method is employed to select a discriminative subset of both frequency and time domain features (spectral powers and entropy). A personalization strategy is further customized to find the best settings (number of channels and features) that yield the highest classification scores for each subject. Experimental results of analyzing 23 subjects in CHB-MIT database are quite promising. We have achieved an average F-1 score of 88% with excellent sensitivity and specificity using not more than 7 features extracted from at most 3 channels.

Electroencephalography (EEG) signal monitoring can be applied for many purposes, such as epileptic seizure detection. To design a reliable, wearable EEG monitoring platform for seizure detection in daily use, this paper presents a two-step approach to select a small subset of discriminative features from a few number of channels. In the first step, linear discriminant analysis (LDA) is applied to choose informative channels which have highly-ranked LDA criterion values. Then in the second step, the least absolute shrinkage and selection operator (LASSO) method is adopted to incrementally add features into selection subset. To determine the best number of channels and features for each subject, a personalization technique is utilized by evaluating the classification result of different feature subsets based on support vector machine (SVM) classifier. Experimentation on CHB-MIT database shows that on average, the proposed method selects approximately 3 channels and 7 features, and yields F-1 score of 81% based on SVM evaluation.

BACKGROUND: Identifying drug-target interaction is a key element in drug discovery. In silico prediction of drug-target interaction can speed up the process of identifying unknown interactions between drugs and target proteins. In recent studies, handcrafted features, similarity metrics and machine learning methods have been proposed for predicting drug-target interactions. However, these methods cannot fully learn the underlying relations between drugs and targets. In this paper, we propose anew framework for drug-target interaction prediction that learns latent features from drug-target interaction network. RESULTS: We present a framework to utilize the network topology and identify interacting and non-interacting drug-target pairs. We model the problem as a semi-bipartite graph in which we are able to use drug-drug and protein-protein similarity in a drug-protein network. We have then used a graph labeling method for vertex ordering in our graph embedding process. Finally, we employed deep neural network to learn the complex pattern of interacting pairs from embedded graphs. We show our approach is able to learn sophisticated drug-target topological features and outperforms other state-of-the-art approaches. CONCLUSIONS: The proposed learning model on semi-bipartite graph model, can integrate drug-drug and protein-protein similarities which are semantically different than drug-protein information in a drug-target interaction network. We show our model can determine interaction likelihood for each drug-target pair and outperform other heuristics.

In this paper, a heterogeneous graph of drug-target entities are constructed to predict drug-protein interactions. We use a deep learning approach and apply an encoder-decoder technique in an end-to-end manner directly on a full-scale heterogeneous graph. The proposed method not only achieves performance improvement over previous state-of-the-art techniques, but also integrates additional information into the model for a more comprehensive analysis.

We present our patient activity monitoring system with the aim of aiding informed clinical decision-making that encourages early and progressive ambulation (EPA). EPA has been shown to reduce the risk of many serious complications experienced by hospitalized patients. To achieve our goal, we employed a preexisting real-time location system (RTLS). We developed algorithms which leverage the data from an RTLS to determine the distance traveled, average velocity, time in zones-of-interest, and inactivity of patients to accurately inform clinicians of patient activities.

This research focuses on quantifying human activity for healthcare applications. Distance traveled, average velocity, and postures are the primary focus. A Microsoft Kinect V2 camera was used to collect data for analysis. By tracking the human head, position relative to the camera can be determined. Accuracy of at least 87% was achieved for distance traveled and average velocity measurements. For posture detection, accuracy of at least 80% was achieved.

Monitoring acoustic emission from mechanical systems is an effective non-invasive way of diagnosing both system performance as well as short-term/long-term system failures. A difficulty however in fault detection in such systems is inter-class variability caused by non-uniform or unknown load conditions which decrease the classification accuracy. In this paper, a scattering transform is employed to diagnose gearbox faults using acoustic emission analysis. The results analysis and solution shows that a two layer scattering transform can diagnose four gearbox faults with an average accuracy of 97% even if the system is not exposed to data of all loads in the training phase.

Persons who suffer from intractable seizures are safer if attended when seizures strike. Consequently, there is a need for wearable devices capable of detecting both convulsive and nonconvulsive seizures in everyday life. We have developed a three-stage seizure detection methodology based on 339 h of data (26 seizures) collected from 10 patients in an epilepsy monitoring unit. Our intent is to develop a wearable system that will detect seizures, alert a caregiver and record the time of seizure in an electronic diary for the patient's physician. Stage I looks for concurrent activity in heart rate, arterial oxygenation and electrodermal activity, all of which can be monitored by a wrist-worn device and which in combination produce a very low false positive rate. Stage II looks for a specific pattern created by these three biosignals. For the patients whose seizures cannot be detected by Stage II, Stage III detects seizures using limited-channel electroencephalogram (EEG) monitoring with at most three electrodes. Out of 10 patients, Stage I recognized all 11 seizures from seven patients, Stage II detected all 10 seizures from six patients and Stage III detected all of the seizures of two out of the three patients it analyzed.

Single-cell flow cytometry is a technology that measures the expression of several cellular markers simultaneously for a large number of cells. Identification of homogeneous cell populations, currently done by manual biaxial gating, is highly subjective and time consuming. To overcome the shortcomings of manual gating, automatic algorithms have been proposed. However, the performance of these methods highly depends on the shape of populations and the dimension of the data. In this paper, we have developed a time-efficient method that accurately identifies cellular populations. This is done based on a novel technique that estimates the initial number of clusters in high dimension and identifies the final clusters by merging clusters using their phenotypic signatures in low dimension. The proposed method is called SigClust. We have applied SigClust to four public datasets and compared it with five well known methods in the field. The results are promising and indicate higher performance and accuracy compared to similar approaches reported in literature.

Reliability of power converters is crucial for mission critical systems. Among the components that are susceptible to failure, power semiconductor devices are one of the major causes of the power converter failures. This paper focuses on the remaining useful lifetime (RUL) estimation of degraded power MOSFETs, which are stressed by thermal cycling. The relative change in on-state resistance is identified as the fault signature. A data-driven RUL estimation algorithm based on a linear approximation model is proposed. The empirical coefficients are estimated by the classical least squares, where the outliers are removed by random sample consensus (RANSAC) algorithm. A sliding window approach is used to track the nonlinearities. The window size, threshold value, and number of samples used by RANSAC are optimized with the genetic algorithm. The accuracy of the proposed RUL estimation tool is verified on a number of thermally aged discrete power MOSFET data.

Complex tissues such as brain and bone marrow are made up of multiple cell types. As the study of biological tissue structure progresses, the role of cell-type-specific research becomes increasingly important. Novel sequencing technology such as single-cell cytometry provides researchers access to valuable biological data. Applying machine-learning techniques to these high-throughput datasets provides deep insights into the cellular landscape of the tissue where those cells are a part of. In this paper, we propose the use of random-forest-based single-cell profiling, a new machine-learning-based technique, to profile different cell types of intricate tissues using single-cell cytometry data. Our technique utilizes random forests to capture cell marker dependences and model the cellular populations using the cell network concept. This cellular network helps us discover what cell types are in the tissue. Our experimental results on public-domain datasets indicate promising performance and accuracy of our technique in extracting cell populations of complex tissues.

Analog circuits contribute to as much test cost as digital circuits. Traditional model-based testing (e.g. catastrophic, range-based, regression models) had limited success due to diversity of circuits and contributing metrics. We propose a model-free analog circuit testing using a combination of advanced signal processing and machine learning techniques with low computation and memory requirements. These unique features make the proposed test methodology scalable, reusable and suitable for both off-chip and on-chip test possibilities.

Negative Bias Temperature Instability (NBTI) induced transistor aging has become one of the major reliability concerns in sub-micron circuit as technology scales. Transistor performance degrades over time and may eventually cause timing violations and circuit failure. Multi-Vthis known as a method to improve circuit performance with leakage and timing tradeoffs. In this paper, we propose a heuristic metric, which could be used to capture leakage and timing tradeoff during multi-Vthoptimization. Our technique is an after-aging delay minimization problem under leakage power constraint. The experimental results on ISCAS85 benchmark circuits at 45nm node show up to 17% after-aging delay improvement within the predefined leakage power constraint.

Automatic fault diagnosis is an inseparable part of today's electromechanical systems. Advanced signal processing and machine learning techniques are required to address variabilities and uncertainties associated with the monitoring signals. In this paper, deep neural networks are employed to diagnose five classes of gearbox faults applied to three common monitoring signals, i.e. vibration, acoustic and torque. Discrete wavelet transform is used to provide the initial features as the inputs of the network. A test-rig based on a 250W three-phase squirrel cage induction machine shaft connected to a single stage helical gear is built for validation of the proposed method. The experimental results indicate accurate fault diagnosis in various conditions such as different modalities, signal variabilities, and load conditions.

Measurement of various markers of single cells using flow cytometry has several biological applications. These applications include improving our understanding of behavior of cellular systems, identifying rare cell populations and personalized medication. A common critical issue in the existing methods is approximation of the number of cellular populations which heavily affects the accuracy of results. In this work, we propose a novel technique to estimate the number of dominant subtypes and identify them in flow cytometry datasets. Our experimentation on 42 flow cytometry datasets indicates high performance and accurate clustering (F-measure > 91%) in identifying the main cellular populations.

Recent advances in computer processor design have led to the introduction of sub-blocking to cache architectures. Sub-block caches reduce the tag area and power overhead in caches without reducing the effective cache size by using fewer tags to index the full data RAM array. In spite of achieving reduced area and power overhead, sub-block caches suffer performance degradation due to cache trashing. This occurs when a wider cache line (super-block), made up of multiple valid cache lines (sub-blocks), is replaced or evicted when only a sub-block is to be allocated into the wider super-block. To address this problem, we propose cache replacement policies as they relate specifically to sub-block caches. We propose new replacement policies that are tuned for sub-block caches by adding more intelligence based on the valid state of individual sub-blocks of a super-block. We also investigate the effect of using a few level-0 registers to bypass a few level-1 cache pipe stages on sub-block cache performance. To evaluate the performance improvement offered by our proposed replacement policies and the use of level-0 registers, we developed a sub-block cache simulator based on the Simplescalar toolset for single-core evaluations and the Sniper Simulator for multicore evaluations. We show that, with minimal architectural updates to existing conventional cache replacement policies, we are able to improve level-1 cache hit rates by up to 4.17% using our proposed policies alone on SPEC2006 benchmarks and up to 14% in shared level-2 caches using multicore benchmark suites: PARSEC and SPLASH2.

We propose an algorithm for separating arterial and venous-related signals using second-order statistics of red and infrared signals in a blind source separation technique. The separated arterial signal is used to compute accurate arterial oxygen saturation. We have also introduced an algorithm for extracting the respiratory pattern from the extracted venous-related signal. In addition to real-time monitoring, respiratory rate is also extracted. Our experimental results from multiple subjects show that the proposed separation technique is extremely useful for extracting accurate arterial oxygen saturation and respiratory rate. Specifically, the breathing rate is extracted with average root mean square deviation of 1.89 and average mean difference of -0.69.

We propose a technique that reduces static power consumption in caches with negligible hardware overhead and no performance penalties. Our proposed architecture achieves this by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in the immediate future by exploiting in-flight cache access information. We simulated our architecture using the Simplescalar and Cacti toolsets, and observed up to 92% reduction in static power consumption in SPEC2006 benchmarks with no performance penalties and minimal hardware overhead.

Performance degradation due to transistor aging is a significant impediment to high-performance IC design due to increasing concerns of reliability mechanisms such as negative-bias-temperature-instability (NBTI). The concern only grows with technology scaling as the effects of positive bias temperature instability (PBTI) is becoming prominent in future technologies and compounding with the effects of NBTI. Although aging of transistor is inevitable and the magnitude of degradation due to aging varies depending upon the context. Specifically, in power-efficient systems designs, the logic and clock paths are susceptible to static stress resulting in peak degradation due to BTI occurrence when clock is gated. In this article, we present the reliability impact of making systems power efficient and propose a design-for-reliability methodology that can be used in conjunction with low-power design techniques to alleviate the stress conditions caused by rendering circuits in idle state. The technique— BTI-Refresh , is shown to be applicable to both logic and clock paths alike and focuses on preventing prolonged static stress using periodic refreshes to achieve alternating stress. The mechanism is shown to integrate seamlessly into the design at gate-level without requiring any architectural or RT-level changes. Using ISCAS benchmarks and Kogge-Stone-Adder circuits, it is shown to reduce the aging effect in logic path delay due to static stress by up to 50% with negligible area and power overhead. BTI-Refresh is extended to clock-paths to prevent pulse-width degradation due to static aging and with minimal clock-skew.

The performance of portable and wearable biosensors is highly influenced by motion artifact. In this paper, a novel real-time adaptive algorithm is proposed for accurate motion-tolerant extraction of heart rate (HR) and pulse oximeter oxygen saturation ( SpO2) from wearable photoplethysmographic (PPG) biosensors. The proposed algorithm removes motion artifact due to various sources including tissue effect and venous blood changes during body movements and provides noise-free PPG waveforms for further feature extraction. A two-stage normalized least mean square adaptive noise canceler is designed and validated using a novel synthetic reference signal at each stage. Evaluation of the proposed algorithm is done by Bland-Altman agreement and correlation analyses against reference HR from commercial ECG and SpO2 sensors during standing, walking, and running at different conditions for a single- and multisubject scenarios. Experimental results indicate high agreement and high correlation (more than 0.98 for HR and 0.7 for SpO2 extraction) between measurements by reference sensors and our algorithm.

Pressure ulcer is a major problem for bed-bound and wheelchair-bound individuals specially in regions like sacrum, buttocks, hip, heels, back and head. Once developed, it is extremely uncomfortable and costly. Identification and monitoring of high-risk regions and their pressure distributions help nurses to have information about risk in each specific area of body and reposition patient efficiently. In this paper, we propose an algorithm to detect regions that are under high stress. Because of low resolution nature of pressure image and changes in shape of human body parts in various images, we adopted image processing algorithms. The image of human body is segmented using Delaunay triangulation. The extracted tree is compared to defined template for each posture. Then, signal processing and graph matching algorithms are used to label the tree according to the template. Pressure values of each specific region are collected for other phases of ulcer management such as risk assessment and reposition schedule. The experimental results indicate that our method can detect 9 (6) regions in supine (side) postures with average accuracy of 85.7%.

We have developed a real-time sleep apnea monitoring system called “Apnea MedAssist II”. This has three independent sensors: ECG, SpO2 and Breath sensor. These sensors are connected to a smartphone via Bluetooth. The signal processing of the sensor signals and automated classification of a sleep epoch as an apnea event or a non-apnea event are done in a smart phone. The soft ware for signal processing and automated classification can be imported to an Android OS based smart phones as an `app' that we have developed. The system has accuracy well over 97% when tested on Physionet database. The system is being readied for limited patient trial.

A realistic, as opposed to fixed pessimistic end-of-life method to identify paths that are at-risk to excessive degradation due to aging is presented. It uses library cell grading information to assess the cells/instances for their sensitivity to parametric degradation.

The foot complications constitute a tremendous challenge for diabetic patients, caregivers, and the healthcare system. With current technology, in-shoe monitoring systems can be implemented to continuously monitor foot's at-risk ulceration sites and send feedback to patients and physicians. The few available high resolution in-shoe pressure measuring systems are extremely expensive and targeting clinical use only. The more affordable price ranges can be reached by limiting the number of sensors in the shoe. Precise subject-specific sensor placement is still a challenge in such platforms. Moreover, there is no good way to estimate pressure on other points of the foot. In this paper, we address these technical challenges by proposing SCPM algorithm that reconstructs a continuous foot plantar pressure image from a sparse set of sensor readings. Using our technique, sensor placement can be the same in every electronic insole. However, the SCPM's trained parameters are unique for every subject and foot.

Negative Bias Temperature Instability (NBTI) degrades the life-time of both the analog and digital circuits significantly and has become a major concern in nanoscale regime. In analog circuits, the DC biasing voltage is always present irrespective of the input signal. Therefore, coupled with high operating temperature (due to digital switching and high packaging density of SoC) and constant DC bias there would be continuous NBTI stress in analog circuits with minor or almost no recovery. Moreover, mismatch and input referred offset voltage caused by NBTI in differential pairs, current sources and cascode stages can cause instantaneous failure or catastrophic failure after certain time period. The problem of NBTI is usually addressed by leaving large design margins or employing adaptive body bias/adaptive voltage scaling based calibration algorithms using on-chip sensors or monitors. We present an ultra low power and small area on-chip NBTI sensor which can be used for accurately sensing the NBTI degradation in analog circuits. We have shown that the temporal degradation in threshold voltage of pMOS transistor in analog circuits has high correlation to the variation of reference voltage of our NBTI sensor which can be exploited for accurate calibration of analog circuits. Measurement results are also provided for the proposed sensor fabricated in commercially available 65nm process.

Pressure ulcer is a critical problem for bed-ridden and wheelchair-bound patients, diabetics, and the elderly. Patients need to be regularly repositioned to prevent excessive pressure on a single area of body, which can lead to ulcers. Pressure ulcers are extremely costly to treat and may lead to several other health problems, including death. The current standard for prevention is to reposition at-risk patients every two hours. Even if it is done properly, a fixed schedule is not sufficient to prevent all ulcers. Moreover, it may result in nurses being overworked by turning some patients too frequently. In this paper, we present an algorithm for finding a nurse-effort optimal repositioning schedule that prevents pressure ulcer formation for a finite planning horizon. Our proposed algorithm uses data from a commercial pressure mat assembled on the beds surface and provides a sequence of next positions and the time of repositioning for each patient.

Pressure ulcer is a severe threat for immobilized and peripheral neuropathic patients such as bed-ridden, elderly, and diabetics. Once developed, the complication of pressure ulcer causes pain, suffering, and longer hospitalization for the patients. Additionally, pressure ulcer management imposes a serious burden on the health care providers. The optimal strategy to deal with pressure ulcers is prevention. The current standard for prevention is to reposition at-risk patients every two hours. But, each patient has different needs based on overall vulnerability and damaged skin areas. A fixed schedule may either result in some patients getting ulcers, or nurses being overworked by turning some patients too frequently. In this paper, we present an efficient algorithm to find a repositioning schedule for bed- bound patients based on their risk of ulcer development. Our proposed algorithm uses data from a commercial pressure mat assembled on the bed's surface and provides a sequence of next positions and the time of repositioning for each patient. Our patient-specific turning schedule minimizes the overall cost of nursing staff involvement in repositioning the patients while simultaneously decreases the chance of pressure ulcer formation.

Network intrusion detection systems continuously monitor the network traffic in order to identify any traces of suspicious activities such as worm, viruses or spam. One attractive technique for identifying potential Internet threats is detecting previously unknown, but common sub-strings that appear very frequently in data packets. In this paper, we propose a novel architectural platform that thoroughly analyzes the network traffic behavior in terms of repetitions to identify potential Internet threats. The main idea is to use a two-phase hashing system and small memory units functioning in parallel to achieve a high-throughput and memory efficient behavioral analysis engine. The system performs behavioral analysis on selected information/user(s) and builds a bell-shaped curve for normal traffic using parallel counters. Our traffic behavioral analysis system has been fully prototyped on Altera Stratix FPGA. Experimental results verify that our system can support line speed of gigabit-rates with very negligible false positive and negative rates.

Recent trends in clinical and telemedicine applications highly demand automation in (electrocardiogram) ECG signal processing and heart beat classification. A real-time patient-adaptive cardiac profiling scheme using repetition detection is proposed in this paper. We introduce a novel local ECG beat classifier to profile each patient's normal cardiac behavior. As ECG morphologies vary from person to person, and even for each person, it can vary depending on the person's physical condition, having such profile is essential for various diagnosis (e.g. arrhythmia) purposes, and can successfully raise an early warning flag for the abnormal cardiac behavior of any individual. Experimental results show that our technique follows the MIT/BIH arrhythmia database annotations with high accuracy.

Recent trends in clinical and telemedicine applications highly demand automation in electrocardiogram (ECG) signal processing and heart beat classification. A patient-adaptive cardiac profiling scheme using repetition-detection concept is proposed in this paper. We first employ an efficient wavelet-based beat-detection mechanism to extract precise fiducial ECG points. Then, we implement a novel local ECG beat classifier to profile each patient's normal cardiac behavior. ECG morphologies vary from person to person and even for each person, it can vary over time depending on the person's physical condition and/or environment. Having such profile is essential for various diagnosis (e.g., arrhythmia) purposes. One application of such profiling scheme is to automatically raise an early warning flag for the abnormal cardiac behavior of any individual. Our extensive experimental results on the MIT-BIH arrhythmia database show that our technique can detect the beats with 99.59% accuracy and can identify abnormalities with a high classification accuracy of 97.42%.

Redundancy-based techniques have been widely used to correct the faulty behavior of components and achieve high reliability.N-tuple modular redundancy (NMR) systems, in particular, are all based on majority voting. The voter unit therefore becomes a bottleneck for the correct operation of any NMR system. In this paper, we propose a novel current-based voting strategy to design a robust NMR system. We show that, with this inexpensive strategy, we can completely eliminate the centralized voter unit and push NMR to the logic gate level. Our strategy achieves high reliability that is vital for future nanotechnology in which a high defect rate is expected. At the same time, it consumes less power and has less propagation delay compared to conventional NMR systems. Experimental results are reported to verify the concept, clarify the design procedure, and measure the system's reliability.

Redundancy techniques, such as N -tuple modular redundancy (NMR), has been widely used to correct faulty behavior of components and achieve high reliability. Almost all redundancy-based strategies rely on a majority voting. The voter, therefore, becomes a critical unit for the correct operation of any NMR system. In this paper, we propose a voterless fault-tolerant strategy to implement a robust NMR system design. We show that using a novel fault-tolerant communication mechanism, namely logic code division multiple access, we can transfer data with extremely low error rates among N modules and completely eliminate the need for a centralized voter unit. Such a highly reliable strategy is vital for future nanosystems in which high defect rate is expected. Experimental results are also reported to verify the concept, clarify the design procedure, and measure the system's reliability.

Most conventional packet classifiers find only the highest priority filter that matches the arriving packet. However, new networking applications such as network intrusion detection systems and load balancers require all (or the first few) matching packets during classification. In this paper, two TCAM-based architectures for multi-match search are introduced. The first one is a renovated TCAM design that can find all or the first r matches in a packet filter set. The second architecture is a novel partitioning scheme based on filter intersection properties allowing us to use off-the-shelf TCAMs for multi-match packet classification. Our classifier engine finds all matches in exactly one conventional TCAM cycle while reducing the power consumption by at least two orders of magnitude, which is far better than the existing hardware based designs.

Network Intrusion Detection Systems (NIDS) monitor network traffic to detect attacks or unauthorized activities. Traditional NIDSes search for patterns that match typical network compromise or remote hacking attempts. However, newer networking applications require finding the frequently repeated strings in a packet stream for further investigation of potential attack attempts. Finding frequently repeated strings within a given time frame of the packet stream has been quite efficient to detect polymorphic worm outbreaks. A novel real-time worm outbreak detection system using two-phase hashing and monitoring repeated common substrings is proposed in this article. We use the concept of shared counters to minimize the memory cost while efficiently sifting through suspicious strings. The worm outbreak system has been prototyped on Altera Stratix FPGA. We have tested the system for various settings and packet stream sizes. Experimental results verify that our system can support line speed of gigabit-rates with negligible false positive and negative rates.

This paper introduces a new basic building block based on Non-deterministic Finite Automata (NFA) hardware implementation to support complex constraint repetitions in regular expressions. This block is a customized counter capable of handling any type of constraint repetition, applicable to any sub-regular expression. We also apply optimization techniques to reduce the area and improve the overall performance.

Recent network intrusion detection systems (NIDS) use regular expressions to represent suspicious or malicious character sequences in packet payloads in a more efficient way. This paper introduces a new basic building block based on Non- deterministic Finite Automata (NFA) hardware implementation to support complex constraint repetitions in regular expressions. This block is a customized counter capable of handling any type of constraint repetition, applicable to any sub-regular expression. We also introduce optimization techniques to reduce the area and improve the overall performance. We have examined SNORT IDS regular expressions by taking advantage of the basic NFA building blocks, our proposed counting block and our proposed optimization techniques. We report experimental results for our architecture that verify area saving and performance improvement.

Analog and digital circuits are both prone to failure due to transient upsets, variations, etc. Redundancy techniques, such as N-tuple Modular Redundancy, has been widely used to correct faulty behavior of components and achieve high reliability for digital circuits, whereas, not much has been done on the analog side. In this paper, we propose a redundancy based fault-tolerant methodology to design a highly reliable analog to digital converters (ADC). Our methodology employs redundant analog blocks and chooses the best result using an innovative analog voter. Experimental results are reported to verify the concepts, measure the systempsilas reliability and tradeoff reliability versus cost and power.

A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions: 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the patterns generated by LT-LFSR with negligible impact on test length. The experimental results for the ISCAS'85 and '89 benchmarks confirm up to 77 percent and 49 percent reduction in average and peak power, respectively.

In this paper, we propose a distributed voting strategy to design a robust NMR system. We show that using inexpensive current-based drivers and buffers, we can completely eliminate the centralized voter unit and do the majority voting among N modules in a distributed fashion. Our strategy achieves high reliability that is vital for future nano systems in which high defect rate is expected. Experimental results are also reported to verify the concept, clarify the design procedure and measure the system's reliability.

In this paper, efficient clock delayed domino logic with variable strength voltage keeper is proposed. The variable strength of the keeper is achieved through applying two different body biases to the keeper. The circuits used to generate the body biases are called capacitive body bias generator and cross-coupled capacitive body bias generator. Compared to a previous work, the body bias generator circuits presented in this paper are simpler and do not require double or triple power supply while consuming less area and power. To show the efficiency of the proposed technique, the implementation of a carry generator circuit by the proposed techniques and the previous work are compared. The simulation results for standard CMOS technologies of 0.18 mum and 70 nm show considerable improvements in terms of power and power delay product. In addition, the proposed technique shows much less temperature dependence when compared to that of previous work

Most conventional packet classifiers find the highest priority filter that matches the packet. However, new networking applications such as network intrusion detection systems (NIDS) and load balancers require all (or the first few) matching results in packet classification. A TCAM -based architecture optimized for multiple match search is introduced in this paper. We propose a renovated TCAM design that can find all or the first r matches in a packet filter set. Our scheme partitions the filter set and performs the multi-match search on one partition only. A VLSI implementation of our classifier in 0.18 mum technology can achieve speed that is 1-2 order of magnitude higher than software based approaches. Power consumption is reduced by 40% which is far better than the conventional hardware based multi-match designs.

In an effort to substantially reduce the relatively high chip testing time, an application specific protocol/network named Test Area Network (TAN) is proposed based on the open standard suggestion for automatic test equipment. TAN architecture speeds up testing manifold and thus reduces the overall test cost significantly. The advantages of the proposed architecture come from the radically new idea of using packet switched network as the mode of communication between test equipment and tens of device under test.

A novel reconfigurable content addressable memory, called RCAM, is proposed that supports on-the-fly reconfiguration between CAM and TCAM. The area overhead of the proposed RCAM cell is only 5.6% when compared to conventional TCAM. This overhead is compensated by area saving due to removal of the priority encoder. Other features of our architecture include reconfigurability, and better overall performance and power. To achieve these we incorporated two novel techniques: (i) a hybrid CAM/TCAM architecture that allows user to pre-define CAM/TCAM cell behavior in each bit or word position and ultimately curtail the overall power consumptions of memory unit: and (ii) a wired-AND technique by which we can completely eliminate the sorting requirement and thus significantly reduce the update time. A 4 Kb RCAM architecture was implemented using 0.18 mum CMOS technology. The simulations indicate a search time of 6.15 ns, i.e. capability of handling about five OC-192 at wire speed.

As device technology progresses toward 45nm and beyond, the fidelity of the process parameter modeling becomes questionable. In this paper we propose the concept of process variation (PV) testing. This is achieved by applying an innovative fault model and test methodology that uses PV sensing circuitry and frequency domain analysis. Rather than pinpointing the variation of different parameters, our architecture looks at the effect of PV in a chip indirectly and collectively. The novelty of this architecture is in shifting the strategy of VLSI testing to frequency domain by using a distributed network of frequency-sensitive circuits such as ring oscillators. This provides an intrinsic advantage by minimizing the effect of noise (signal integrity loss, crosstalk, IR drop, etc.) and by using the powerful concept of digital signal processing for test analysis. The test architecture does not interfere with the rest of the circuit thus providing freedom to tune accuracy of the PV test by choosing the proper number and type of oscillators

An optimized Ternary CAM concept is introduced for the hardware search engines in high-speed Internet routers. Our design employs w + 1 RAM bits to store a word of size w, whereas a conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8-bit cluster is designed out of 9 SRAM bits, used as the basic building block of our Prefix-CAM (PCAM) structure. Four such clusters merge to store a 32-bit IPv4 prefix, thus, configuring a PCAM suitable for Internet packet forwarding. This PCAM module employs 48% less SRAM cells and a total of 22% less transistors plus 50% less address decode interconnects compared to a conventional TCAM, for equal storage size and equal functionality. We show that PCAM can be employed for multifield packet classification. Other factors, such as lookup speed and power dissipation, are not adversely affected.

This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within randomtest pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns and bits. LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures. The experimental results for ISCAS’85 and ’89 benchmarks, con- firm up to 77% and 49% reduction in average and peak power, respectively.

A novel low power ripple-precharge ternary CAM (RP-TCAM) architecture is proposed for applications in longest prefix matching tasks. The main motivation behind this research is to reduce the dynamic power consumption in TCAM due to frequent charging and discharging of the highly capacitive match line. This issue is addressed by exploiting the fact that when we compare only the first four bits of incoming packet's destination address we can identify up to 80% mismatches in the forwarding table. A selective precharge scheme was devised exploiting the above fact wherein the match line is charged only when there is an exact match in the first four bits of TCAM word, thereby significantly reducing the number of transitions in the match line. The parasitics for simulation were extracted from the layout implemented for a 64 /spl times/ 32 RP-TCAM architecture using 0.18/spl mu/m technology. This structure has 1.71% less area and 80% less power when compared to the conventional TCAM of equal storage size and functionality. Our RP-TCAM architecture has a search time of 1.86ns.

Noise on the power-supply lines has become a critical factor especially in low-voltage designs as excessive noise may cause intermittent functional error and eventually system failure. Having a realistic picture of the worst case noise throughout a chip is important as we can devise a remedy to alleviate the problem before it becomes too late. This paper provides a fast automatic pattern generation method to estimate the maximum simultaneous switching noise for a non-embedded core. When the cores are integrated within a SoC, the combined noise is far from a simple additive behavior. We offer a heuristic to estimate the power-supply noise in core-based SoCs. This heuristic can be employed to minimize the number of power-supply lines/pins while keeping the noise under control. The experiments using ISCAS'85 benchmarks verify that our power-supply noise methodology is fairly fast and accurate and can be used for effective power-supply distribution

This paper presents an automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 /spl rarr/ 1 and 1 /spl rarr/ 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns was verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum power supply noise.

We present a comprehensive and flexible test scheduling environment, called FITS, for testing core-based system-on-chips. Our environment prevents formation of hot spots during test. It also allows trade-off among test time, test access mechanism, power, and test controller/resource constraints. The basic strategy is to use power profile over application time and structural grids of nonembedded cores to find the best test schedule of their test pattern subsets while satisfying the constraints. As case studies, four integer linear programming formulations, corresponding to four power approximation models, are extensively analyzed. With proper setting of the weights and constraints, optimized results can be obtained quickly for each of the four power approximation models. Extensive experimental results are reported based on ISCAS '89 benchmarks and verify the efficiency and flexibility of the FITS environment.

This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan test applications. This is achieved by using run-length encoding followed by Huffman encoding. This combination is especially effective when the percentage of don't cares in a test set is high, which is a common case in today's large systems-on-chips (SoCs). Our analysis and experimental results confirm that achieving up to an 89% compression ratio and a 93% scan-in power reduction is possible for scan-testable circuits such as ISCAS89 benchmarks.

We present a search algorithm implementable by a parallel architecture based on partitioned forwarding table. This scheme effectively reduces the complexity of finding "the longest prefix match" problem to "a prefix match" problem. The main feature of this algorithm is twofold. First, it advocates intelligent partitioning of the forwarding table to enhance and parallelize the lookup operation. Second, it takes advantage of ternary CAM to achieve low lookup time. The resulting architecture has better throughput and much better update time than the traditional TCAM. Our experimental results show that such features can significantly elevate the flexibility and scalability of the next generation packet processing devices.

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.

This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single- or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

We propose a novel approach for IP packet forwarding based on a new ternary content addressable memory configuration. Our design is an efficient hardware solution for the longest prefix matching problem in Internet routers. Our scheme segregates the encompassing prefixes into a separate, practically small TCAM module. Consequently, the remaining prefixes, that often conform to more than 92% of the lookup table, form a disjoint set. The big TCAM module that accommodates this set has a simplified architecture, with no priority encoder. Our architecture has lower update complexity, lower cost and shorter search time, compared to the conventional TCAM structure.

In this paper, a new approach for reducing the subthreshold leakage current of digital circuits is proposed. It does not use a multi-threshold process technique which is more expensive. The technique which makes to use of a new variable supply voltage oscillator, combines the ideas of both Standby Leakage Control Using Transistor Stacks (SRB) and variable threshold (VT) methods. In this technique compared to the Leakage Control Using Transistor Stacks method, the subthreshold current decreases three times. In addition, leakage current monitor (LCM) and its related circuits which are used in VT techniques are not required here. This makes the proposed technique more power and area efficient.

An optimized ternary CAM concept is introduced for application in the longest prefix matching tasks of the Internet search engines. It employs w+1 RAM bits for a word of size w. A conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8 bit prefix-CAM cluster is designed out of 9 SRAM bits, four of which merge to store a 32-bit IPv4 prefix. A complete prefix-CAM module employs 22% less transistors than a conventional TCAM, for equal storage size and equal functionality. We confirm the 22% area saving by implementing the layouts for prefix-CAM and TCAM words. Our design also reduces interconnect area by reducing address decode lines.

This work presents a method of creating a true/complement pattern set of optimal size that satisfies simultaneous switching limit constraints. This method is an improvement over previous methods in that it has better runtime characteristics as well as the ability to handle additional scenarios. It can produce safe initial vectors, produce vectors that consider switching limits by device rather than globally, and reduce (or eliminate) the number of morph vectors required.

As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.

In this paper, we introduce the idea of using packet switched network as the mode of communication between automatic test equipment and the VLSI chip under test in a multisite ATE architecture. We show that our architecture, which we refer to as test area network reduces the complexity and time involved in testing tens of chips at a time. To increase the ATE utilization, we distribute a portion of ATE's task of signature verification to the intelligent test-heads, which are now capable of applying patterns and verifying signatures produced by the chip being tested. Our analysis and empirical results indicate a speed up of 4 to 10 by using existing network infrastructure.

We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of nonembedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation.

As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. Here, we propose a new fault model, called multiple transition, and its corresponding test pattern generation mechanism. We also extend the conventional boundary scan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant.

As the technology is shrinking toward 50 nm and the working frequency is going into the multi Gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we extend the conventional boundary scan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant. We also propose a simple yet efficient compression scheme that can be employed by an ATE to minimize the scan-in delivery time.

This paper aims at analysis of signal integrity for the purpose of testing high speed interconnects. This requires taking into account the effect of inputs as well as parasitic RLC elements of the interconnect. To improve the analysis/simulation time in integrity fault testing, we use reduced-order modeling that essentially performs the analysis in the frequency domain. To demonstrate the generality and usefulness of our method, we also discuss its application for test pattern generation targeting signal integrity loss.

In this paper, we present a fully scalable architecture for IP packet forwarding engines used in router line cards and other network equipment. Our conceptually sliced architecture can be replicated to increase the number of ports or deal with larger lookup tables. We show empirical evidence that, using our architecture, the expansion requires very limited glue logic and does not deteriorate the performance. Such a scalability feature is especially vital to satisfy the Internet's huge appetite for large routing tables, increased traffic, higher speed and the migration to IPv6.

We present an efficient IP packet forwarding methodology and architecture. This is achieved by partitioning the lookup table into smaller ones for each output port and allowing a forwarding engine to process them in parallel. This effectively reduces the complexity of the problem of finding "the longest prefix match" to that of finding "the first prefix match".

A reconfigurable memory architecture and lookup technique for IP packet forwarding engines is presented. This is a flexible technique that significantly elevates the scalability of the next generation network processors and other packet processing equipments, especially in terms of increased routing table sizes, increased traffic and bandwidth, increased frequency of route updates, and migration to IPv6.

Presents a systematic approach for utilizing the microprocessor capabilities in testing the SoC's interconnects for signal integrity. We propose a graph representation of SoC/interconnects to minimize the test time while performing thorough test of interconnects for integrity loss. This is achieved by using the embedded microprocessor for two main tasks: (1) to dynamically determine the best test plan based on resource constraints and the test results from previous sessions, and (2) to execute the test plan, that includes test generation/delivery, signature analysis/diagnosis and process control.

In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.

Presents a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.

Real defects (e.g., resistive stuck at or bridging faults) in very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate level. Our method uses Takagi-Sugeno (TS) fuzzy system to accurately model digital VLSI circuits and produces much more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test-pattern statistics for the ISCAS85 benchmarks.

The rising level of complexity and speed of SoC makes it increasingly vital to test adequately the system for signal integrity. Voltage overshoot is one of the integrity factors that has not been sufficiently addressed for the purpose of testing and reliability. Overshoots are known to inject hot-carriers into the gate oxide and cause permanent degradation of MOSFET transistors' performance. This performance degradation creates a serious reliability concern. Unfortunately, accurate parasitic extraction and simulation to detect the interconnect problems is very time consuming and very sensitive to the circuit characteristics and thus is not practical for large SoC. This paper presents a built-in chip methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. This built-in test strategy does not require external probing or signal waveform monitoring. Instead, the overshoot detector cells monitor signals received by a core (e.g. from the system bus) and record the occurrence of overshoots over a period of operation. The overshoot information accumulated by these cells can be compressed and scanned out efficiently And inexpensively for final quality grading, reliability analysis and diagnosis.

In this paper, we present an accurate delay-estimation algorithm at the register-transfer level. We study three important sources of false paths in register-transfer-level (RTL) structures, i.e., 1) resource binding; 2) interdependent conditions; and 3) datapath-controller path mismatching. The existence and creation of such paths and their effects in delay analysis are discussed. We show that in a RTL datapath structure the accuracy of the delay estimators is affected by the existence of false paths. Specifically, the accuracy drops significantly for structures synthesized from condition-dominated behaviors. We propose a mechanism to efficiently avoid false paths in delay analysis. This is achieved by introducing the propagation delay graph (PDG), whose traversal for delay analysis is equivalent to the traversal of sensitizable paths in the datapath. Comparison with the timing verifier in commercial computer-aided design (CAD) tools, show that estimated delays are within 14% accuracy of those reported by CAD tools.

Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deep-submicron high-speed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low integrity signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.

Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. We present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips.

We present a methodology to detect and measure the signal overshoots occurring on the interconnects of high-speed system-on-chips. Overshoots are known to inject hot-carriers into the gate oxide which cause permanent degradation of MOSFET transistor performance over time. We propose a built-in chip mechanism to detect overshoots, collect the occurrence information and scan them out efficiently and inexpensively for built-in self-test, reliability analysis and diagnosis.

In systems consisting of interacting datapaths and controllers and utilizing built-in self test (BIST), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This work facilitates the testing of datapath/controller pairs in an integrated fashion . The key to the approach is the addition of logic to the system that interacts with the existing controller to push the effects of controller faults into the data flow , so that they can be observed at the datapath registers rather than directly at the controller outputs. The result is to reduce the BIST overhead over what is needed if the datapath and controller are tested independently, and to allow a more complete test of the interface between datapath and controller, including the faults that do not manifest themselves in isolation. Fault coverage and overhead results are given for four example circuits.

Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.

A method for high level synthesis-for-testability of controller-datapath pairs that use gated clocks is developed. It uses a register allocation technique that improves the observability of the controller through the datapath, and takes advantage of the unique testability properties of one-hot-encoded controllers. The resulting controller can be fully tested without isolating it from the system. Area, fault coverage, and power consumption are reported for three example circuits.

In systems consisting of interacting datapaths and controllers, the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This is not possible when the controller-datapath pair is an embedded system designed as a hard core. This work facilitates the testing of controller-datapath pairs in a truly integrated fashion. The key to the approach is a careful examination of the types of gate level stuck-at faults that can occur within the controller. A class of faults that are undetectable in an integrated test by traditional means is identified. These faults create faulty but functional circuits. The effect of these faults on power consumption is explored, and a method based on power analysis is given for detecting these faults. Analysis is given for three example systems.

We present an optimization method that complies with IEEE P1500 draft standard and deals with modeling and design of the test access mechanism for the SoCs. The basic goal is to develop a global design for the test methodology and optimization technique for testing a core-based SoC in its entirety. We propose an ILP formulation to minimize the hardware cost or the overall access time which also produces the test access schedule.

This paper presents new algorithms for the scheduling and allocation phases in high-level synthesis under time and resource constraints. This is achieved by formulating these problems in terms of Liapunov's stability theorem using a transformation technique between the design space and the dynamic system space. These algorithms are based on moves in the design space, which correspond to the moves toward the equilibrium point in the dynamic system space. The scheduling algorithm (MFS) takes care of mutually exclusive operations, loop folding, multicycle operations, chained operations, and pipelining (structural and functional). The mixed scheduling-allocation algorithm (MFSA) can handle all of the above scheduling applications as well as simultaneously performing allocation of functional units, registers, and interconnects while minimizing the overall cost.

The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip (SOC). The novel feature of the approach is the use an embedded microprocessor/memory pair to test the remaining components of the SOC. Test data is downloaded using DMA techniques directly into memory while the microprocessor uses the test data to test the core. The test results are tranferred to a MISR for evaluation. The approach has several important advantages over conventional ATPG such as achieving at-speed testing, not limiting the chip speed to the tester speed during test and achieving great exibility since most of the testing process is based on software. Experimental results on an example system are discussed. 1

This work facilitates the testing of datapath-controller pairs in an integrated fashion, with datapath and controller tested together in a single test session. Such an approach requires less test overhead than an approach that isolates datapath and controller from each other during test. The ability to do an integrated test is especially important when testing core-based embedded systems. The key to the approach is a careful examination of the relationship between techniques for controller synthesis and the types of gate level controller faults that can occur. A method for controller synthesis is outlined that results in a fully testable controller, so that full fault coverage of the controller can be achieved without any need for isolation during test.

This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported.

We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering with the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.

We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a "bypass" mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem.

In systems consisting of interacting datapaths and controllersand utilizing built-in self test (BIST), the datapaths andcontrollers are traditionally tested separately by isolatingeach component from the environment of the system duringtest.This work facilitates the testing of datapath-controllerpairs in an integrated fashion.The key to the approach isthe addition of logic to the system that interacts with theexisting controller to push the effects of controller faults intothe data flow, so that they can be observed at the datapathregisters rather than directly at the controller outputs.Theresult is to reduce the BIST overhead over what is neededif the datapath and controller are tested independently, andto allow a more complete test of the interface between datapathand controller.Fault coverage and overhead resultsare given for four example circuits.

This paper presents an effective technique of low power design for RTL circuits and microarchitectures. The basis of this technique is: a) to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles; b) to partition the circuit into disjoint modules and assign each module to a distinct clock with frequency f=n. However, the overall effective frequency of the circuit remains f the single clock frequency. The results show that our multiple clocking scheme provides more effective power management (power savings up to 50%) at the RTL in comparison to conventional power management techniques based on gated clocks. 1. Introduction A major feature of currently proliferating portable applications is their requirement for low power consumption because they use battery voltage. Considering "power" rather than area or speed as the main optimization factor requires a second look at the entire VLSI design technologies, techniques, archi...

This paper presents a fast and efficient algorithm to estimate the area cost of a given RTL datapath.This is achieved by considering

A new method of redesign at the registertransfer level using a transformational process is proposed. The redesign approach by reallocation takes into consideration ALU and interconnect cost in addition to layout area estimation. The idea is to start with a design, possibly generated by a synthesis system, and iteratively improve it by means of the reallocation process. The method is based on a set of reallocation transformations along with systematic strategies as to how to apply them together with a layout estimation model. I. INTRODUCTION High Level Synthesis is the automatic generation of a register transfer level (RTL) design (datapath/controller) from a behavioral level description, subject to a set of constraints. The datapath is usually synthesized in two steps --- operation scheduling and resource allocation. One of the main tasks of high-level synthesis is to find the structure that best meets the constraints while minimizing other costs [6]. The actual circuit layout can be...